1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 */ 5 6 /** 7 * DOC: VC4 CRTC module 8 * 9 * In VC4, the Pixel Valve is what most closely corresponds to the 10 * DRM's concept of a CRTC. The PV generates video timings from the 11 * encoder's clock plus its configuration. It pulls scaled pixels from 12 * the HVS at that timing, and feeds it to the encoder. 13 * 14 * However, the DRM CRTC also collects the configuration of all the 15 * DRM planes attached to it. As a result, the CRTC is also 16 * responsible for writing the display list for the HVS channel that 17 * the CRTC will use. 18 * 19 * The 2835 has 3 different pixel valves. pv0 in the audio power 20 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the 21 * image domain can feed either HDMI or the SDTV controller. The 22 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for 23 * SDTV, etc.) according to which output type is chosen in the mux. 24 * 25 * For power management, the pixel valve's registers are all clocked 26 * by the AXI clock, while the timings and FIFOs make use of the 27 * output-specific clock. Since the encoders also directly consume 28 * the CPRMAN clocks, and know what timings they need, they are the 29 * ones that set the clock. 30 */ 31 32 #include <linux/clk.h> 33 #include <linux/component.h> 34 #include <linux/of_device.h> 35 #include <linux/pm_runtime.h> 36 37 #include <drm/drm_atomic.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_atomic_uapi.h> 40 #include <drm/drm_fb_cma_helper.h> 41 #include <drm/drm_print.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_vblank.h> 44 45 #include "vc4_drv.h" 46 #include "vc4_hdmi.h" 47 #include "vc4_regs.h" 48 49 #define HVS_FIFO_LATENCY_PIX 6 50 51 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset)) 52 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset)) 53 54 static const struct debugfs_reg32 crtc_regs[] = { 55 VC4_REG32(PV_CONTROL), 56 VC4_REG32(PV_V_CONTROL), 57 VC4_REG32(PV_VSYNCD_EVEN), 58 VC4_REG32(PV_HORZA), 59 VC4_REG32(PV_HORZB), 60 VC4_REG32(PV_VERTA), 61 VC4_REG32(PV_VERTB), 62 VC4_REG32(PV_VERTA_EVEN), 63 VC4_REG32(PV_VERTB_EVEN), 64 VC4_REG32(PV_INTEN), 65 VC4_REG32(PV_INTSTAT), 66 VC4_REG32(PV_STAT), 67 VC4_REG32(PV_HACT_ACT), 68 }; 69 70 static unsigned int 71 vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel) 72 { 73 struct vc4_hvs *hvs = vc4->hvs; 74 u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel)); 75 /* Top/base are supposed to be 4-pixel aligned, but the 76 * Raspberry Pi firmware fills the low bits (which are 77 * presumably ignored). 78 */ 79 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3; 80 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3; 81 82 return top - base + 4; 83 } 84 85 static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc, 86 bool in_vblank_irq, 87 int *vpos, int *hpos, 88 ktime_t *stime, ktime_t *etime, 89 const struct drm_display_mode *mode) 90 { 91 struct drm_device *dev = crtc->dev; 92 struct vc4_dev *vc4 = to_vc4_dev(dev); 93 struct vc4_hvs *hvs = vc4->hvs; 94 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 95 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state); 96 unsigned int cob_size; 97 u32 val; 98 int fifo_lines; 99 int vblank_lines; 100 bool ret = false; 101 102 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 103 104 /* Get optional system timestamp before query. */ 105 if (stime) 106 *stime = ktime_get(); 107 108 /* 109 * Read vertical scanline which is currently composed for our 110 * pixelvalve by the HVS, and also the scaler status. 111 */ 112 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel)); 113 114 /* Get optional system timestamp after query. */ 115 if (etime) 116 *etime = ktime_get(); 117 118 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 119 120 /* Vertical position of hvs composed scanline. */ 121 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE); 122 *hpos = 0; 123 124 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 125 *vpos /= 2; 126 127 /* Use hpos to correct for field offset in interlaced mode. */ 128 if (vc4_hvs_get_fifo_frame_count(hvs, vc4_crtc_state->assigned_channel) % 2) 129 *hpos += mode->crtc_htotal / 2; 130 } 131 132 cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc_state->assigned_channel); 133 /* This is the offset we need for translating hvs -> pv scanout pos. */ 134 fifo_lines = cob_size / mode->crtc_hdisplay; 135 136 if (fifo_lines > 0) 137 ret = true; 138 139 /* HVS more than fifo_lines into frame for compositing? */ 140 if (*vpos > fifo_lines) { 141 /* 142 * We are in active scanout and can get some meaningful results 143 * from HVS. The actual PV scanout can not trail behind more 144 * than fifo_lines as that is the fifo's capacity. Assume that 145 * in active scanout the HVS and PV work in lockstep wrt. HVS 146 * refilling the fifo and PV consuming from the fifo, ie. 147 * whenever the PV consumes and frees up a scanline in the 148 * fifo, the HVS will immediately refill it, therefore 149 * incrementing vpos. Therefore we choose HVS read position - 150 * fifo size in scanlines as a estimate of the real scanout 151 * position of the PV. 152 */ 153 *vpos -= fifo_lines + 1; 154 155 return ret; 156 } 157 158 /* 159 * Less: This happens when we are in vblank and the HVS, after getting 160 * the VSTART restart signal from the PV, just started refilling its 161 * fifo with new lines from the top-most lines of the new framebuffers. 162 * The PV does not scan out in vblank, so does not remove lines from 163 * the fifo, so the fifo will be full quickly and the HVS has to pause. 164 * We can't get meaningful readings wrt. scanline position of the PV 165 * and need to make things up in a approximative but consistent way. 166 */ 167 vblank_lines = mode->vtotal - mode->vdisplay; 168 169 if (in_vblank_irq) { 170 /* 171 * Assume the irq handler got called close to first 172 * line of vblank, so PV has about a full vblank 173 * scanlines to go, and as a base timestamp use the 174 * one taken at entry into vblank irq handler, so it 175 * is not affected by random delays due to lock 176 * contention on event_lock or vblank_time lock in 177 * the core. 178 */ 179 *vpos = -vblank_lines; 180 181 if (stime) 182 *stime = vc4_crtc->t_vblank; 183 if (etime) 184 *etime = vc4_crtc->t_vblank; 185 186 /* 187 * If the HVS fifo is not yet full then we know for certain 188 * we are at the very beginning of vblank, as the hvs just 189 * started refilling, and the stime and etime timestamps 190 * truly correspond to start of vblank. 191 * 192 * Unfortunately there's no way to report this to upper levels 193 * and make it more useful. 194 */ 195 } else { 196 /* 197 * No clue where we are inside vblank. Return a vpos of zero, 198 * which will cause calling code to just return the etime 199 * timestamp uncorrected. At least this is no worse than the 200 * standard fallback. 201 */ 202 *vpos = 0; 203 } 204 205 return ret; 206 } 207 208 void vc4_crtc_destroy(struct drm_crtc *crtc) 209 { 210 drm_crtc_cleanup(crtc); 211 } 212 213 static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format) 214 { 215 const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc); 216 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc); 217 struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev); 218 u32 fifo_len_bytes = pv_data->fifo_depth; 219 220 /* 221 * Pixels are pulled from the HVS if the number of bytes is 222 * lower than the FIFO full level. 223 * 224 * The latency of the pixel fetch mechanism is 6 pixels, so we 225 * need to convert those 6 pixels in bytes, depending on the 226 * format, and then subtract that from the length of the FIFO 227 * to make sure we never end up in a situation where the FIFO 228 * is full. 229 */ 230 switch (format) { 231 case PV_CONTROL_FORMAT_DSIV_16: 232 case PV_CONTROL_FORMAT_DSIC_16: 233 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX; 234 case PV_CONTROL_FORMAT_DSIV_18: 235 return fifo_len_bytes - 14; 236 case PV_CONTROL_FORMAT_24: 237 case PV_CONTROL_FORMAT_DSIV_24: 238 default: 239 /* 240 * For some reason, the pixelvalve4 doesn't work with 241 * the usual formula and will only work with 32. 242 */ 243 if (crtc_data->hvs_output == 5) 244 return 32; 245 246 /* 247 * It looks like in some situations, we will overflow 248 * the PixelValve FIFO (with the bit 10 of PV stat being 249 * set) and stall the HVS / PV, eventually resulting in 250 * a page flip timeout. 251 * 252 * Displaying the video overlay during a playback with 253 * Kodi on an RPi3 seems to be a great solution with a 254 * failure rate around 50%. 255 * 256 * Removing 1 from the FIFO full level however 257 * seems to completely remove that issue. 258 */ 259 if (!vc4->hvs->hvs5) 260 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1; 261 262 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX; 263 } 264 } 265 266 static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc, 267 u32 format) 268 { 269 u32 level = vc4_get_fifo_full_level(vc4_crtc, format); 270 u32 ret = 0; 271 272 ret |= VC4_SET_FIELD((level >> 6), 273 PV5_CONTROL_FIFO_LEVEL_HIGH); 274 275 return ret | VC4_SET_FIELD(level & 0x3f, 276 PV_CONTROL_FIFO_LEVEL); 277 } 278 279 /* 280 * Returns the encoder attached to the CRTC. 281 * 282 * VC4 can only scan out to one encoder at a time, while the DRM core 283 * allows drivers to push pixels to more than one encoder from the 284 * same CRTC. 285 */ 286 struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc, 287 struct drm_crtc_state *state) 288 { 289 struct drm_encoder *encoder; 290 291 WARN_ON(hweight32(state->encoder_mask) > 1); 292 293 drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) 294 return encoder; 295 296 return NULL; 297 } 298 299 static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc) 300 { 301 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 302 303 /* The PV needs to be disabled before it can be flushed */ 304 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN); 305 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR); 306 } 307 308 static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encoder, 309 struct drm_atomic_state *state) 310 { 311 struct drm_device *dev = crtc->dev; 312 struct vc4_dev *vc4 = to_vc4_dev(dev); 313 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 314 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 315 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc); 316 struct drm_crtc_state *crtc_state = crtc->state; 317 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 318 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; 319 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 320 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || 321 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); 322 u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; 323 u8 ppc = pv_data->pixels_per_clock; 324 bool debug_dump_regs = false; 325 326 if (debug_dump_regs) { 327 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev); 328 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n", 329 drm_crtc_index(crtc)); 330 drm_print_regset32(&p, &vc4_crtc->regset); 331 } 332 333 vc4_crtc_pixelvalve_reset(crtc); 334 335 CRTC_WRITE(PV_HORZA, 336 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc, 337 PV_HORZA_HBP) | 338 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc, 339 PV_HORZA_HSYNC)); 340 341 CRTC_WRITE(PV_HORZB, 342 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc, 343 PV_HORZB_HFP) | 344 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc, 345 PV_HORZB_HACTIVE)); 346 347 CRTC_WRITE(PV_VERTA, 348 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 349 PV_VERTA_VBP) | 350 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 351 PV_VERTA_VSYNC)); 352 CRTC_WRITE(PV_VERTB, 353 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 354 PV_VERTB_VFP) | 355 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); 356 357 if (interlace) { 358 CRTC_WRITE(PV_VERTA_EVEN, 359 VC4_SET_FIELD(mode->crtc_vtotal - 360 mode->crtc_vsync_end - 1, 361 PV_VERTA_VBP) | 362 VC4_SET_FIELD(mode->crtc_vsync_end - 363 mode->crtc_vsync_start, 364 PV_VERTA_VSYNC)); 365 CRTC_WRITE(PV_VERTB_EVEN, 366 VC4_SET_FIELD(mode->crtc_vsync_start - 367 mode->crtc_vdisplay, 368 PV_VERTB_VFP) | 369 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); 370 371 /* We set up first field even mode for HDMI. VEC's 372 * NTSC mode would want first field odd instead, once 373 * we support it (to do so, set ODD_FIRST and put the 374 * delay in VSYNCD_EVEN instead). 375 */ 376 CRTC_WRITE(PV_V_CONTROL, 377 PV_VCONTROL_CONTINUOUS | 378 (is_dsi ? PV_VCONTROL_DSI : 0) | 379 PV_VCONTROL_INTERLACE | 380 VC4_SET_FIELD(mode->htotal * pixel_rep / 2, 381 PV_VCONTROL_ODD_DELAY)); 382 CRTC_WRITE(PV_VSYNCD_EVEN, 0); 383 } else { 384 CRTC_WRITE(PV_V_CONTROL, 385 PV_VCONTROL_CONTINUOUS | 386 (is_dsi ? PV_VCONTROL_DSI : 0)); 387 } 388 389 if (is_dsi) 390 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); 391 392 if (vc4->hvs->hvs5) 393 CRTC_WRITE(PV_MUX_CFG, 394 VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP, 395 PV_MUX_CFG_RGB_PIXEL_MUX_MODE)); 396 397 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | 398 vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) | 399 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | 400 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | 401 PV_CONTROL_CLR_AT_START | 402 PV_CONTROL_TRIGGER_UNDERFLOW | 403 PV_CONTROL_WAIT_HSTART | 404 VC4_SET_FIELD(vc4_encoder->clock_select, 405 PV_CONTROL_CLK_SELECT)); 406 407 if (debug_dump_regs) { 408 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev); 409 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n", 410 drm_crtc_index(crtc)); 411 drm_print_regset32(&p, &vc4_crtc->regset); 412 } 413 } 414 415 static void require_hvs_enabled(struct drm_device *dev) 416 { 417 struct vc4_dev *vc4 = to_vc4_dev(dev); 418 struct vc4_hvs *hvs = vc4->hvs; 419 420 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) != 421 SCALER_DISPCTRL_ENABLE); 422 } 423 424 static int vc4_crtc_disable(struct drm_crtc *crtc, 425 struct drm_encoder *encoder, 426 struct drm_atomic_state *state, 427 unsigned int channel) 428 { 429 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 430 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 431 struct drm_device *dev = crtc->dev; 432 struct vc4_dev *vc4 = to_vc4_dev(dev); 433 int ret; 434 435 CRTC_WRITE(PV_V_CONTROL, 436 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN); 437 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); 438 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); 439 440 /* 441 * This delay is needed to avoid to get a pixel stuck in an 442 * unflushable FIFO between the pixelvalve and the HDMI 443 * controllers on the BCM2711. 444 * 445 * Timing is fairly sensitive here, so mdelay is the safest 446 * approach. 447 * 448 * If it was to be reworked, the stuck pixel happens on a 449 * BCM2711 when changing mode with a good probability, so a 450 * script that changes mode on a regular basis should trigger 451 * the bug after less than 10 attempts. It manifests itself with 452 * every pixels being shifted by one to the right, and thus the 453 * last pixel of a line actually being displayed as the first 454 * pixel on the next line. 455 */ 456 mdelay(20); 457 458 if (vc4_encoder && vc4_encoder->post_crtc_disable) 459 vc4_encoder->post_crtc_disable(encoder, state); 460 461 vc4_crtc_pixelvalve_reset(crtc); 462 vc4_hvs_stop_channel(vc4->hvs, channel); 463 464 if (vc4_encoder && vc4_encoder->post_crtc_powerdown) 465 vc4_encoder->post_crtc_powerdown(encoder, state); 466 467 return 0; 468 } 469 470 static struct drm_encoder *vc4_crtc_get_encoder_by_type(struct drm_crtc *crtc, 471 enum vc4_encoder_type type) 472 { 473 struct drm_encoder *encoder; 474 475 drm_for_each_encoder(encoder, crtc->dev) { 476 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 477 478 if (vc4_encoder->type == type) 479 return encoder; 480 } 481 482 return NULL; 483 } 484 485 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc) 486 { 487 struct drm_device *drm = crtc->dev; 488 struct vc4_dev *vc4 = to_vc4_dev(drm); 489 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 490 enum vc4_encoder_type encoder_type; 491 const struct vc4_pv_data *pv_data; 492 struct drm_encoder *encoder; 493 struct vc4_hdmi *vc4_hdmi; 494 unsigned encoder_sel; 495 int channel; 496 int ret; 497 498 if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node, 499 "brcm,bcm2711-pixelvalve2") || 500 of_device_is_compatible(vc4_crtc->pdev->dev.of_node, 501 "brcm,bcm2711-pixelvalve4"))) 502 return 0; 503 504 if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN)) 505 return 0; 506 507 if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN)) 508 return 0; 509 510 channel = vc4_hvs_get_fifo_from_output(vc4->hvs, vc4_crtc->data->hvs_output); 511 if (channel < 0) 512 return 0; 513 514 encoder_sel = VC4_GET_FIELD(CRTC_READ(PV_CONTROL), PV_CONTROL_CLK_SELECT); 515 if (WARN_ON(encoder_sel != 0)) 516 return 0; 517 518 pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc); 519 encoder_type = pv_data->encoder_types[encoder_sel]; 520 encoder = vc4_crtc_get_encoder_by_type(crtc, encoder_type); 521 if (WARN_ON(!encoder)) 522 return 0; 523 524 vc4_hdmi = encoder_to_vc4_hdmi(encoder); 525 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 526 if (ret) 527 return ret; 528 529 ret = vc4_crtc_disable(crtc, encoder, NULL, channel); 530 if (ret) 531 return ret; 532 533 /* 534 * post_crtc_powerdown will have called pm_runtime_put, so we 535 * don't need it here otherwise we'll get the reference counting 536 * wrong. 537 */ 538 539 return 0; 540 } 541 542 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, 543 struct drm_atomic_state *state) 544 { 545 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 546 crtc); 547 struct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state); 548 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, old_state); 549 struct drm_device *dev = crtc->dev; 550 551 drm_dbg(dev, "Disabling CRTC %s (%u) connected to Encoder %s (%u)", 552 crtc->name, crtc->base.id, encoder->name, encoder->base.id); 553 554 require_hvs_enabled(dev); 555 556 /* Disable vblank irq handling before crtc is disabled. */ 557 drm_crtc_vblank_off(crtc); 558 559 vc4_crtc_disable(crtc, encoder, state, old_vc4_state->assigned_channel); 560 561 /* 562 * Make sure we issue a vblank event after disabling the CRTC if 563 * someone was waiting it. 564 */ 565 if (crtc->state->event) { 566 unsigned long flags; 567 568 spin_lock_irqsave(&dev->event_lock, flags); 569 drm_crtc_send_vblank_event(crtc, crtc->state->event); 570 crtc->state->event = NULL; 571 spin_unlock_irqrestore(&dev->event_lock, flags); 572 } 573 } 574 575 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, 576 struct drm_atomic_state *state) 577 { 578 struct drm_crtc_state *new_state = drm_atomic_get_new_crtc_state(state, 579 crtc); 580 struct drm_device *dev = crtc->dev; 581 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 582 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, new_state); 583 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 584 585 drm_dbg(dev, "Enabling CRTC %s (%u) connected to Encoder %s (%u)", 586 crtc->name, crtc->base.id, encoder->name, encoder->base.id); 587 588 require_hvs_enabled(dev); 589 590 /* Enable vblank irq handling before crtc is started otherwise 591 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist(). 592 */ 593 drm_crtc_vblank_on(crtc); 594 595 vc4_hvs_atomic_enable(crtc, state); 596 597 if (vc4_encoder->pre_crtc_configure) 598 vc4_encoder->pre_crtc_configure(encoder, state); 599 600 vc4_crtc_config_pv(crtc, encoder, state); 601 602 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN); 603 604 if (vc4_encoder->pre_crtc_enable) 605 vc4_encoder->pre_crtc_enable(encoder, state); 606 607 /* When feeding the transposer block the pixelvalve is unneeded and 608 * should not be enabled. 609 */ 610 CRTC_WRITE(PV_V_CONTROL, 611 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN); 612 613 if (vc4_encoder->post_crtc_enable) 614 vc4_encoder->post_crtc_enable(encoder, state); 615 } 616 617 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc, 618 const struct drm_display_mode *mode) 619 { 620 /* Do not allow doublescan modes from user space */ 621 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { 622 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n", 623 crtc->base.id); 624 return MODE_NO_DBLESCAN; 625 } 626 627 return MODE_OK; 628 } 629 630 void vc4_crtc_get_margins(struct drm_crtc_state *state, 631 unsigned int *left, unsigned int *right, 632 unsigned int *top, unsigned int *bottom) 633 { 634 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); 635 struct drm_connector_state *conn_state; 636 struct drm_connector *conn; 637 int i; 638 639 *left = vc4_state->margins.left; 640 *right = vc4_state->margins.right; 641 *top = vc4_state->margins.top; 642 *bottom = vc4_state->margins.bottom; 643 644 /* We have to interate over all new connector states because 645 * vc4_crtc_get_margins() might be called before 646 * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state 647 * might be outdated. 648 */ 649 for_each_new_connector_in_state(state->state, conn, conn_state, i) { 650 if (conn_state->crtc != state->crtc) 651 continue; 652 653 *left = conn_state->tv.margins.left; 654 *right = conn_state->tv.margins.right; 655 *top = conn_state->tv.margins.top; 656 *bottom = conn_state->tv.margins.bottom; 657 break; 658 } 659 } 660 661 static int vc4_crtc_atomic_check(struct drm_crtc *crtc, 662 struct drm_atomic_state *state) 663 { 664 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 665 crtc); 666 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); 667 struct drm_connector *conn; 668 struct drm_connector_state *conn_state; 669 struct drm_encoder *encoder; 670 int ret, i; 671 672 ret = vc4_hvs_atomic_check(crtc, state); 673 if (ret) 674 return ret; 675 676 encoder = vc4_get_crtc_encoder(crtc, crtc_state); 677 if (encoder) { 678 const struct drm_display_mode *mode = &crtc_state->adjusted_mode; 679 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 680 681 if (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) { 682 vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 1000, 683 mode->clock * 9 / 10) * 1000; 684 } else { 685 vc4_state->hvs_load = mode->clock * 1000; 686 } 687 } 688 689 for_each_new_connector_in_state(state, conn, conn_state, 690 i) { 691 if (conn_state->crtc != crtc) 692 continue; 693 694 vc4_state->margins.left = conn_state->tv.margins.left; 695 vc4_state->margins.right = conn_state->tv.margins.right; 696 vc4_state->margins.top = conn_state->tv.margins.top; 697 vc4_state->margins.bottom = conn_state->tv.margins.bottom; 698 break; 699 } 700 701 return 0; 702 } 703 704 static int vc4_enable_vblank(struct drm_crtc *crtc) 705 { 706 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 707 708 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START); 709 710 return 0; 711 } 712 713 static void vc4_disable_vblank(struct drm_crtc *crtc) 714 { 715 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 716 717 CRTC_WRITE(PV_INTEN, 0); 718 } 719 720 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) 721 { 722 struct drm_crtc *crtc = &vc4_crtc->base; 723 struct drm_device *dev = crtc->dev; 724 struct vc4_dev *vc4 = to_vc4_dev(dev); 725 struct vc4_hvs *hvs = vc4->hvs; 726 u32 chan = vc4_crtc->current_hvs_channel; 727 unsigned long flags; 728 729 spin_lock_irqsave(&dev->event_lock, flags); 730 spin_lock(&vc4_crtc->irq_lock); 731 if (vc4_crtc->event && 732 (vc4_crtc->current_dlist == HVS_READ(SCALER_DISPLACTX(chan)) || 733 vc4_crtc->feeds_txp)) { 734 drm_crtc_send_vblank_event(crtc, vc4_crtc->event); 735 vc4_crtc->event = NULL; 736 drm_crtc_vblank_put(crtc); 737 738 /* Wait for the page flip to unmask the underrun to ensure that 739 * the display list was updated by the hardware. Before that 740 * happens, the HVS will be using the previous display list with 741 * the CRTC and encoder already reconfigured, leading to 742 * underruns. This can be seen when reconfiguring the CRTC. 743 */ 744 vc4_hvs_unmask_underrun(hvs, chan); 745 } 746 spin_unlock(&vc4_crtc->irq_lock); 747 spin_unlock_irqrestore(&dev->event_lock, flags); 748 } 749 750 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc) 751 { 752 crtc->t_vblank = ktime_get(); 753 drm_crtc_handle_vblank(&crtc->base); 754 vc4_crtc_handle_page_flip(crtc); 755 } 756 757 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data) 758 { 759 struct vc4_crtc *vc4_crtc = data; 760 u32 stat = CRTC_READ(PV_INTSTAT); 761 irqreturn_t ret = IRQ_NONE; 762 763 if (stat & PV_INT_VFP_START) { 764 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); 765 vc4_crtc_handle_vblank(vc4_crtc); 766 ret = IRQ_HANDLED; 767 } 768 769 return ret; 770 } 771 772 struct vc4_async_flip_state { 773 struct drm_crtc *crtc; 774 struct drm_framebuffer *fb; 775 struct drm_framebuffer *old_fb; 776 struct drm_pending_vblank_event *event; 777 778 struct vc4_seqno_cb cb; 779 }; 780 781 /* Called when the V3D execution for the BO being flipped to is done, so that 782 * we can actually update the plane's address to point to it. 783 */ 784 static void 785 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb) 786 { 787 struct vc4_async_flip_state *flip_state = 788 container_of(cb, struct vc4_async_flip_state, cb); 789 struct drm_crtc *crtc = flip_state->crtc; 790 struct drm_device *dev = crtc->dev; 791 struct drm_plane *plane = crtc->primary; 792 793 vc4_plane_async_set_fb(plane, flip_state->fb); 794 if (flip_state->event) { 795 unsigned long flags; 796 797 spin_lock_irqsave(&dev->event_lock, flags); 798 drm_crtc_send_vblank_event(crtc, flip_state->event); 799 spin_unlock_irqrestore(&dev->event_lock, flags); 800 } 801 802 drm_crtc_vblank_put(crtc); 803 drm_framebuffer_put(flip_state->fb); 804 805 /* Decrement the BO usecnt in order to keep the inc/dec calls balanced 806 * when the planes are updated through the async update path. 807 * FIXME: we should move to generic async-page-flip when it's 808 * available, so that we can get rid of this hand-made cleanup_fb() 809 * logic. 810 */ 811 if (flip_state->old_fb) { 812 struct drm_gem_cma_object *cma_bo; 813 struct vc4_bo *bo; 814 815 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0); 816 bo = to_vc4_bo(&cma_bo->base); 817 vc4_bo_dec_usecnt(bo); 818 drm_framebuffer_put(flip_state->old_fb); 819 } 820 821 kfree(flip_state); 822 } 823 824 /* Implements async (non-vblank-synced) page flips. 825 * 826 * The page flip ioctl needs to return immediately, so we grab the 827 * modeset semaphore on the pipe, and queue the address update for 828 * when V3D is done with the BO being flipped to. 829 */ 830 static int vc4_async_page_flip(struct drm_crtc *crtc, 831 struct drm_framebuffer *fb, 832 struct drm_pending_vblank_event *event, 833 uint32_t flags) 834 { 835 struct drm_device *dev = crtc->dev; 836 struct drm_plane *plane = crtc->primary; 837 int ret = 0; 838 struct vc4_async_flip_state *flip_state; 839 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0); 840 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base); 841 842 /* Increment the BO usecnt here, so that we never end up with an 843 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the 844 * plane is later updated through the non-async path. 845 * FIXME: we should move to generic async-page-flip when it's 846 * available, so that we can get rid of this hand-made prepare_fb() 847 * logic. 848 */ 849 ret = vc4_bo_inc_usecnt(bo); 850 if (ret) 851 return ret; 852 853 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL); 854 if (!flip_state) { 855 vc4_bo_dec_usecnt(bo); 856 return -ENOMEM; 857 } 858 859 drm_framebuffer_get(fb); 860 flip_state->fb = fb; 861 flip_state->crtc = crtc; 862 flip_state->event = event; 863 864 /* Save the current FB before it's replaced by the new one in 865 * drm_atomic_set_fb_for_plane(). We'll need the old FB in 866 * vc4_async_page_flip_complete() to decrement the BO usecnt and keep 867 * it consistent. 868 * FIXME: we should move to generic async-page-flip when it's 869 * available, so that we can get rid of this hand-made cleanup_fb() 870 * logic. 871 */ 872 flip_state->old_fb = plane->state->fb; 873 if (flip_state->old_fb) 874 drm_framebuffer_get(flip_state->old_fb); 875 876 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 877 878 /* Immediately update the plane's legacy fb pointer, so that later 879 * modeset prep sees the state that will be present when the semaphore 880 * is released. 881 */ 882 drm_atomic_set_fb_for_plane(plane->state, fb); 883 884 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno, 885 vc4_async_page_flip_complete); 886 887 /* Driver takes ownership of state on successful async commit. */ 888 return 0; 889 } 890 891 int vc4_page_flip(struct drm_crtc *crtc, 892 struct drm_framebuffer *fb, 893 struct drm_pending_vblank_event *event, 894 uint32_t flags, 895 struct drm_modeset_acquire_ctx *ctx) 896 { 897 if (flags & DRM_MODE_PAGE_FLIP_ASYNC) 898 return vc4_async_page_flip(crtc, fb, event, flags); 899 else 900 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx); 901 } 902 903 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc) 904 { 905 struct vc4_crtc_state *vc4_state, *old_vc4_state; 906 907 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL); 908 if (!vc4_state) 909 return NULL; 910 911 old_vc4_state = to_vc4_crtc_state(crtc->state); 912 vc4_state->margins = old_vc4_state->margins; 913 vc4_state->assigned_channel = old_vc4_state->assigned_channel; 914 915 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base); 916 return &vc4_state->base; 917 } 918 919 void vc4_crtc_destroy_state(struct drm_crtc *crtc, 920 struct drm_crtc_state *state) 921 { 922 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev); 923 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); 924 925 if (drm_mm_node_allocated(&vc4_state->mm)) { 926 unsigned long flags; 927 928 spin_lock_irqsave(&vc4->hvs->mm_lock, flags); 929 drm_mm_remove_node(&vc4_state->mm); 930 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); 931 932 } 933 934 drm_atomic_helper_crtc_destroy_state(crtc, state); 935 } 936 937 void vc4_crtc_reset(struct drm_crtc *crtc) 938 { 939 struct vc4_crtc_state *vc4_crtc_state; 940 941 if (crtc->state) 942 vc4_crtc_destroy_state(crtc, crtc->state); 943 944 vc4_crtc_state = kzalloc(sizeof(*vc4_crtc_state), GFP_KERNEL); 945 if (!vc4_crtc_state) { 946 crtc->state = NULL; 947 return; 948 } 949 950 vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED; 951 __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base); 952 } 953 954 static const struct drm_crtc_funcs vc4_crtc_funcs = { 955 .set_config = drm_atomic_helper_set_config, 956 .destroy = vc4_crtc_destroy, 957 .page_flip = vc4_page_flip, 958 .set_property = NULL, 959 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */ 960 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */ 961 .reset = vc4_crtc_reset, 962 .atomic_duplicate_state = vc4_crtc_duplicate_state, 963 .atomic_destroy_state = vc4_crtc_destroy_state, 964 .enable_vblank = vc4_enable_vblank, 965 .disable_vblank = vc4_disable_vblank, 966 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 967 }; 968 969 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = { 970 .mode_valid = vc4_crtc_mode_valid, 971 .atomic_check = vc4_crtc_atomic_check, 972 .atomic_begin = vc4_hvs_atomic_begin, 973 .atomic_flush = vc4_hvs_atomic_flush, 974 .atomic_enable = vc4_crtc_atomic_enable, 975 .atomic_disable = vc4_crtc_atomic_disable, 976 .get_scanout_position = vc4_crtc_get_scanout_position, 977 }; 978 979 static const struct vc4_pv_data bcm2835_pv0_data = { 980 .base = { 981 .hvs_available_channels = BIT(0), 982 .hvs_output = 0, 983 }, 984 .debugfs_name = "crtc0_regs", 985 .fifo_depth = 64, 986 .pixels_per_clock = 1, 987 .encoder_types = { 988 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0, 989 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI, 990 }, 991 }; 992 993 static const struct vc4_pv_data bcm2835_pv1_data = { 994 .base = { 995 .hvs_available_channels = BIT(2), 996 .hvs_output = 2, 997 }, 998 .debugfs_name = "crtc1_regs", 999 .fifo_depth = 64, 1000 .pixels_per_clock = 1, 1001 .encoder_types = { 1002 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1, 1003 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI, 1004 }, 1005 }; 1006 1007 static const struct vc4_pv_data bcm2835_pv2_data = { 1008 .base = { 1009 .hvs_available_channels = BIT(1), 1010 .hvs_output = 1, 1011 }, 1012 .debugfs_name = "crtc2_regs", 1013 .fifo_depth = 64, 1014 .pixels_per_clock = 1, 1015 .encoder_types = { 1016 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0, 1017 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC, 1018 }, 1019 }; 1020 1021 static const struct vc4_pv_data bcm2711_pv0_data = { 1022 .base = { 1023 .hvs_available_channels = BIT(0), 1024 .hvs_output = 0, 1025 }, 1026 .debugfs_name = "crtc0_regs", 1027 .fifo_depth = 64, 1028 .pixels_per_clock = 1, 1029 .encoder_types = { 1030 [0] = VC4_ENCODER_TYPE_DSI0, 1031 [1] = VC4_ENCODER_TYPE_DPI, 1032 }, 1033 }; 1034 1035 static const struct vc4_pv_data bcm2711_pv1_data = { 1036 .base = { 1037 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2), 1038 .hvs_output = 3, 1039 }, 1040 .debugfs_name = "crtc1_regs", 1041 .fifo_depth = 64, 1042 .pixels_per_clock = 1, 1043 .encoder_types = { 1044 [0] = VC4_ENCODER_TYPE_DSI1, 1045 [1] = VC4_ENCODER_TYPE_SMI, 1046 }, 1047 }; 1048 1049 static const struct vc4_pv_data bcm2711_pv2_data = { 1050 .base = { 1051 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2), 1052 .hvs_output = 4, 1053 }, 1054 .debugfs_name = "crtc2_regs", 1055 .fifo_depth = 256, 1056 .pixels_per_clock = 2, 1057 .encoder_types = { 1058 [0] = VC4_ENCODER_TYPE_HDMI0, 1059 }, 1060 }; 1061 1062 static const struct vc4_pv_data bcm2711_pv3_data = { 1063 .base = { 1064 .hvs_available_channels = BIT(1), 1065 .hvs_output = 1, 1066 }, 1067 .debugfs_name = "crtc3_regs", 1068 .fifo_depth = 64, 1069 .pixels_per_clock = 1, 1070 .encoder_types = { 1071 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC, 1072 }, 1073 }; 1074 1075 static const struct vc4_pv_data bcm2711_pv4_data = { 1076 .base = { 1077 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2), 1078 .hvs_output = 5, 1079 }, 1080 .debugfs_name = "crtc4_regs", 1081 .fifo_depth = 64, 1082 .pixels_per_clock = 2, 1083 .encoder_types = { 1084 [0] = VC4_ENCODER_TYPE_HDMI1, 1085 }, 1086 }; 1087 1088 static const struct of_device_id vc4_crtc_dt_match[] = { 1089 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data }, 1090 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data }, 1091 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data }, 1092 { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data }, 1093 { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data }, 1094 { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data }, 1095 { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data }, 1096 { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data }, 1097 {} 1098 }; 1099 1100 static void vc4_set_crtc_possible_masks(struct drm_device *drm, 1101 struct drm_crtc *crtc) 1102 { 1103 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 1104 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc); 1105 const enum vc4_encoder_type *encoder_types = pv_data->encoder_types; 1106 struct drm_encoder *encoder; 1107 1108 drm_for_each_encoder(encoder, drm) { 1109 struct vc4_encoder *vc4_encoder; 1110 int i; 1111 1112 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) 1113 continue; 1114 1115 vc4_encoder = to_vc4_encoder(encoder); 1116 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) { 1117 if (vc4_encoder->type == encoder_types[i]) { 1118 vc4_encoder->clock_select = i; 1119 encoder->possible_crtcs |= drm_crtc_mask(crtc); 1120 break; 1121 } 1122 } 1123 } 1124 } 1125 1126 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc, 1127 const struct drm_crtc_funcs *crtc_funcs, 1128 const struct drm_crtc_helper_funcs *crtc_helper_funcs) 1129 { 1130 struct vc4_dev *vc4 = to_vc4_dev(drm); 1131 struct drm_crtc *crtc = &vc4_crtc->base; 1132 struct drm_plane *primary_plane; 1133 unsigned int i; 1134 1135 /* For now, we create just the primary and the legacy cursor 1136 * planes. We should be able to stack more planes on easily, 1137 * but to do that we would need to compute the bandwidth 1138 * requirement of the plane configuration, and reject ones 1139 * that will take too much. 1140 */ 1141 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY); 1142 if (IS_ERR(primary_plane)) { 1143 dev_err(drm->dev, "failed to construct primary plane\n"); 1144 return PTR_ERR(primary_plane); 1145 } 1146 1147 spin_lock_init(&vc4_crtc->irq_lock); 1148 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, 1149 crtc_funcs, NULL); 1150 drm_crtc_helper_add(crtc, crtc_helper_funcs); 1151 1152 if (!vc4->hvs->hvs5) { 1153 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); 1154 1155 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); 1156 1157 /* We support CTM, but only for one CRTC at a time. It's therefore 1158 * implemented as private driver state in vc4_kms, not here. 1159 */ 1160 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size); 1161 } 1162 1163 for (i = 0; i < crtc->gamma_size; i++) { 1164 vc4_crtc->lut_r[i] = i; 1165 vc4_crtc->lut_g[i] = i; 1166 vc4_crtc->lut_b[i] = i; 1167 } 1168 1169 return 0; 1170 } 1171 1172 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) 1173 { 1174 struct platform_device *pdev = to_platform_device(dev); 1175 struct drm_device *drm = dev_get_drvdata(master); 1176 const struct vc4_pv_data *pv_data; 1177 struct vc4_crtc *vc4_crtc; 1178 struct drm_crtc *crtc; 1179 struct drm_plane *destroy_plane, *temp; 1180 int ret; 1181 1182 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL); 1183 if (!vc4_crtc) 1184 return -ENOMEM; 1185 crtc = &vc4_crtc->base; 1186 1187 pv_data = of_device_get_match_data(dev); 1188 if (!pv_data) 1189 return -ENODEV; 1190 vc4_crtc->data = &pv_data->base; 1191 vc4_crtc->pdev = pdev; 1192 1193 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0); 1194 if (IS_ERR(vc4_crtc->regs)) 1195 return PTR_ERR(vc4_crtc->regs); 1196 1197 vc4_crtc->regset.base = vc4_crtc->regs; 1198 vc4_crtc->regset.regs = crtc_regs; 1199 vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs); 1200 1201 ret = vc4_crtc_init(drm, vc4_crtc, 1202 &vc4_crtc_funcs, &vc4_crtc_helper_funcs); 1203 if (ret) 1204 return ret; 1205 vc4_set_crtc_possible_masks(drm, crtc); 1206 1207 CRTC_WRITE(PV_INTEN, 0); 1208 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); 1209 ret = devm_request_irq(dev, platform_get_irq(pdev, 0), 1210 vc4_crtc_irq_handler, 1211 IRQF_SHARED, 1212 "vc4 crtc", vc4_crtc); 1213 if (ret) 1214 goto err_destroy_planes; 1215 1216 platform_set_drvdata(pdev, vc4_crtc); 1217 1218 vc4_debugfs_add_regset32(drm, pv_data->debugfs_name, 1219 &vc4_crtc->regset); 1220 1221 return 0; 1222 1223 err_destroy_planes: 1224 list_for_each_entry_safe(destroy_plane, temp, 1225 &drm->mode_config.plane_list, head) { 1226 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc)) 1227 destroy_plane->funcs->destroy(destroy_plane); 1228 } 1229 1230 return ret; 1231 } 1232 1233 static void vc4_crtc_unbind(struct device *dev, struct device *master, 1234 void *data) 1235 { 1236 struct platform_device *pdev = to_platform_device(dev); 1237 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev); 1238 1239 vc4_crtc_destroy(&vc4_crtc->base); 1240 1241 CRTC_WRITE(PV_INTEN, 0); 1242 1243 platform_set_drvdata(pdev, NULL); 1244 } 1245 1246 static const struct component_ops vc4_crtc_ops = { 1247 .bind = vc4_crtc_bind, 1248 .unbind = vc4_crtc_unbind, 1249 }; 1250 1251 static int vc4_crtc_dev_probe(struct platform_device *pdev) 1252 { 1253 return component_add(&pdev->dev, &vc4_crtc_ops); 1254 } 1255 1256 static int vc4_crtc_dev_remove(struct platform_device *pdev) 1257 { 1258 component_del(&pdev->dev, &vc4_crtc_ops); 1259 return 0; 1260 } 1261 1262 struct platform_driver vc4_crtc_driver = { 1263 .probe = vc4_crtc_dev_probe, 1264 .remove = vc4_crtc_dev_remove, 1265 .driver = { 1266 .name = "vc4_crtc", 1267 .of_match_table = vc4_crtc_dt_match, 1268 }, 1269 }; 1270