1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 */ 5 6 /** 7 * DOC: VC4 CRTC module 8 * 9 * In VC4, the Pixel Valve is what most closely corresponds to the 10 * DRM's concept of a CRTC. The PV generates video timings from the 11 * encoder's clock plus its configuration. It pulls scaled pixels from 12 * the HVS at that timing, and feeds it to the encoder. 13 * 14 * However, the DRM CRTC also collects the configuration of all the 15 * DRM planes attached to it. As a result, the CRTC is also 16 * responsible for writing the display list for the HVS channel that 17 * the CRTC will use. 18 * 19 * The 2835 has 3 different pixel valves. pv0 in the audio power 20 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the 21 * image domain can feed either HDMI or the SDTV controller. The 22 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for 23 * SDTV, etc.) according to which output type is chosen in the mux. 24 * 25 * For power management, the pixel valve's registers are all clocked 26 * by the AXI clock, while the timings and FIFOs make use of the 27 * output-specific clock. Since the encoders also directly consume 28 * the CPRMAN clocks, and know what timings they need, they are the 29 * ones that set the clock. 30 */ 31 32 #include <linux/clk.h> 33 #include <linux/component.h> 34 #include <linux/of_device.h> 35 #include <linux/pm_runtime.h> 36 37 #include <drm/drm_atomic.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_atomic_uapi.h> 40 #include <drm/drm_fb_cma_helper.h> 41 #include <drm/drm_print.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/drm_vblank.h> 44 45 #include "vc4_drv.h" 46 #include "vc4_hdmi.h" 47 #include "vc4_regs.h" 48 49 #define HVS_FIFO_LATENCY_PIX 6 50 51 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset)) 52 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset)) 53 54 static const struct debugfs_reg32 crtc_regs[] = { 55 VC4_REG32(PV_CONTROL), 56 VC4_REG32(PV_V_CONTROL), 57 VC4_REG32(PV_VSYNCD_EVEN), 58 VC4_REG32(PV_HORZA), 59 VC4_REG32(PV_HORZB), 60 VC4_REG32(PV_VERTA), 61 VC4_REG32(PV_VERTB), 62 VC4_REG32(PV_VERTA_EVEN), 63 VC4_REG32(PV_VERTB_EVEN), 64 VC4_REG32(PV_INTEN), 65 VC4_REG32(PV_INTSTAT), 66 VC4_REG32(PV_STAT), 67 VC4_REG32(PV_HACT_ACT), 68 }; 69 70 static unsigned int 71 vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel) 72 { 73 u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel)); 74 /* Top/base are supposed to be 4-pixel aligned, but the 75 * Raspberry Pi firmware fills the low bits (which are 76 * presumably ignored). 77 */ 78 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3; 79 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3; 80 81 return top - base + 4; 82 } 83 84 static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc, 85 bool in_vblank_irq, 86 int *vpos, int *hpos, 87 ktime_t *stime, ktime_t *etime, 88 const struct drm_display_mode *mode) 89 { 90 struct drm_device *dev = crtc->dev; 91 struct vc4_dev *vc4 = to_vc4_dev(dev); 92 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 93 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state); 94 unsigned int cob_size; 95 u32 val; 96 int fifo_lines; 97 int vblank_lines; 98 bool ret = false; 99 100 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 101 102 /* Get optional system timestamp before query. */ 103 if (stime) 104 *stime = ktime_get(); 105 106 /* 107 * Read vertical scanline which is currently composed for our 108 * pixelvalve by the HVS, and also the scaler status. 109 */ 110 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel)); 111 112 /* Get optional system timestamp after query. */ 113 if (etime) 114 *etime = ktime_get(); 115 116 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 117 118 /* Vertical position of hvs composed scanline. */ 119 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE); 120 *hpos = 0; 121 122 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 123 *vpos /= 2; 124 125 /* Use hpos to correct for field offset in interlaced mode. */ 126 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2) 127 *hpos += mode->crtc_htotal / 2; 128 } 129 130 cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc_state->assigned_channel); 131 /* This is the offset we need for translating hvs -> pv scanout pos. */ 132 fifo_lines = cob_size / mode->crtc_hdisplay; 133 134 if (fifo_lines > 0) 135 ret = true; 136 137 /* HVS more than fifo_lines into frame for compositing? */ 138 if (*vpos > fifo_lines) { 139 /* 140 * We are in active scanout and can get some meaningful results 141 * from HVS. The actual PV scanout can not trail behind more 142 * than fifo_lines as that is the fifo's capacity. Assume that 143 * in active scanout the HVS and PV work in lockstep wrt. HVS 144 * refilling the fifo and PV consuming from the fifo, ie. 145 * whenever the PV consumes and frees up a scanline in the 146 * fifo, the HVS will immediately refill it, therefore 147 * incrementing vpos. Therefore we choose HVS read position - 148 * fifo size in scanlines as a estimate of the real scanout 149 * position of the PV. 150 */ 151 *vpos -= fifo_lines + 1; 152 153 return ret; 154 } 155 156 /* 157 * Less: This happens when we are in vblank and the HVS, after getting 158 * the VSTART restart signal from the PV, just started refilling its 159 * fifo with new lines from the top-most lines of the new framebuffers. 160 * The PV does not scan out in vblank, so does not remove lines from 161 * the fifo, so the fifo will be full quickly and the HVS has to pause. 162 * We can't get meaningful readings wrt. scanline position of the PV 163 * and need to make things up in a approximative but consistent way. 164 */ 165 vblank_lines = mode->vtotal - mode->vdisplay; 166 167 if (in_vblank_irq) { 168 /* 169 * Assume the irq handler got called close to first 170 * line of vblank, so PV has about a full vblank 171 * scanlines to go, and as a base timestamp use the 172 * one taken at entry into vblank irq handler, so it 173 * is not affected by random delays due to lock 174 * contention on event_lock or vblank_time lock in 175 * the core. 176 */ 177 *vpos = -vblank_lines; 178 179 if (stime) 180 *stime = vc4_crtc->t_vblank; 181 if (etime) 182 *etime = vc4_crtc->t_vblank; 183 184 /* 185 * If the HVS fifo is not yet full then we know for certain 186 * we are at the very beginning of vblank, as the hvs just 187 * started refilling, and the stime and etime timestamps 188 * truly correspond to start of vblank. 189 * 190 * Unfortunately there's no way to report this to upper levels 191 * and make it more useful. 192 */ 193 } else { 194 /* 195 * No clue where we are inside vblank. Return a vpos of zero, 196 * which will cause calling code to just return the etime 197 * timestamp uncorrected. At least this is no worse than the 198 * standard fallback. 199 */ 200 *vpos = 0; 201 } 202 203 return ret; 204 } 205 206 void vc4_crtc_destroy(struct drm_crtc *crtc) 207 { 208 drm_crtc_cleanup(crtc); 209 } 210 211 static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format) 212 { 213 const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc); 214 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc); 215 struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev); 216 u32 fifo_len_bytes = pv_data->fifo_depth; 217 218 /* 219 * Pixels are pulled from the HVS if the number of bytes is 220 * lower than the FIFO full level. 221 * 222 * The latency of the pixel fetch mechanism is 6 pixels, so we 223 * need to convert those 6 pixels in bytes, depending on the 224 * format, and then subtract that from the length of the FIFO 225 * to make sure we never end up in a situation where the FIFO 226 * is full. 227 */ 228 switch (format) { 229 case PV_CONTROL_FORMAT_DSIV_16: 230 case PV_CONTROL_FORMAT_DSIC_16: 231 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX; 232 case PV_CONTROL_FORMAT_DSIV_18: 233 return fifo_len_bytes - 14; 234 case PV_CONTROL_FORMAT_24: 235 case PV_CONTROL_FORMAT_DSIV_24: 236 default: 237 /* 238 * For some reason, the pixelvalve4 doesn't work with 239 * the usual formula and will only work with 32. 240 */ 241 if (crtc_data->hvs_output == 5) 242 return 32; 243 244 /* 245 * It looks like in some situations, we will overflow 246 * the PixelValve FIFO (with the bit 10 of PV stat being 247 * set) and stall the HVS / PV, eventually resulting in 248 * a page flip timeout. 249 * 250 * Displaying the video overlay during a playback with 251 * Kodi on an RPi3 seems to be a great solution with a 252 * failure rate around 50%. 253 * 254 * Removing 1 from the FIFO full level however 255 * seems to completely remove that issue. 256 */ 257 if (!vc4->hvs->hvs5) 258 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1; 259 260 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX; 261 } 262 } 263 264 static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc, 265 u32 format) 266 { 267 u32 level = vc4_get_fifo_full_level(vc4_crtc, format); 268 u32 ret = 0; 269 270 ret |= VC4_SET_FIELD((level >> 6), 271 PV5_CONTROL_FIFO_LEVEL_HIGH); 272 273 return ret | VC4_SET_FIELD(level & 0x3f, 274 PV_CONTROL_FIFO_LEVEL); 275 } 276 277 /* 278 * Returns the encoder attached to the CRTC. 279 * 280 * VC4 can only scan out to one encoder at a time, while the DRM core 281 * allows drivers to push pixels to more than one encoder from the 282 * same CRTC. 283 */ 284 struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc, 285 struct drm_crtc_state *state) 286 { 287 struct drm_encoder *encoder; 288 289 WARN_ON(hweight32(state->encoder_mask) > 1); 290 291 drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask) 292 return encoder; 293 294 return NULL; 295 } 296 297 static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc) 298 { 299 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 300 301 /* The PV needs to be disabled before it can be flushed */ 302 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN); 303 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR); 304 } 305 306 static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encoder, 307 struct drm_atomic_state *state) 308 { 309 struct drm_device *dev = crtc->dev; 310 struct vc4_dev *vc4 = to_vc4_dev(dev); 311 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 312 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 313 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc); 314 struct drm_crtc_state *crtc_state = crtc->state; 315 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 316 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; 317 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 318 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || 319 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); 320 u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; 321 u8 ppc = pv_data->pixels_per_clock; 322 bool debug_dump_regs = false; 323 324 if (debug_dump_regs) { 325 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev); 326 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n", 327 drm_crtc_index(crtc)); 328 drm_print_regset32(&p, &vc4_crtc->regset); 329 } 330 331 vc4_crtc_pixelvalve_reset(crtc); 332 333 CRTC_WRITE(PV_HORZA, 334 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc, 335 PV_HORZA_HBP) | 336 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc, 337 PV_HORZA_HSYNC)); 338 339 CRTC_WRITE(PV_HORZB, 340 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc, 341 PV_HORZB_HFP) | 342 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc, 343 PV_HORZB_HACTIVE)); 344 345 CRTC_WRITE(PV_VERTA, 346 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 347 PV_VERTA_VBP) | 348 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 349 PV_VERTA_VSYNC)); 350 CRTC_WRITE(PV_VERTB, 351 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 352 PV_VERTB_VFP) | 353 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); 354 355 if (interlace) { 356 CRTC_WRITE(PV_VERTA_EVEN, 357 VC4_SET_FIELD(mode->crtc_vtotal - 358 mode->crtc_vsync_end - 1, 359 PV_VERTA_VBP) | 360 VC4_SET_FIELD(mode->crtc_vsync_end - 361 mode->crtc_vsync_start, 362 PV_VERTA_VSYNC)); 363 CRTC_WRITE(PV_VERTB_EVEN, 364 VC4_SET_FIELD(mode->crtc_vsync_start - 365 mode->crtc_vdisplay, 366 PV_VERTB_VFP) | 367 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); 368 369 /* We set up first field even mode for HDMI. VEC's 370 * NTSC mode would want first field odd instead, once 371 * we support it (to do so, set ODD_FIRST and put the 372 * delay in VSYNCD_EVEN instead). 373 */ 374 CRTC_WRITE(PV_V_CONTROL, 375 PV_VCONTROL_CONTINUOUS | 376 (is_dsi ? PV_VCONTROL_DSI : 0) | 377 PV_VCONTROL_INTERLACE | 378 VC4_SET_FIELD(mode->htotal * pixel_rep / 2, 379 PV_VCONTROL_ODD_DELAY)); 380 CRTC_WRITE(PV_VSYNCD_EVEN, 0); 381 } else { 382 CRTC_WRITE(PV_V_CONTROL, 383 PV_VCONTROL_CONTINUOUS | 384 (is_dsi ? PV_VCONTROL_DSI : 0)); 385 } 386 387 if (is_dsi) 388 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); 389 390 if (vc4->hvs->hvs5) 391 CRTC_WRITE(PV_MUX_CFG, 392 VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP, 393 PV_MUX_CFG_RGB_PIXEL_MUX_MODE)); 394 395 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | 396 vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) | 397 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | 398 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | 399 PV_CONTROL_CLR_AT_START | 400 PV_CONTROL_TRIGGER_UNDERFLOW | 401 PV_CONTROL_WAIT_HSTART | 402 VC4_SET_FIELD(vc4_encoder->clock_select, 403 PV_CONTROL_CLK_SELECT)); 404 405 if (debug_dump_regs) { 406 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev); 407 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n", 408 drm_crtc_index(crtc)); 409 drm_print_regset32(&p, &vc4_crtc->regset); 410 } 411 } 412 413 static void require_hvs_enabled(struct drm_device *dev) 414 { 415 struct vc4_dev *vc4 = to_vc4_dev(dev); 416 417 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) != 418 SCALER_DISPCTRL_ENABLE); 419 } 420 421 static int vc4_crtc_disable(struct drm_crtc *crtc, 422 struct drm_encoder *encoder, 423 struct drm_atomic_state *state, 424 unsigned int channel) 425 { 426 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 427 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 428 struct drm_device *dev = crtc->dev; 429 int ret; 430 431 CRTC_WRITE(PV_V_CONTROL, 432 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN); 433 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); 434 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); 435 436 /* 437 * This delay is needed to avoid to get a pixel stuck in an 438 * unflushable FIFO between the pixelvalve and the HDMI 439 * controllers on the BCM2711. 440 * 441 * Timing is fairly sensitive here, so mdelay is the safest 442 * approach. 443 * 444 * If it was to be reworked, the stuck pixel happens on a 445 * BCM2711 when changing mode with a good probability, so a 446 * script that changes mode on a regular basis should trigger 447 * the bug after less than 10 attempts. It manifests itself with 448 * every pixels being shifted by one to the right, and thus the 449 * last pixel of a line actually being displayed as the first 450 * pixel on the next line. 451 */ 452 mdelay(20); 453 454 if (vc4_encoder && vc4_encoder->post_crtc_disable) 455 vc4_encoder->post_crtc_disable(encoder, state); 456 457 vc4_crtc_pixelvalve_reset(crtc); 458 vc4_hvs_stop_channel(dev, channel); 459 460 if (vc4_encoder && vc4_encoder->post_crtc_powerdown) 461 vc4_encoder->post_crtc_powerdown(encoder, state); 462 463 return 0; 464 } 465 466 static struct drm_encoder *vc4_crtc_get_encoder_by_type(struct drm_crtc *crtc, 467 enum vc4_encoder_type type) 468 { 469 struct drm_encoder *encoder; 470 471 drm_for_each_encoder(encoder, crtc->dev) { 472 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 473 474 if (vc4_encoder->type == type) 475 return encoder; 476 } 477 478 return NULL; 479 } 480 481 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc) 482 { 483 struct drm_device *drm = crtc->dev; 484 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 485 enum vc4_encoder_type encoder_type; 486 const struct vc4_pv_data *pv_data; 487 struct drm_encoder *encoder; 488 struct vc4_hdmi *vc4_hdmi; 489 unsigned encoder_sel; 490 int channel; 491 int ret; 492 493 if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node, 494 "brcm,bcm2711-pixelvalve2") || 495 of_device_is_compatible(vc4_crtc->pdev->dev.of_node, 496 "brcm,bcm2711-pixelvalve4"))) 497 return 0; 498 499 if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN)) 500 return 0; 501 502 if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN)) 503 return 0; 504 505 channel = vc4_hvs_get_fifo_from_output(drm, vc4_crtc->data->hvs_output); 506 if (channel < 0) 507 return 0; 508 509 encoder_sel = VC4_GET_FIELD(CRTC_READ(PV_CONTROL), PV_CONTROL_CLK_SELECT); 510 if (WARN_ON(encoder_sel != 0)) 511 return 0; 512 513 pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc); 514 encoder_type = pv_data->encoder_types[encoder_sel]; 515 encoder = vc4_crtc_get_encoder_by_type(crtc, encoder_type); 516 if (WARN_ON(!encoder)) 517 return 0; 518 519 vc4_hdmi = encoder_to_vc4_hdmi(encoder); 520 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 521 if (ret) 522 return ret; 523 524 ret = vc4_crtc_disable(crtc, encoder, NULL, channel); 525 if (ret) 526 return ret; 527 528 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 529 if (ret) 530 return ret; 531 532 return 0; 533 } 534 535 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, 536 struct drm_atomic_state *state) 537 { 538 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 539 crtc); 540 struct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state); 541 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, old_state); 542 struct drm_device *dev = crtc->dev; 543 544 drm_dbg(dev, "Disabling CRTC %s (%u) connected to Encoder %s (%u)", 545 crtc->name, crtc->base.id, encoder->name, encoder->base.id); 546 547 require_hvs_enabled(dev); 548 549 /* Disable vblank irq handling before crtc is disabled. */ 550 drm_crtc_vblank_off(crtc); 551 552 vc4_crtc_disable(crtc, encoder, state, old_vc4_state->assigned_channel); 553 554 /* 555 * Make sure we issue a vblank event after disabling the CRTC if 556 * someone was waiting it. 557 */ 558 if (crtc->state->event) { 559 unsigned long flags; 560 561 spin_lock_irqsave(&dev->event_lock, flags); 562 drm_crtc_send_vblank_event(crtc, crtc->state->event); 563 crtc->state->event = NULL; 564 spin_unlock_irqrestore(&dev->event_lock, flags); 565 } 566 } 567 568 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, 569 struct drm_atomic_state *state) 570 { 571 struct drm_crtc_state *new_state = drm_atomic_get_new_crtc_state(state, 572 crtc); 573 struct drm_device *dev = crtc->dev; 574 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 575 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, new_state); 576 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 577 578 drm_dbg(dev, "Enabling CRTC %s (%u) connected to Encoder %s (%u)", 579 crtc->name, crtc->base.id, encoder->name, encoder->base.id); 580 581 require_hvs_enabled(dev); 582 583 /* Enable vblank irq handling before crtc is started otherwise 584 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist(). 585 */ 586 drm_crtc_vblank_on(crtc); 587 588 vc4_hvs_atomic_enable(crtc, state); 589 590 if (vc4_encoder->pre_crtc_configure) 591 vc4_encoder->pre_crtc_configure(encoder, state); 592 593 vc4_crtc_config_pv(crtc, encoder, state); 594 595 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN); 596 597 if (vc4_encoder->pre_crtc_enable) 598 vc4_encoder->pre_crtc_enable(encoder, state); 599 600 /* When feeding the transposer block the pixelvalve is unneeded and 601 * should not be enabled. 602 */ 603 CRTC_WRITE(PV_V_CONTROL, 604 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN); 605 606 if (vc4_encoder->post_crtc_enable) 607 vc4_encoder->post_crtc_enable(encoder, state); 608 } 609 610 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc, 611 const struct drm_display_mode *mode) 612 { 613 /* Do not allow doublescan modes from user space */ 614 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { 615 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n", 616 crtc->base.id); 617 return MODE_NO_DBLESCAN; 618 } 619 620 return MODE_OK; 621 } 622 623 void vc4_crtc_get_margins(struct drm_crtc_state *state, 624 unsigned int *left, unsigned int *right, 625 unsigned int *top, unsigned int *bottom) 626 { 627 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); 628 struct drm_connector_state *conn_state; 629 struct drm_connector *conn; 630 int i; 631 632 *left = vc4_state->margins.left; 633 *right = vc4_state->margins.right; 634 *top = vc4_state->margins.top; 635 *bottom = vc4_state->margins.bottom; 636 637 /* We have to interate over all new connector states because 638 * vc4_crtc_get_margins() might be called before 639 * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state 640 * might be outdated. 641 */ 642 for_each_new_connector_in_state(state->state, conn, conn_state, i) { 643 if (conn_state->crtc != state->crtc) 644 continue; 645 646 *left = conn_state->tv.margins.left; 647 *right = conn_state->tv.margins.right; 648 *top = conn_state->tv.margins.top; 649 *bottom = conn_state->tv.margins.bottom; 650 break; 651 } 652 } 653 654 static int vc4_crtc_atomic_check(struct drm_crtc *crtc, 655 struct drm_atomic_state *state) 656 { 657 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 658 crtc); 659 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); 660 struct drm_connector *conn; 661 struct drm_connector_state *conn_state; 662 struct drm_encoder *encoder; 663 int ret, i; 664 665 ret = vc4_hvs_atomic_check(crtc, state); 666 if (ret) 667 return ret; 668 669 encoder = vc4_get_crtc_encoder(crtc, crtc_state); 670 if (encoder) { 671 const struct drm_display_mode *mode = &crtc_state->adjusted_mode; 672 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 673 674 mode = &crtc_state->adjusted_mode; 675 if (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) { 676 vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 1000, 677 mode->clock * 9 / 10) * 1000; 678 } else { 679 vc4_state->hvs_load = mode->clock * 1000; 680 } 681 } 682 683 for_each_new_connector_in_state(state, conn, conn_state, 684 i) { 685 if (conn_state->crtc != crtc) 686 continue; 687 688 vc4_state->margins.left = conn_state->tv.margins.left; 689 vc4_state->margins.right = conn_state->tv.margins.right; 690 vc4_state->margins.top = conn_state->tv.margins.top; 691 vc4_state->margins.bottom = conn_state->tv.margins.bottom; 692 break; 693 } 694 695 return 0; 696 } 697 698 static int vc4_enable_vblank(struct drm_crtc *crtc) 699 { 700 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 701 702 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START); 703 704 return 0; 705 } 706 707 static void vc4_disable_vblank(struct drm_crtc *crtc) 708 { 709 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 710 711 CRTC_WRITE(PV_INTEN, 0); 712 } 713 714 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) 715 { 716 struct drm_crtc *crtc = &vc4_crtc->base; 717 struct drm_device *dev = crtc->dev; 718 struct vc4_dev *vc4 = to_vc4_dev(dev); 719 u32 chan = vc4_crtc->current_hvs_channel; 720 unsigned long flags; 721 722 spin_lock_irqsave(&dev->event_lock, flags); 723 spin_lock(&vc4_crtc->irq_lock); 724 if (vc4_crtc->event && 725 (vc4_crtc->current_dlist == HVS_READ(SCALER_DISPLACTX(chan)) || 726 vc4_crtc->feeds_txp)) { 727 drm_crtc_send_vblank_event(crtc, vc4_crtc->event); 728 vc4_crtc->event = NULL; 729 drm_crtc_vblank_put(crtc); 730 731 /* Wait for the page flip to unmask the underrun to ensure that 732 * the display list was updated by the hardware. Before that 733 * happens, the HVS will be using the previous display list with 734 * the CRTC and encoder already reconfigured, leading to 735 * underruns. This can be seen when reconfiguring the CRTC. 736 */ 737 vc4_hvs_unmask_underrun(dev, chan); 738 } 739 spin_unlock(&vc4_crtc->irq_lock); 740 spin_unlock_irqrestore(&dev->event_lock, flags); 741 } 742 743 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc) 744 { 745 crtc->t_vblank = ktime_get(); 746 drm_crtc_handle_vblank(&crtc->base); 747 vc4_crtc_handle_page_flip(crtc); 748 } 749 750 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data) 751 { 752 struct vc4_crtc *vc4_crtc = data; 753 u32 stat = CRTC_READ(PV_INTSTAT); 754 irqreturn_t ret = IRQ_NONE; 755 756 if (stat & PV_INT_VFP_START) { 757 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); 758 vc4_crtc_handle_vblank(vc4_crtc); 759 ret = IRQ_HANDLED; 760 } 761 762 return ret; 763 } 764 765 struct vc4_async_flip_state { 766 struct drm_crtc *crtc; 767 struct drm_framebuffer *fb; 768 struct drm_framebuffer *old_fb; 769 struct drm_pending_vblank_event *event; 770 771 struct vc4_seqno_cb cb; 772 }; 773 774 /* Called when the V3D execution for the BO being flipped to is done, so that 775 * we can actually update the plane's address to point to it. 776 */ 777 static void 778 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb) 779 { 780 struct vc4_async_flip_state *flip_state = 781 container_of(cb, struct vc4_async_flip_state, cb); 782 struct drm_crtc *crtc = flip_state->crtc; 783 struct drm_device *dev = crtc->dev; 784 struct drm_plane *plane = crtc->primary; 785 786 vc4_plane_async_set_fb(plane, flip_state->fb); 787 if (flip_state->event) { 788 unsigned long flags; 789 790 spin_lock_irqsave(&dev->event_lock, flags); 791 drm_crtc_send_vblank_event(crtc, flip_state->event); 792 spin_unlock_irqrestore(&dev->event_lock, flags); 793 } 794 795 drm_crtc_vblank_put(crtc); 796 drm_framebuffer_put(flip_state->fb); 797 798 /* Decrement the BO usecnt in order to keep the inc/dec calls balanced 799 * when the planes are updated through the async update path. 800 * FIXME: we should move to generic async-page-flip when it's 801 * available, so that we can get rid of this hand-made cleanup_fb() 802 * logic. 803 */ 804 if (flip_state->old_fb) { 805 struct drm_gem_cma_object *cma_bo; 806 struct vc4_bo *bo; 807 808 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0); 809 bo = to_vc4_bo(&cma_bo->base); 810 vc4_bo_dec_usecnt(bo); 811 drm_framebuffer_put(flip_state->old_fb); 812 } 813 814 kfree(flip_state); 815 } 816 817 /* Implements async (non-vblank-synced) page flips. 818 * 819 * The page flip ioctl needs to return immediately, so we grab the 820 * modeset semaphore on the pipe, and queue the address update for 821 * when V3D is done with the BO being flipped to. 822 */ 823 static int vc4_async_page_flip(struct drm_crtc *crtc, 824 struct drm_framebuffer *fb, 825 struct drm_pending_vblank_event *event, 826 uint32_t flags) 827 { 828 struct drm_device *dev = crtc->dev; 829 struct drm_plane *plane = crtc->primary; 830 int ret = 0; 831 struct vc4_async_flip_state *flip_state; 832 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0); 833 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base); 834 835 /* Increment the BO usecnt here, so that we never end up with an 836 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the 837 * plane is later updated through the non-async path. 838 * FIXME: we should move to generic async-page-flip when it's 839 * available, so that we can get rid of this hand-made prepare_fb() 840 * logic. 841 */ 842 ret = vc4_bo_inc_usecnt(bo); 843 if (ret) 844 return ret; 845 846 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL); 847 if (!flip_state) { 848 vc4_bo_dec_usecnt(bo); 849 return -ENOMEM; 850 } 851 852 drm_framebuffer_get(fb); 853 flip_state->fb = fb; 854 flip_state->crtc = crtc; 855 flip_state->event = event; 856 857 /* Save the current FB before it's replaced by the new one in 858 * drm_atomic_set_fb_for_plane(). We'll need the old FB in 859 * vc4_async_page_flip_complete() to decrement the BO usecnt and keep 860 * it consistent. 861 * FIXME: we should move to generic async-page-flip when it's 862 * available, so that we can get rid of this hand-made cleanup_fb() 863 * logic. 864 */ 865 flip_state->old_fb = plane->state->fb; 866 if (flip_state->old_fb) 867 drm_framebuffer_get(flip_state->old_fb); 868 869 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 870 871 /* Immediately update the plane's legacy fb pointer, so that later 872 * modeset prep sees the state that will be present when the semaphore 873 * is released. 874 */ 875 drm_atomic_set_fb_for_plane(plane->state, fb); 876 877 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno, 878 vc4_async_page_flip_complete); 879 880 /* Driver takes ownership of state on successful async commit. */ 881 return 0; 882 } 883 884 int vc4_page_flip(struct drm_crtc *crtc, 885 struct drm_framebuffer *fb, 886 struct drm_pending_vblank_event *event, 887 uint32_t flags, 888 struct drm_modeset_acquire_ctx *ctx) 889 { 890 if (flags & DRM_MODE_PAGE_FLIP_ASYNC) 891 return vc4_async_page_flip(crtc, fb, event, flags); 892 else 893 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx); 894 } 895 896 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc) 897 { 898 struct vc4_crtc_state *vc4_state, *old_vc4_state; 899 900 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL); 901 if (!vc4_state) 902 return NULL; 903 904 old_vc4_state = to_vc4_crtc_state(crtc->state); 905 vc4_state->margins = old_vc4_state->margins; 906 vc4_state->assigned_channel = old_vc4_state->assigned_channel; 907 908 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base); 909 return &vc4_state->base; 910 } 911 912 void vc4_crtc_destroy_state(struct drm_crtc *crtc, 913 struct drm_crtc_state *state) 914 { 915 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev); 916 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); 917 918 if (drm_mm_node_allocated(&vc4_state->mm)) { 919 unsigned long flags; 920 921 spin_lock_irqsave(&vc4->hvs->mm_lock, flags); 922 drm_mm_remove_node(&vc4_state->mm); 923 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); 924 925 } 926 927 drm_atomic_helper_crtc_destroy_state(crtc, state); 928 } 929 930 void vc4_crtc_reset(struct drm_crtc *crtc) 931 { 932 struct vc4_crtc_state *vc4_crtc_state; 933 934 if (crtc->state) 935 vc4_crtc_destroy_state(crtc, crtc->state); 936 937 vc4_crtc_state = kzalloc(sizeof(*vc4_crtc_state), GFP_KERNEL); 938 if (!vc4_crtc_state) { 939 crtc->state = NULL; 940 return; 941 } 942 943 vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED; 944 __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base); 945 } 946 947 static const struct drm_crtc_funcs vc4_crtc_funcs = { 948 .set_config = drm_atomic_helper_set_config, 949 .destroy = vc4_crtc_destroy, 950 .page_flip = vc4_page_flip, 951 .set_property = NULL, 952 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */ 953 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */ 954 .reset = vc4_crtc_reset, 955 .atomic_duplicate_state = vc4_crtc_duplicate_state, 956 .atomic_destroy_state = vc4_crtc_destroy_state, 957 .enable_vblank = vc4_enable_vblank, 958 .disable_vblank = vc4_disable_vblank, 959 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 960 }; 961 962 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = { 963 .mode_valid = vc4_crtc_mode_valid, 964 .atomic_check = vc4_crtc_atomic_check, 965 .atomic_begin = vc4_hvs_atomic_begin, 966 .atomic_flush = vc4_hvs_atomic_flush, 967 .atomic_enable = vc4_crtc_atomic_enable, 968 .atomic_disable = vc4_crtc_atomic_disable, 969 .get_scanout_position = vc4_crtc_get_scanout_position, 970 }; 971 972 static const struct vc4_pv_data bcm2835_pv0_data = { 973 .base = { 974 .hvs_available_channels = BIT(0), 975 .hvs_output = 0, 976 }, 977 .debugfs_name = "crtc0_regs", 978 .fifo_depth = 64, 979 .pixels_per_clock = 1, 980 .encoder_types = { 981 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0, 982 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI, 983 }, 984 }; 985 986 static const struct vc4_pv_data bcm2835_pv1_data = { 987 .base = { 988 .hvs_available_channels = BIT(2), 989 .hvs_output = 2, 990 }, 991 .debugfs_name = "crtc1_regs", 992 .fifo_depth = 64, 993 .pixels_per_clock = 1, 994 .encoder_types = { 995 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1, 996 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI, 997 }, 998 }; 999 1000 static const struct vc4_pv_data bcm2835_pv2_data = { 1001 .base = { 1002 .hvs_available_channels = BIT(1), 1003 .hvs_output = 1, 1004 }, 1005 .debugfs_name = "crtc2_regs", 1006 .fifo_depth = 64, 1007 .pixels_per_clock = 1, 1008 .encoder_types = { 1009 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0, 1010 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC, 1011 }, 1012 }; 1013 1014 static const struct vc4_pv_data bcm2711_pv0_data = { 1015 .base = { 1016 .hvs_available_channels = BIT(0), 1017 .hvs_output = 0, 1018 }, 1019 .debugfs_name = "crtc0_regs", 1020 .fifo_depth = 64, 1021 .pixels_per_clock = 1, 1022 .encoder_types = { 1023 [0] = VC4_ENCODER_TYPE_DSI0, 1024 [1] = VC4_ENCODER_TYPE_DPI, 1025 }, 1026 }; 1027 1028 static const struct vc4_pv_data bcm2711_pv1_data = { 1029 .base = { 1030 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2), 1031 .hvs_output = 3, 1032 }, 1033 .debugfs_name = "crtc1_regs", 1034 .fifo_depth = 64, 1035 .pixels_per_clock = 1, 1036 .encoder_types = { 1037 [0] = VC4_ENCODER_TYPE_DSI1, 1038 [1] = VC4_ENCODER_TYPE_SMI, 1039 }, 1040 }; 1041 1042 static const struct vc4_pv_data bcm2711_pv2_data = { 1043 .base = { 1044 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2), 1045 .hvs_output = 4, 1046 }, 1047 .debugfs_name = "crtc2_regs", 1048 .fifo_depth = 256, 1049 .pixels_per_clock = 2, 1050 .encoder_types = { 1051 [0] = VC4_ENCODER_TYPE_HDMI0, 1052 }, 1053 }; 1054 1055 static const struct vc4_pv_data bcm2711_pv3_data = { 1056 .base = { 1057 .hvs_available_channels = BIT(1), 1058 .hvs_output = 1, 1059 }, 1060 .debugfs_name = "crtc3_regs", 1061 .fifo_depth = 64, 1062 .pixels_per_clock = 1, 1063 .encoder_types = { 1064 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC, 1065 }, 1066 }; 1067 1068 static const struct vc4_pv_data bcm2711_pv4_data = { 1069 .base = { 1070 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2), 1071 .hvs_output = 5, 1072 }, 1073 .debugfs_name = "crtc4_regs", 1074 .fifo_depth = 64, 1075 .pixels_per_clock = 2, 1076 .encoder_types = { 1077 [0] = VC4_ENCODER_TYPE_HDMI1, 1078 }, 1079 }; 1080 1081 static const struct of_device_id vc4_crtc_dt_match[] = { 1082 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data }, 1083 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data }, 1084 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data }, 1085 { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data }, 1086 { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data }, 1087 { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data }, 1088 { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data }, 1089 { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data }, 1090 {} 1091 }; 1092 1093 static void vc4_set_crtc_possible_masks(struct drm_device *drm, 1094 struct drm_crtc *crtc) 1095 { 1096 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 1097 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc); 1098 const enum vc4_encoder_type *encoder_types = pv_data->encoder_types; 1099 struct drm_encoder *encoder; 1100 1101 drm_for_each_encoder(encoder, drm) { 1102 struct vc4_encoder *vc4_encoder; 1103 int i; 1104 1105 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) 1106 continue; 1107 1108 vc4_encoder = to_vc4_encoder(encoder); 1109 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) { 1110 if (vc4_encoder->type == encoder_types[i]) { 1111 vc4_encoder->clock_select = i; 1112 encoder->possible_crtcs |= drm_crtc_mask(crtc); 1113 break; 1114 } 1115 } 1116 } 1117 } 1118 1119 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc, 1120 const struct drm_crtc_funcs *crtc_funcs, 1121 const struct drm_crtc_helper_funcs *crtc_helper_funcs) 1122 { 1123 struct vc4_dev *vc4 = to_vc4_dev(drm); 1124 struct drm_crtc *crtc = &vc4_crtc->base; 1125 struct drm_plane *primary_plane; 1126 unsigned int i; 1127 1128 /* For now, we create just the primary and the legacy cursor 1129 * planes. We should be able to stack more planes on easily, 1130 * but to do that we would need to compute the bandwidth 1131 * requirement of the plane configuration, and reject ones 1132 * that will take too much. 1133 */ 1134 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY); 1135 if (IS_ERR(primary_plane)) { 1136 dev_err(drm->dev, "failed to construct primary plane\n"); 1137 return PTR_ERR(primary_plane); 1138 } 1139 1140 spin_lock_init(&vc4_crtc->irq_lock); 1141 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, 1142 crtc_funcs, NULL); 1143 drm_crtc_helper_add(crtc, crtc_helper_funcs); 1144 1145 if (!vc4->hvs->hvs5) { 1146 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); 1147 1148 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); 1149 1150 /* We support CTM, but only for one CRTC at a time. It's therefore 1151 * implemented as private driver state in vc4_kms, not here. 1152 */ 1153 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size); 1154 } 1155 1156 for (i = 0; i < crtc->gamma_size; i++) { 1157 vc4_crtc->lut_r[i] = i; 1158 vc4_crtc->lut_g[i] = i; 1159 vc4_crtc->lut_b[i] = i; 1160 } 1161 1162 return 0; 1163 } 1164 1165 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) 1166 { 1167 struct platform_device *pdev = to_platform_device(dev); 1168 struct drm_device *drm = dev_get_drvdata(master); 1169 const struct vc4_pv_data *pv_data; 1170 struct vc4_crtc *vc4_crtc; 1171 struct drm_crtc *crtc; 1172 struct drm_plane *destroy_plane, *temp; 1173 int ret; 1174 1175 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL); 1176 if (!vc4_crtc) 1177 return -ENOMEM; 1178 crtc = &vc4_crtc->base; 1179 1180 pv_data = of_device_get_match_data(dev); 1181 if (!pv_data) 1182 return -ENODEV; 1183 vc4_crtc->data = &pv_data->base; 1184 vc4_crtc->pdev = pdev; 1185 1186 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0); 1187 if (IS_ERR(vc4_crtc->regs)) 1188 return PTR_ERR(vc4_crtc->regs); 1189 1190 vc4_crtc->regset.base = vc4_crtc->regs; 1191 vc4_crtc->regset.regs = crtc_regs; 1192 vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs); 1193 1194 ret = vc4_crtc_init(drm, vc4_crtc, 1195 &vc4_crtc_funcs, &vc4_crtc_helper_funcs); 1196 if (ret) 1197 return ret; 1198 vc4_set_crtc_possible_masks(drm, crtc); 1199 1200 CRTC_WRITE(PV_INTEN, 0); 1201 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); 1202 ret = devm_request_irq(dev, platform_get_irq(pdev, 0), 1203 vc4_crtc_irq_handler, 1204 IRQF_SHARED, 1205 "vc4 crtc", vc4_crtc); 1206 if (ret) 1207 goto err_destroy_planes; 1208 1209 platform_set_drvdata(pdev, vc4_crtc); 1210 1211 vc4_debugfs_add_regset32(drm, pv_data->debugfs_name, 1212 &vc4_crtc->regset); 1213 1214 return 0; 1215 1216 err_destroy_planes: 1217 list_for_each_entry_safe(destroy_plane, temp, 1218 &drm->mode_config.plane_list, head) { 1219 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc)) 1220 destroy_plane->funcs->destroy(destroy_plane); 1221 } 1222 1223 return ret; 1224 } 1225 1226 static void vc4_crtc_unbind(struct device *dev, struct device *master, 1227 void *data) 1228 { 1229 struct platform_device *pdev = to_platform_device(dev); 1230 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev); 1231 1232 vc4_crtc_destroy(&vc4_crtc->base); 1233 1234 CRTC_WRITE(PV_INTEN, 0); 1235 1236 platform_set_drvdata(pdev, NULL); 1237 } 1238 1239 static const struct component_ops vc4_crtc_ops = { 1240 .bind = vc4_crtc_bind, 1241 .unbind = vc4_crtc_unbind, 1242 }; 1243 1244 static int vc4_crtc_dev_probe(struct platform_device *pdev) 1245 { 1246 return component_add(&pdev->dev, &vc4_crtc_ops); 1247 } 1248 1249 static int vc4_crtc_dev_remove(struct platform_device *pdev) 1250 { 1251 component_del(&pdev->dev, &vc4_crtc_ops); 1252 return 0; 1253 } 1254 1255 struct platform_driver vc4_crtc_driver = { 1256 .probe = vc4_crtc_dev_probe, 1257 .remove = vc4_crtc_dev_remove, 1258 .driver = { 1259 .name = "vc4_crtc", 1260 .of_match_table = vc4_crtc_dt_match, 1261 }, 1262 }; 1263