1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2017-2018 Broadcom */ 3 4 #ifndef V3D_REGS_H 5 #define V3D_REGS_H 6 7 #include <linux/bitops.h> 8 9 #define V3D_MASK(high, low) ((u32)GENMASK(high, low)) 10 /* Using the GNU statement expression extension */ 11 #define V3D_SET_FIELD(value, field) \ 12 ({ \ 13 u32 fieldval = (value) << field##_SHIFT; \ 14 WARN_ON((fieldval & ~field##_MASK) != 0); \ 15 fieldval & field##_MASK; \ 16 }) 17 18 #define V3D_GET_FIELD(word, field) (((word) & field##_MASK) >> \ 19 field##_SHIFT) 20 21 /* Hub registers for shared hardware between V3D cores. */ 22 23 #define V3D_HUB_AXICFG 0x00000 24 # define V3D_HUB_AXICFG_MAX_LEN_MASK V3D_MASK(3, 0) 25 # define V3D_HUB_AXICFG_MAX_LEN_SHIFT 0 26 #define V3D_HUB_UIFCFG 0x00004 27 #define V3D_HUB_IDENT0 0x00008 28 29 #define V3D_HUB_IDENT1 0x0000c 30 # define V3D_HUB_IDENT1_WITH_MSO BIT(19) 31 # define V3D_HUB_IDENT1_WITH_TSY BIT(18) 32 # define V3D_HUB_IDENT1_WITH_TFU BIT(17) 33 # define V3D_HUB_IDENT1_WITH_L3C BIT(16) 34 # define V3D_HUB_IDENT1_NHOSTS_MASK V3D_MASK(15, 12) 35 # define V3D_HUB_IDENT1_NHOSTS_SHIFT 12 36 # define V3D_HUB_IDENT1_NCORES_MASK V3D_MASK(11, 8) 37 # define V3D_HUB_IDENT1_NCORES_SHIFT 8 38 # define V3D_HUB_IDENT1_REV_MASK V3D_MASK(7, 4) 39 # define V3D_HUB_IDENT1_REV_SHIFT 4 40 # define V3D_HUB_IDENT1_TVER_MASK V3D_MASK(3, 0) 41 # define V3D_HUB_IDENT1_TVER_SHIFT 0 42 43 #define V3D_HUB_IDENT2 0x00010 44 # define V3D_HUB_IDENT2_WITH_MMU BIT(8) 45 # define V3D_HUB_IDENT2_L3C_NKB_MASK V3D_MASK(7, 0) 46 # define V3D_HUB_IDENT2_L3C_NKB_SHIFT 0 47 48 #define V3D_HUB_IDENT3 0x00014 49 # define V3D_HUB_IDENT3_IPREV_MASK V3D_MASK(15, 8) 50 # define V3D_HUB_IDENT3_IPREV_SHIFT 8 51 # define V3D_HUB_IDENT3_IPIDX_MASK V3D_MASK(7, 0) 52 # define V3D_HUB_IDENT3_IPIDX_SHIFT 0 53 54 #define V3D_HUB_INT_STS 0x00050 55 #define V3D_HUB_INT_SET 0x00054 56 #define V3D_HUB_INT_CLR 0x00058 57 #define V3D_HUB_INT_MSK_STS 0x0005c 58 #define V3D_HUB_INT_MSK_SET 0x00060 59 #define V3D_HUB_INT_MSK_CLR 0x00064 60 # define V3D_HUB_INT_MMU_WRV BIT(5) 61 # define V3D_HUB_INT_MMU_PTI BIT(4) 62 # define V3D_HUB_INT_MMU_CAP BIT(3) 63 # define V3D_HUB_INT_MSO BIT(2) 64 # define V3D_HUB_INT_TFUC BIT(1) 65 # define V3D_HUB_INT_TFUF BIT(0) 66 67 #define V3D_GCA_CACHE_CTRL 0x0000c 68 # define V3D_GCA_CACHE_CTRL_FLUSH BIT(0) 69 70 #define V3D_GCA_SAFE_SHUTDOWN 0x000b0 71 # define V3D_GCA_SAFE_SHUTDOWN_EN BIT(0) 72 73 #define V3D_GCA_SAFE_SHUTDOWN_ACK 0x000b4 74 # define V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED 3 75 76 # define V3D_TOP_GR_BRIDGE_REVISION 0x00000 77 # define V3D_TOP_GR_BRIDGE_MAJOR_MASK V3D_MASK(15, 8) 78 # define V3D_TOP_GR_BRIDGE_MAJOR_SHIFT 8 79 # define V3D_TOP_GR_BRIDGE_MINOR_MASK V3D_MASK(7, 0) 80 # define V3D_TOP_GR_BRIDGE_MINOR_SHIFT 0 81 82 /* 7268 reset reg */ 83 # define V3D_TOP_GR_BRIDGE_SW_INIT_0 0x00008 84 # define V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT BIT(0) 85 /* 7278 reset reg */ 86 # define V3D_TOP_GR_BRIDGE_SW_INIT_1 0x0000c 87 # define V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT BIT(0) 88 89 /* Per-MMU registers. */ 90 91 #define V3D_MMUC_CONTROL 0x01000 92 # define V3D_MMUC_CONTROL_CLEAR BIT(3) 93 # define V3D_MMUC_CONTROL_FLUSHING BIT(2) 94 # define V3D_MMUC_CONTROL_FLUSH BIT(1) 95 # define V3D_MMUC_CONTROL_ENABLE BIT(0) 96 97 #define V3D_MMU_CTL 0x01200 98 # define V3D_MMU_CTL_CAP_EXCEEDED BIT(27) 99 # define V3D_MMU_CTL_CAP_EXCEEDED_ABORT BIT(26) 100 # define V3D_MMU_CTL_CAP_EXCEEDED_INT BIT(25) 101 # define V3D_MMU_CTL_CAP_EXCEEDED_EXCEPTION BIT(24) 102 # define V3D_MMU_CTL_PT_INVALID BIT(20) 103 # define V3D_MMU_CTL_PT_INVALID_ABORT BIT(19) 104 # define V3D_MMU_CTL_PT_INVALID_INT BIT(18) 105 # define V3D_MMU_CTL_PT_INVALID_EXCEPTION BIT(17) 106 # define V3D_MMU_CTL_WRITE_VIOLATION BIT(16) 107 # define V3D_MMU_CTL_WRITE_VIOLATION_ABORT BIT(11) 108 # define V3D_MMU_CTL_WRITE_VIOLATION_INT BIT(10) 109 # define V3D_MMU_CTL_WRITE_VIOLATION_EXCEPTION BIT(9) 110 # define V3D_MMU_CTL_TLB_CLEARING BIT(7) 111 # define V3D_MMU_CTL_TLB_STATS_CLEAR BIT(3) 112 # define V3D_MMU_CTL_TLB_CLEAR BIT(2) 113 # define V3D_MMU_CTL_TLB_STATS_ENABLE BIT(1) 114 # define V3D_MMU_CTL_ENABLE BIT(0) 115 116 #define V3D_MMU_PT_PA_BASE 0x01204 117 #define V3D_MMU_HIT 0x01208 118 #define V3D_MMU_MISSES 0x0120c 119 #define V3D_MMU_STALLS 0x01210 120 121 #define V3D_MMU_ADDR_CAP 0x01214 122 # define V3D_MMU_ADDR_CAP_ENABLE BIT(31) 123 # define V3D_MMU_ADDR_CAP_MPAGE_MASK V3D_MASK(11, 0) 124 # define V3D_MMU_ADDR_CAP_MPAGE_SHIFT 0 125 126 #define V3D_MMU_SHOOT_DOWN 0x01218 127 # define V3D_MMU_SHOOT_DOWN_SHOOTING BIT(29) 128 # define V3D_MMU_SHOOT_DOWN_SHOOT BIT(28) 129 # define V3D_MMU_SHOOT_DOWN_PAGE_MASK V3D_MASK(27, 0) 130 # define V3D_MMU_SHOOT_DOWN_PAGE_SHIFT 0 131 132 #define V3D_MMU_BYPASS_START 0x0121c 133 #define V3D_MMU_BYPASS_END 0x01220 134 135 /* AXI ID of the access that faulted */ 136 #define V3D_MMU_VIO_ID 0x0122c 137 138 /* Address for illegal PTEs to return */ 139 #define V3D_MMU_ILLEGAL_ADDR 0x01230 140 # define V3D_MMU_ILLEGAL_ADDR_ENABLE BIT(31) 141 142 /* Address that faulted */ 143 #define V3D_MMU_VIO_ADDR 0x01234 144 145 /* Per-V3D-core registers */ 146 147 #define V3D_CTL_IDENT0 0x00000 148 # define V3D_IDENT0_VER_MASK V3D_MASK(31, 24) 149 # define V3D_IDENT0_VER_SHIFT 24 150 151 #define V3D_CTL_IDENT1 0x00004 152 /* Multiples of 1kb */ 153 # define V3D_IDENT1_VPM_SIZE_MASK V3D_MASK(31, 28) 154 # define V3D_IDENT1_VPM_SIZE_SHIFT 28 155 # define V3D_IDENT1_NSEM_MASK V3D_MASK(23, 16) 156 # define V3D_IDENT1_NSEM_SHIFT 16 157 # define V3D_IDENT1_NTMU_MASK V3D_MASK(15, 12) 158 # define V3D_IDENT1_NTMU_SHIFT 12 159 # define V3D_IDENT1_QUPS_MASK V3D_MASK(11, 8) 160 # define V3D_IDENT1_QUPS_SHIFT 8 161 # define V3D_IDENT1_NSLC_MASK V3D_MASK(7, 4) 162 # define V3D_IDENT1_NSLC_SHIFT 4 163 # define V3D_IDENT1_REV_MASK V3D_MASK(3, 0) 164 # define V3D_IDENT1_REV_SHIFT 0 165 166 #define V3D_CTL_IDENT2 0x00008 167 # define V3D_IDENT2_BCG_INT BIT(28) 168 169 #define V3D_CTL_MISCCFG 0x00018 170 # define V3D_MISCCFG_OVRTMUOUT BIT(0) 171 172 #define V3D_CTL_L2CACTL 0x00020 173 # define V3D_L2CACTL_L2CCLR BIT(2) 174 # define V3D_L2CACTL_L2CDIS BIT(1) 175 # define V3D_L2CACTL_L2CENA BIT(0) 176 177 #define V3D_CTL_SLCACTL 0x00024 178 # define V3D_SLCACTL_TVCCS_MASK V3D_MASK(27, 24) 179 # define V3D_SLCACTL_TVCCS_SHIFT 24 180 # define V3D_SLCACTL_TDCCS_MASK V3D_MASK(19, 16) 181 # define V3D_SLCACTL_TDCCS_SHIFT 16 182 # define V3D_SLCACTL_UCC_MASK V3D_MASK(11, 8) 183 # define V3D_SLCACTL_UCC_SHIFT 8 184 # define V3D_SLCACTL_ICC_MASK V3D_MASK(3, 0) 185 # define V3D_SLCACTL_ICC_SHIFT 0 186 187 #define V3D_CTL_L2TCACTL 0x00030 188 # define V3D_L2TCACTL_TMUWCF BIT(8) 189 # define V3D_L2TCACTL_L2T_NO_WM BIT(4) 190 # define V3D_L2TCACTL_FLM_FLUSH 0 191 # define V3D_L2TCACTL_FLM_CLEAR 1 192 # define V3D_L2TCACTL_FLM_CLEAN 2 193 # define V3D_L2TCACTL_FLM_MASK V3D_MASK(2, 1) 194 # define V3D_L2TCACTL_FLM_SHIFT 1 195 # define V3D_L2TCACTL_L2TFLS BIT(0) 196 #define V3D_CTL_L2TFLSTA 0x00034 197 #define V3D_CTL_L2TFLEND 0x00038 198 199 #define V3D_CTL_INT_STS 0x00050 200 #define V3D_CTL_INT_SET 0x00054 201 #define V3D_CTL_INT_CLR 0x00058 202 #define V3D_CTL_INT_MSK_STS 0x0005c 203 #define V3D_CTL_INT_MSK_SET 0x00060 204 #define V3D_CTL_INT_MSK_CLR 0x00064 205 # define V3D_INT_QPU_MASK V3D_MASK(27, 16) 206 # define V3D_INT_QPU_SHIFT 16 207 # define V3D_INT_GMPV BIT(5) 208 # define V3D_INT_TRFB BIT(4) 209 # define V3D_INT_SPILLUSE BIT(3) 210 # define V3D_INT_OUTOMEM BIT(2) 211 # define V3D_INT_FLDONE BIT(1) 212 # define V3D_INT_FRDONE BIT(0) 213 214 #define V3D_CLE_CT0CS 0x00100 215 #define V3D_CLE_CT1CS 0x00104 216 #define V3D_CLE_CTNCS(n) (V3D_CLE_CT0CS + 4 * n) 217 #define V3D_CLE_CT0EA 0x00108 218 #define V3D_CLE_CT1EA 0x0010c 219 #define V3D_CLE_CTNEA(n) (V3D_CLE_CT0EA + 4 * n) 220 #define V3D_CLE_CT0CA 0x00110 221 #define V3D_CLE_CT1CA 0x00114 222 #define V3D_CLE_CTNCA(n) (V3D_CLE_CT0CA + 4 * n) 223 #define V3D_CLE_CT0RA 0x00118 224 #define V3D_CLE_CT1RA 0x0011c 225 #define V3D_CLE_CT0LC 0x00120 226 #define V3D_CLE_CT1LC 0x00124 227 #define V3D_CLE_CT0PC 0x00128 228 #define V3D_CLE_CT1PC 0x0012c 229 #define V3D_CLE_PCS 0x00130 230 #define V3D_CLE_BFC 0x00134 231 #define V3D_CLE_RFC 0x00138 232 #define V3D_CLE_TFBC 0x0013c 233 #define V3D_CLE_TFIT 0x00140 234 #define V3D_CLE_CT1CFG 0x00144 235 #define V3D_CLE_CT1TILECT 0x00148 236 #define V3D_CLE_CT1TSKIP 0x0014c 237 #define V3D_CLE_CT1PTCT 0x00150 238 #define V3D_CLE_CT0SYNC 0x00154 239 #define V3D_CLE_CT1SYNC 0x00158 240 #define V3D_CLE_CT0QTS 0x0015c 241 # define V3D_CLE_CT0QTS_ENABLE BIT(1) 242 #define V3D_CLE_CT0QBA 0x00160 243 #define V3D_CLE_CT1QBA 0x00164 244 #define V3D_CLE_CTNQBA(n) (V3D_CLE_CT0QBA + 4 * n) 245 #define V3D_CLE_CT0QEA 0x00168 246 #define V3D_CLE_CT1QEA 0x0016c 247 #define V3D_CLE_CTNQEA(n) (V3D_CLE_CT0QEA + 4 * n) 248 #define V3D_CLE_CT0QMA 0x00170 249 #define V3D_CLE_CT0QMS 0x00174 250 #define V3D_CLE_CT1QCFG 0x00178 251 /* If set without ETPROC, entirely skip tiles with no primitives. */ 252 # define V3D_CLE_QCFG_ETFILT BIT(7) 253 /* If set with ETFILT, just write the clear color to tiles with no 254 * primitives. 255 */ 256 # define V3D_CLE_QCFG_ETPROC BIT(6) 257 # define V3D_CLE_QCFG_ETSFLUSH BIT(1) 258 # define V3D_CLE_QCFG_MCDIS BIT(0) 259 260 #define V3D_PTB_BPCA 0x00300 261 #define V3D_PTB_BPCS 0x00304 262 #define V3D_PTB_BPOA 0x00308 263 #define V3D_PTB_BPOS 0x0030c 264 265 #define V3D_PTB_BXCF 0x00310 266 # define V3D_PTB_BXCF_RWORDERDISA BIT(1) 267 # define V3D_PTB_BXCF_CLIPDISA BIT(0) 268 269 #define V3D_GMP_STATUS 0x00800 270 # define V3D_GMP_STATUS_GMPRST BIT(31) 271 # define V3D_GMP_STATUS_WR_COUNT_MASK V3D_MASK(30, 24) 272 # define V3D_GMP_STATUS_WR_COUNT_SHIFT 24 273 # define V3D_GMP_STATUS_RD_COUNT_MASK V3D_MASK(22, 16) 274 # define V3D_GMP_STATUS_RD_COUNT_SHIFT 16 275 # define V3D_GMP_STATUS_WR_ACTIVE BIT(5) 276 # define V3D_GMP_STATUS_RD_ACTIVE BIT(4) 277 # define V3D_GMP_STATUS_CFG_BUSY BIT(3) 278 # define V3D_GMP_STATUS_CNTOVF BIT(2) 279 # define V3D_GMP_STATUS_INVPROT BIT(1) 280 # define V3D_GMP_STATUS_VIO BIT(0) 281 282 #define V3D_GMP_CFG 0x00804 283 # define V3D_GMP_CFG_LBURSTEN BIT(3) 284 # define V3D_GMP_CFG_PGCRSEN BIT() 285 # define V3D_GMP_CFG_STOP_REQ BIT(1) 286 # define V3D_GMP_CFG_PROT_ENABLE BIT(0) 287 288 #define V3D_GMP_VIO_ADDR 0x00808 289 #define V3D_GMP_VIO_TYPE 0x0080c 290 #define V3D_GMP_TABLE_ADDR 0x00810 291 #define V3D_GMP_CLEAR_LOAD 0x00814 292 #define V3D_GMP_PRESERVE_LOAD 0x00818 293 #define V3D_GMP_VALID_LINES 0x00820 294 295 #endif /* V3D_REGS_H */ 296