1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 /** 5 * DOC: Interrupt management for the V3D engine 6 * 7 * When we take a bin, render, TFU done, or CSD done interrupt, we 8 * need to signal the fence for that job so that the scheduler can 9 * queue up the next one and unblock any waiters. 10 * 11 * When we take the binner out of memory interrupt, we need to 12 * allocate some new memory and pass it to the binner so that the 13 * current job can make progress. 14 */ 15 16 #include <linux/platform_device.h> 17 18 #include "v3d_drv.h" 19 #include "v3d_regs.h" 20 #include "v3d_trace.h" 21 22 #define V3D_CORE_IRQS ((u32)(V3D_INT_OUTOMEM | \ 23 V3D_INT_FLDONE | \ 24 V3D_INT_FRDONE | \ 25 V3D_INT_CSDDONE | \ 26 V3D_INT_GMPV)) 27 28 #define V3D_HUB_IRQS ((u32)(V3D_HUB_INT_MMU_WRV | \ 29 V3D_HUB_INT_MMU_PTI | \ 30 V3D_HUB_INT_MMU_CAP | \ 31 V3D_HUB_INT_TFUC)) 32 33 static irqreturn_t 34 v3d_hub_irq(int irq, void *arg); 35 36 static void 37 v3d_overflow_mem_work(struct work_struct *work) 38 { 39 struct v3d_dev *v3d = 40 container_of(work, struct v3d_dev, overflow_mem_work); 41 struct drm_device *dev = &v3d->drm; 42 struct v3d_bo *bo = v3d_bo_create(dev, NULL /* XXX: GMP */, 256 * 1024); 43 struct drm_gem_object *obj; 44 unsigned long irqflags; 45 46 if (IS_ERR(bo)) { 47 DRM_ERROR("Couldn't allocate binner overflow mem\n"); 48 return; 49 } 50 obj = &bo->base.base; 51 52 /* We lost a race, and our work task came in after the bin job 53 * completed and exited. This can happen because the HW 54 * signals OOM before it's fully OOM, so the binner might just 55 * barely complete. 56 * 57 * If we lose the race and our work task comes in after a new 58 * bin job got scheduled, that's fine. We'll just give them 59 * some binner pool anyway. 60 */ 61 spin_lock_irqsave(&v3d->job_lock, irqflags); 62 if (!v3d->bin_job) { 63 spin_unlock_irqrestore(&v3d->job_lock, irqflags); 64 goto out; 65 } 66 67 drm_gem_object_get(obj); 68 list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list); 69 spin_unlock_irqrestore(&v3d->job_lock, irqflags); 70 71 V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << PAGE_SHIFT); 72 V3D_CORE_WRITE(0, V3D_PTB_BPOS, obj->size); 73 74 out: 75 drm_gem_object_put(obj); 76 } 77 78 static irqreturn_t 79 v3d_irq(int irq, void *arg) 80 { 81 struct v3d_dev *v3d = arg; 82 u32 intsts; 83 irqreturn_t status = IRQ_NONE; 84 85 intsts = V3D_CORE_READ(0, V3D_CTL_INT_STS); 86 87 /* Acknowledge the interrupts we're handling here. */ 88 V3D_CORE_WRITE(0, V3D_CTL_INT_CLR, intsts); 89 90 if (intsts & V3D_INT_OUTOMEM) { 91 /* Note that the OOM status is edge signaled, so the 92 * interrupt won't happen again until the we actually 93 * add more memory. Also, as of V3D 4.1, FLDONE won't 94 * be reported until any OOM state has been cleared. 95 */ 96 schedule_work(&v3d->overflow_mem_work); 97 status = IRQ_HANDLED; 98 } 99 100 if (intsts & V3D_INT_FLDONE) { 101 struct v3d_fence *fence = 102 to_v3d_fence(v3d->bin_job->base.irq_fence); 103 104 trace_v3d_bcl_irq(&v3d->drm, fence->seqno); 105 106 v3d->bin_job = NULL; 107 dma_fence_signal(&fence->base); 108 109 status = IRQ_HANDLED; 110 } 111 112 if (intsts & V3D_INT_FRDONE) { 113 struct v3d_fence *fence = 114 to_v3d_fence(v3d->render_job->base.irq_fence); 115 116 trace_v3d_rcl_irq(&v3d->drm, fence->seqno); 117 118 v3d->render_job = NULL; 119 dma_fence_signal(&fence->base); 120 121 status = IRQ_HANDLED; 122 } 123 124 if (intsts & V3D_INT_CSDDONE) { 125 struct v3d_fence *fence = 126 to_v3d_fence(v3d->csd_job->base.irq_fence); 127 128 trace_v3d_csd_irq(&v3d->drm, fence->seqno); 129 130 v3d->csd_job = NULL; 131 dma_fence_signal(&fence->base); 132 133 status = IRQ_HANDLED; 134 } 135 136 /* We shouldn't be triggering these if we have GMP in 137 * always-allowed mode. 138 */ 139 if (intsts & V3D_INT_GMPV) 140 dev_err(v3d->drm.dev, "GMP violation\n"); 141 142 /* V3D 4.2 wires the hub and core IRQs together, so if we & 143 * didn't see the common one then check hub for MMU IRQs. 144 */ 145 if (v3d->single_irq_line && status == IRQ_NONE) 146 return v3d_hub_irq(irq, arg); 147 148 return status; 149 } 150 151 static irqreturn_t 152 v3d_hub_irq(int irq, void *arg) 153 { 154 struct v3d_dev *v3d = arg; 155 u32 intsts; 156 irqreturn_t status = IRQ_NONE; 157 158 intsts = V3D_READ(V3D_HUB_INT_STS); 159 160 /* Acknowledge the interrupts we're handling here. */ 161 V3D_WRITE(V3D_HUB_INT_CLR, intsts); 162 163 if (intsts & V3D_HUB_INT_TFUC) { 164 struct v3d_fence *fence = 165 to_v3d_fence(v3d->tfu_job->base.irq_fence); 166 167 trace_v3d_tfu_irq(&v3d->drm, fence->seqno); 168 169 v3d->tfu_job = NULL; 170 dma_fence_signal(&fence->base); 171 172 status = IRQ_HANDLED; 173 } 174 175 if (intsts & (V3D_HUB_INT_MMU_WRV | 176 V3D_HUB_INT_MMU_PTI | 177 V3D_HUB_INT_MMU_CAP)) { 178 u32 axi_id = V3D_READ(V3D_MMU_VIO_ID); 179 u64 vio_addr = ((u64)V3D_READ(V3D_MMU_VIO_ADDR) << 180 (v3d->va_width - 32)); 181 static const char *const v3d41_axi_ids[] = { 182 "L2T", 183 "PTB", 184 "PSE", 185 "TLB", 186 "CLE", 187 "TFU", 188 "MMU", 189 "GMP", 190 }; 191 const char *client = "?"; 192 193 V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL)); 194 195 if (v3d->ver >= 41) { 196 axi_id = axi_id >> 5; 197 if (axi_id < ARRAY_SIZE(v3d41_axi_ids)) 198 client = v3d41_axi_ids[axi_id]; 199 } 200 201 dev_err(v3d->drm.dev, "MMU error from client %s (%d) at 0x%llx%s%s%s\n", 202 client, axi_id, (long long)vio_addr, 203 ((intsts & V3D_HUB_INT_MMU_WRV) ? 204 ", write violation" : ""), 205 ((intsts & V3D_HUB_INT_MMU_PTI) ? 206 ", pte invalid" : ""), 207 ((intsts & V3D_HUB_INT_MMU_CAP) ? 208 ", cap exceeded" : "")); 209 status = IRQ_HANDLED; 210 } 211 212 return status; 213 } 214 215 int 216 v3d_irq_init(struct v3d_dev *v3d) 217 { 218 int irq1, ret, core; 219 220 INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work); 221 222 /* Clear any pending interrupts someone might have left around 223 * for us. 224 */ 225 for (core = 0; core < v3d->cores; core++) 226 V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS); 227 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS); 228 229 irq1 = platform_get_irq_optional(v3d_to_pdev(v3d), 1); 230 if (irq1 == -EPROBE_DEFER) 231 return irq1; 232 if (irq1 > 0) { 233 ret = devm_request_irq(v3d->drm.dev, irq1, 234 v3d_irq, IRQF_SHARED, 235 "v3d_core0", v3d); 236 if (ret) 237 goto fail; 238 ret = devm_request_irq(v3d->drm.dev, 239 platform_get_irq(v3d_to_pdev(v3d), 0), 240 v3d_hub_irq, IRQF_SHARED, 241 "v3d_hub", v3d); 242 if (ret) 243 goto fail; 244 } else { 245 v3d->single_irq_line = true; 246 247 ret = devm_request_irq(v3d->drm.dev, 248 platform_get_irq(v3d_to_pdev(v3d), 0), 249 v3d_irq, IRQF_SHARED, 250 "v3d", v3d); 251 if (ret) 252 goto fail; 253 } 254 255 v3d_irq_enable(v3d); 256 return 0; 257 258 fail: 259 if (ret != -EPROBE_DEFER) 260 dev_err(v3d->drm.dev, "IRQ setup failed: %d\n", ret); 261 return ret; 262 } 263 264 void 265 v3d_irq_enable(struct v3d_dev *v3d) 266 { 267 int core; 268 269 /* Enable our set of interrupts, masking out any others. */ 270 for (core = 0; core < v3d->cores; core++) { 271 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS); 272 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS); 273 } 274 275 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS); 276 V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS); 277 } 278 279 void 280 v3d_irq_disable(struct v3d_dev *v3d) 281 { 282 int core; 283 284 /* Disable all interrupts. */ 285 for (core = 0; core < v3d->cores; core++) 286 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~0); 287 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0); 288 289 /* Clear any pending interrupts we might have left. */ 290 for (core = 0; core < v3d->cores; core++) 291 V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS); 292 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS); 293 294 cancel_work_sync(&v3d->overflow_mem_work); 295 } 296 297 /** Reinitializes interrupt registers when a GPU reset is performed. */ 298 void v3d_irq_reset(struct v3d_dev *v3d) 299 { 300 v3d_irq_enable(v3d); 301 } 302