157692c94SEric Anholt // SPDX-License-Identifier: GPL-2.0+
257692c94SEric Anholt /* Copyright (C) 2014-2018 Broadcom */
357692c94SEric Anholt
457692c94SEric Anholt /**
557692c94SEric Anholt * DOC: Interrupt management for the V3D engine
657692c94SEric Anholt *
7d223f98fSEric Anholt * When we take a bin, render, TFU done, or CSD done interrupt, we
8d223f98fSEric Anholt * need to signal the fence for that job so that the scheduler can
9d223f98fSEric Anholt * queue up the next one and unblock any waiters.
1057692c94SEric Anholt *
1157692c94SEric Anholt * When we take the binner out of memory interrupt, we need to
1257692c94SEric Anholt * allocate some new memory and pass it to the binner so that the
1357692c94SEric Anholt * current job can make progress.
1457692c94SEric Anholt */
1557692c94SEric Anholt
16220989e7SSam Ravnborg #include <linux/platform_device.h>
17220989e7SSam Ravnborg
1857692c94SEric Anholt #include "v3d_drv.h"
1957692c94SEric Anholt #include "v3d_regs.h"
2055a9b748SEric Anholt #include "v3d_trace.h"
2157692c94SEric Anholt
2257692c94SEric Anholt #define V3D_CORE_IRQS ((u32)(V3D_INT_OUTOMEM | \
2357692c94SEric Anholt V3D_INT_FLDONE | \
2457692c94SEric Anholt V3D_INT_FRDONE | \
25d223f98fSEric Anholt V3D_INT_CSDDONE | \
2657692c94SEric Anholt V3D_INT_GMPV))
2757692c94SEric Anholt
2857692c94SEric Anholt #define V3D_HUB_IRQS ((u32)(V3D_HUB_INT_MMU_WRV | \
2957692c94SEric Anholt V3D_HUB_INT_MMU_PTI | \
301584f16cSEric Anholt V3D_HUB_INT_MMU_CAP | \
311584f16cSEric Anholt V3D_HUB_INT_TFUC))
3257692c94SEric Anholt
33eea9b97bSEric Anholt static irqreturn_t
34eea9b97bSEric Anholt v3d_hub_irq(int irq, void *arg);
35eea9b97bSEric Anholt
3657692c94SEric Anholt static void
v3d_overflow_mem_work(struct work_struct * work)3757692c94SEric Anholt v3d_overflow_mem_work(struct work_struct *work)
3857692c94SEric Anholt {
3957692c94SEric Anholt struct v3d_dev *v3d =
4057692c94SEric Anholt container_of(work, struct v3d_dev, overflow_mem_work);
4157692c94SEric Anholt struct drm_device *dev = &v3d->drm;
4257692c94SEric Anholt struct v3d_bo *bo = v3d_bo_create(dev, NULL /* XXX: GMP */, 256 * 1024);
4340609d48SEric Anholt struct drm_gem_object *obj;
4457692c94SEric Anholt unsigned long irqflags;
4557692c94SEric Anholt
4657692c94SEric Anholt if (IS_ERR(bo)) {
4757692c94SEric Anholt DRM_ERROR("Couldn't allocate binner overflow mem\n");
4857692c94SEric Anholt return;
4957692c94SEric Anholt }
5040609d48SEric Anholt obj = &bo->base.base;
5157692c94SEric Anholt
5257692c94SEric Anholt /* We lost a race, and our work task came in after the bin job
5357692c94SEric Anholt * completed and exited. This can happen because the HW
5457692c94SEric Anholt * signals OOM before it's fully OOM, so the binner might just
5557692c94SEric Anholt * barely complete.
5657692c94SEric Anholt *
5757692c94SEric Anholt * If we lose the race and our work task comes in after a new
5857692c94SEric Anholt * bin job got scheduled, that's fine. We'll just give them
5957692c94SEric Anholt * some binner pool anyway.
6057692c94SEric Anholt */
6157692c94SEric Anholt spin_lock_irqsave(&v3d->job_lock, irqflags);
6257692c94SEric Anholt if (!v3d->bin_job) {
6357692c94SEric Anholt spin_unlock_irqrestore(&v3d->job_lock, irqflags);
6457692c94SEric Anholt goto out;
6557692c94SEric Anholt }
6657692c94SEric Anholt
6740609d48SEric Anholt drm_gem_object_get(obj);
68a783a09eSEric Anholt list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list);
6957692c94SEric Anholt spin_unlock_irqrestore(&v3d->job_lock, irqflags);
7057692c94SEric Anholt
7157692c94SEric Anholt V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << PAGE_SHIFT);
7240609d48SEric Anholt V3D_CORE_WRITE(0, V3D_PTB_BPOS, obj->size);
7357692c94SEric Anholt
7457692c94SEric Anholt out:
752b86189eSEmil Velikov drm_gem_object_put(obj);
7657692c94SEric Anholt }
7757692c94SEric Anholt
7857692c94SEric Anholt static irqreturn_t
v3d_irq(int irq,void * arg)7957692c94SEric Anholt v3d_irq(int irq, void *arg)
8057692c94SEric Anholt {
8157692c94SEric Anholt struct v3d_dev *v3d = arg;
8257692c94SEric Anholt u32 intsts;
8357692c94SEric Anholt irqreturn_t status = IRQ_NONE;
8457692c94SEric Anholt
8557692c94SEric Anholt intsts = V3D_CORE_READ(0, V3D_CTL_INT_STS);
8657692c94SEric Anholt
8757692c94SEric Anholt /* Acknowledge the interrupts we're handling here. */
8857692c94SEric Anholt V3D_CORE_WRITE(0, V3D_CTL_INT_CLR, intsts);
8957692c94SEric Anholt
9057692c94SEric Anholt if (intsts & V3D_INT_OUTOMEM) {
9157692c94SEric Anholt /* Note that the OOM status is edge signaled, so the
9257692c94SEric Anholt * interrupt won't happen again until the we actually
93ad8d68b2SEric Anholt * add more memory. Also, as of V3D 4.1, FLDONE won't
94ad8d68b2SEric Anholt * be reported until any OOM state has been cleared.
9557692c94SEric Anholt */
9657692c94SEric Anholt schedule_work(&v3d->overflow_mem_work);
9757692c94SEric Anholt status = IRQ_HANDLED;
9857692c94SEric Anholt }
9957692c94SEric Anholt
10057692c94SEric Anholt if (intsts & V3D_INT_FLDONE) {
10155a9b748SEric Anholt struct v3d_fence *fence =
102a783a09eSEric Anholt to_v3d_fence(v3d->bin_job->base.irq_fence);
10355a9b748SEric Anholt
10455a9b748SEric Anholt trace_v3d_bcl_irq(&v3d->drm, fence->seqno);
10555a9b748SEric Anholt dma_fence_signal(&fence->base);
10657692c94SEric Anholt status = IRQ_HANDLED;
10757692c94SEric Anholt }
10857692c94SEric Anholt
10957692c94SEric Anholt if (intsts & V3D_INT_FRDONE) {
11055a9b748SEric Anholt struct v3d_fence *fence =
111a783a09eSEric Anholt to_v3d_fence(v3d->render_job->base.irq_fence);
11255a9b748SEric Anholt
11355a9b748SEric Anholt trace_v3d_rcl_irq(&v3d->drm, fence->seqno);
11455a9b748SEric Anholt dma_fence_signal(&fence->base);
11557692c94SEric Anholt status = IRQ_HANDLED;
11657692c94SEric Anholt }
11757692c94SEric Anholt
118d223f98fSEric Anholt if (intsts & V3D_INT_CSDDONE) {
119d223f98fSEric Anholt struct v3d_fence *fence =
120d223f98fSEric Anholt to_v3d_fence(v3d->csd_job->base.irq_fence);
121d223f98fSEric Anholt
122d223f98fSEric Anholt trace_v3d_csd_irq(&v3d->drm, fence->seqno);
123d223f98fSEric Anholt dma_fence_signal(&fence->base);
124d223f98fSEric Anholt status = IRQ_HANDLED;
125d223f98fSEric Anholt }
126d223f98fSEric Anholt
12757692c94SEric Anholt /* We shouldn't be triggering these if we have GMP in
12857692c94SEric Anholt * always-allowed mode.
12957692c94SEric Anholt */
13057692c94SEric Anholt if (intsts & V3D_INT_GMPV)
131bc662528SDaniel Vetter dev_err(v3d->drm.dev, "GMP violation\n");
13257692c94SEric Anholt
133eea9b97bSEric Anholt /* V3D 4.2 wires the hub and core IRQs together, so if we &
134eea9b97bSEric Anholt * didn't see the common one then check hub for MMU IRQs.
135eea9b97bSEric Anholt */
136eea9b97bSEric Anholt if (v3d->single_irq_line && status == IRQ_NONE)
137eea9b97bSEric Anholt return v3d_hub_irq(irq, arg);
138eea9b97bSEric Anholt
13957692c94SEric Anholt return status;
14057692c94SEric Anholt }
14157692c94SEric Anholt
14257692c94SEric Anholt static irqreturn_t
v3d_hub_irq(int irq,void * arg)14357692c94SEric Anholt v3d_hub_irq(int irq, void *arg)
14457692c94SEric Anholt {
14557692c94SEric Anholt struct v3d_dev *v3d = arg;
14657692c94SEric Anholt u32 intsts;
14757692c94SEric Anholt irqreturn_t status = IRQ_NONE;
14857692c94SEric Anholt
14957692c94SEric Anholt intsts = V3D_READ(V3D_HUB_INT_STS);
15057692c94SEric Anholt
15157692c94SEric Anholt /* Acknowledge the interrupts we're handling here. */
15257692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_CLR, intsts);
15357692c94SEric Anholt
1541584f16cSEric Anholt if (intsts & V3D_HUB_INT_TFUC) {
15555a9b748SEric Anholt struct v3d_fence *fence =
156a783a09eSEric Anholt to_v3d_fence(v3d->tfu_job->base.irq_fence);
15755a9b748SEric Anholt
15855a9b748SEric Anholt trace_v3d_tfu_irq(&v3d->drm, fence->seqno);
15955a9b748SEric Anholt dma_fence_signal(&fence->base);
1601584f16cSEric Anholt status = IRQ_HANDLED;
1611584f16cSEric Anholt }
1621584f16cSEric Anholt
16357692c94SEric Anholt if (intsts & (V3D_HUB_INT_MMU_WRV |
16457692c94SEric Anholt V3D_HUB_INT_MMU_PTI |
16557692c94SEric Anholt V3D_HUB_INT_MMU_CAP)) {
16657692c94SEric Anholt u32 axi_id = V3D_READ(V3D_MMU_VIO_ID);
16738c2c791SEric Anholt u64 vio_addr = ((u64)V3D_READ(V3D_MMU_VIO_ADDR) <<
16838c2c791SEric Anholt (v3d->va_width - 32));
16938c2c791SEric Anholt static const char *const v3d41_axi_ids[] = {
17038c2c791SEric Anholt "L2T",
17138c2c791SEric Anholt "PTB",
17238c2c791SEric Anholt "PSE",
17338c2c791SEric Anholt "TLB",
17438c2c791SEric Anholt "CLE",
17538c2c791SEric Anholt "TFU",
17638c2c791SEric Anholt "MMU",
17738c2c791SEric Anholt "GMP",
17838c2c791SEric Anholt };
17938c2c791SEric Anholt const char *client = "?";
18057692c94SEric Anholt
181*545d9d78SPhil Elwell V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));
18238c2c791SEric Anholt
18338c2c791SEric Anholt if (v3d->ver >= 41) {
18438c2c791SEric Anholt axi_id = axi_id >> 5;
18538c2c791SEric Anholt if (axi_id < ARRAY_SIZE(v3d41_axi_ids))
18638c2c791SEric Anholt client = v3d41_axi_ids[axi_id];
18738c2c791SEric Anholt }
18838c2c791SEric Anholt
189bc662528SDaniel Vetter dev_err(v3d->drm.dev, "MMU error from client %s (%d) at 0x%llx%s%s%s\n",
19038c2c791SEric Anholt client, axi_id, (long long)vio_addr,
19157692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_WRV) ?
19257692c94SEric Anholt ", write violation" : ""),
19357692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_PTI) ?
19457692c94SEric Anholt ", pte invalid" : ""),
19557692c94SEric Anholt ((intsts & V3D_HUB_INT_MMU_CAP) ?
19657692c94SEric Anholt ", cap exceeded" : ""));
19757692c94SEric Anholt status = IRQ_HANDLED;
19857692c94SEric Anholt }
19957692c94SEric Anholt
20057692c94SEric Anholt return status;
20157692c94SEric Anholt }
20257692c94SEric Anholt
203fc227715SEric Anholt int
v3d_irq_init(struct v3d_dev * v3d)20457692c94SEric Anholt v3d_irq_init(struct v3d_dev *v3d)
20557692c94SEric Anholt {
206eea9b97bSEric Anholt int irq1, ret, core;
20757692c94SEric Anholt
20857692c94SEric Anholt INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work);
20957692c94SEric Anholt
21057692c94SEric Anholt /* Clear any pending interrupts someone might have left around
21157692c94SEric Anholt * for us.
21257692c94SEric Anholt */
21357692c94SEric Anholt for (core = 0; core < v3d->cores; core++)
21457692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS);
21557692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS);
21657692c94SEric Anholt
217f4f3beb7SNicolas Saenz Julienne irq1 = platform_get_irq_optional(v3d_to_pdev(v3d), 1);
218eea9b97bSEric Anholt if (irq1 == -EPROBE_DEFER)
219eea9b97bSEric Anholt return irq1;
220eea9b97bSEric Anholt if (irq1 > 0) {
221bc662528SDaniel Vetter ret = devm_request_irq(v3d->drm.dev, irq1,
222eea9b97bSEric Anholt v3d_irq, IRQF_SHARED,
223eea9b97bSEric Anholt "v3d_core0", v3d);
224eea9b97bSEric Anholt if (ret)
225eea9b97bSEric Anholt goto fail;
2260df3ac76SDaniel Vetter ret = devm_request_irq(v3d->drm.dev,
2270df3ac76SDaniel Vetter platform_get_irq(v3d_to_pdev(v3d), 0),
22857692c94SEric Anholt v3d_hub_irq, IRQF_SHARED,
22957692c94SEric Anholt "v3d_hub", v3d);
230fc227715SEric Anholt if (ret)
231fc227715SEric Anholt goto fail;
232eea9b97bSEric Anholt } else {
233eea9b97bSEric Anholt v3d->single_irq_line = true;
234fc227715SEric Anholt
2350df3ac76SDaniel Vetter ret = devm_request_irq(v3d->drm.dev,
2360df3ac76SDaniel Vetter platform_get_irq(v3d_to_pdev(v3d), 0),
23757692c94SEric Anholt v3d_irq, IRQF_SHARED,
238eea9b97bSEric Anholt "v3d", v3d);
23957692c94SEric Anholt if (ret)
240fc227715SEric Anholt goto fail;
241eea9b97bSEric Anholt }
24257692c94SEric Anholt
24357692c94SEric Anholt v3d_irq_enable(v3d);
244fc227715SEric Anholt return 0;
245fc227715SEric Anholt
246fc227715SEric Anholt fail:
247fc227715SEric Anholt if (ret != -EPROBE_DEFER)
248bc662528SDaniel Vetter dev_err(v3d->drm.dev, "IRQ setup failed: %d\n", ret);
249fc227715SEric Anholt return ret;
25057692c94SEric Anholt }
25157692c94SEric Anholt
25257692c94SEric Anholt void
v3d_irq_enable(struct v3d_dev * v3d)25357692c94SEric Anholt v3d_irq_enable(struct v3d_dev *v3d)
25457692c94SEric Anholt {
25557692c94SEric Anholt int core;
25657692c94SEric Anholt
25757692c94SEric Anholt /* Enable our set of interrupts, masking out any others. */
25857692c94SEric Anholt for (core = 0; core < v3d->cores; core++) {
25957692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS);
26057692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS);
26157692c94SEric Anholt }
26257692c94SEric Anholt
26357692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS);
26457692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS);
26557692c94SEric Anholt }
26657692c94SEric Anholt
26757692c94SEric Anholt void
v3d_irq_disable(struct v3d_dev * v3d)26857692c94SEric Anholt v3d_irq_disable(struct v3d_dev *v3d)
26957692c94SEric Anholt {
27057692c94SEric Anholt int core;
27157692c94SEric Anholt
27257692c94SEric Anholt /* Disable all interrupts. */
27357692c94SEric Anholt for (core = 0; core < v3d->cores; core++)
27457692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~0);
27557692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0);
27657692c94SEric Anholt
27757692c94SEric Anholt /* Clear any pending interrupts we might have left. */
27857692c94SEric Anholt for (core = 0; core < v3d->cores; core++)
27957692c94SEric Anholt V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS);
28057692c94SEric Anholt V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS);
28157692c94SEric Anholt
28257692c94SEric Anholt cancel_work_sync(&v3d->overflow_mem_work);
28357692c94SEric Anholt }
28457692c94SEric Anholt
28557692c94SEric Anholt /** Reinitializes interrupt registers when a GPU reset is performed. */
v3d_irq_reset(struct v3d_dev * v3d)28657692c94SEric Anholt void v3d_irq_reset(struct v3d_dev *v3d)
28757692c94SEric Anholt {
28857692c94SEric Anholt v3d_irq_enable(v3d);
28957692c94SEric Anholt }
290