1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2015-2018 Broadcom */ 3 4 #include <linux/reservation.h> 5 #include <drm/drmP.h> 6 #include <drm/drm_encoder.h> 7 #include <drm/drm_gem.h> 8 #include <drm/gpu_scheduler.h> 9 10 #define GMP_GRANULARITY (128 * 1024) 11 12 /* Enum for each of the V3D queues. We maintain various queue 13 * tracking as an array because at some point we'll want to support 14 * the TFU (texture formatting unit) as another queue. 15 */ 16 enum v3d_queue { 17 V3D_BIN, 18 V3D_RENDER, 19 }; 20 21 #define V3D_MAX_QUEUES (V3D_RENDER + 1) 22 23 struct v3d_queue_state { 24 struct drm_gpu_scheduler sched; 25 26 u64 fence_context; 27 u64 emit_seqno; 28 }; 29 30 struct v3d_dev { 31 struct drm_device drm; 32 33 /* Short representation (e.g. 33, 41) of the V3D tech version 34 * and revision. 35 */ 36 int ver; 37 38 struct device *dev; 39 struct platform_device *pdev; 40 void __iomem *hub_regs; 41 void __iomem *core_regs[3]; 42 void __iomem *bridge_regs; 43 void __iomem *gca_regs; 44 struct clk *clk; 45 46 /* Virtual and DMA addresses of the single shared page table. */ 47 volatile u32 *pt; 48 dma_addr_t pt_paddr; 49 50 /* Virtual and DMA addresses of the MMU's scratch page. When 51 * a read or write is invalid in the MMU, it will be 52 * redirected here. 53 */ 54 void *mmu_scratch; 55 dma_addr_t mmu_scratch_paddr; 56 57 /* Number of V3D cores. */ 58 u32 cores; 59 60 /* Allocator managing the address space. All units are in 61 * number of pages. 62 */ 63 struct drm_mm mm; 64 spinlock_t mm_lock; 65 66 struct work_struct overflow_mem_work; 67 68 struct v3d_exec_info *bin_job; 69 struct v3d_exec_info *render_job; 70 71 struct v3d_queue_state queue[V3D_MAX_QUEUES]; 72 73 /* Spinlock used to synchronize the overflow memory 74 * management against bin job submission. 75 */ 76 spinlock_t job_lock; 77 78 /* Protects bo_stats */ 79 struct mutex bo_lock; 80 81 /* Lock taken when resetting the GPU, to keep multiple 82 * processes from trying to park the scheduler threads and 83 * reset at once. 84 */ 85 struct mutex reset_lock; 86 87 /* Lock taken when creating and pushing the GPU scheduler 88 * jobs, to keep the sched-fence seqnos in order. 89 */ 90 struct mutex sched_lock; 91 92 struct { 93 u32 num_allocated; 94 u32 pages_allocated; 95 } bo_stats; 96 }; 97 98 static inline struct v3d_dev * 99 to_v3d_dev(struct drm_device *dev) 100 { 101 return (struct v3d_dev *)dev->dev_private; 102 } 103 104 /* The per-fd struct, which tracks the MMU mappings. */ 105 struct v3d_file_priv { 106 struct v3d_dev *v3d; 107 108 struct drm_sched_entity sched_entity[V3D_MAX_QUEUES]; 109 }; 110 111 /* Tracks a mapping of a BO into a per-fd address space */ 112 struct v3d_vma { 113 struct v3d_page_table *pt; 114 struct list_head list; /* entry in v3d_bo.vmas */ 115 }; 116 117 struct v3d_bo { 118 struct drm_gem_object base; 119 120 struct mutex lock; 121 122 struct drm_mm_node node; 123 124 u32 pages_refcount; 125 struct page **pages; 126 struct sg_table *sgt; 127 void *vaddr; 128 129 struct list_head vmas; /* list of v3d_vma */ 130 131 /* List entry for the BO's position in 132 * v3d_exec_info->unref_list 133 */ 134 struct list_head unref_head; 135 136 /* normally (resv == &_resv) except for imported bo's */ 137 struct reservation_object *resv; 138 struct reservation_object _resv; 139 }; 140 141 static inline struct v3d_bo * 142 to_v3d_bo(struct drm_gem_object *bo) 143 { 144 return (struct v3d_bo *)bo; 145 } 146 147 struct v3d_fence { 148 struct dma_fence base; 149 struct drm_device *dev; 150 /* v3d seqno for signaled() test */ 151 u64 seqno; 152 enum v3d_queue queue; 153 }; 154 155 static inline struct v3d_fence * 156 to_v3d_fence(struct dma_fence *fence) 157 { 158 return (struct v3d_fence *)fence; 159 } 160 161 #define V3D_READ(offset) readl(v3d->hub_regs + offset) 162 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset) 163 164 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset) 165 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset) 166 167 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset) 168 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset) 169 170 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset) 171 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset) 172 173 struct v3d_job { 174 struct drm_sched_job base; 175 176 struct v3d_exec_info *exec; 177 178 /* An optional fence userspace can pass in for the job to depend on. */ 179 struct dma_fence *in_fence; 180 181 /* v3d fence to be signaled by IRQ handler when the job is complete. */ 182 struct dma_fence *done_fence; 183 184 /* GPU virtual addresses of the start/end of the CL job. */ 185 u32 start, end; 186 }; 187 188 struct v3d_exec_info { 189 struct v3d_dev *v3d; 190 191 struct v3d_job bin, render; 192 193 /* Fence for when the scheduler considers the binner to be 194 * done, for render to depend on. 195 */ 196 struct dma_fence *bin_done_fence; 197 198 struct kref refcount; 199 200 /* This is the array of BOs that were looked up at the start of exec. */ 201 struct v3d_bo **bo; 202 u32 bo_count; 203 204 /* List of overflow BOs used in the job that need to be 205 * released once the job is complete. 206 */ 207 struct list_head unref_list; 208 209 /* Submitted tile memory allocation start/size, tile state. */ 210 u32 qma, qms, qts; 211 }; 212 213 /** 214 * _wait_for - magic (register) wait macro 215 * 216 * Does the right thing for modeset paths when run under kdgb or similar atomic 217 * contexts. Note that it's important that we check the condition again after 218 * having timed out, since the timeout could be due to preemption or similar and 219 * we've never had a chance to check the condition before the timeout. 220 */ 221 #define wait_for(COND, MS) ({ \ 222 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ 223 int ret__ = 0; \ 224 while (!(COND)) { \ 225 if (time_after(jiffies, timeout__)) { \ 226 if (!(COND)) \ 227 ret__ = -ETIMEDOUT; \ 228 break; \ 229 } \ 230 msleep(1); \ 231 } \ 232 ret__; \ 233 }) 234 235 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) 236 { 237 /* nsecs_to_jiffies64() does not guard against overflow */ 238 if (NSEC_PER_SEC % HZ && 239 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) 240 return MAX_JIFFY_OFFSET; 241 242 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); 243 } 244 245 /* v3d_bo.c */ 246 void v3d_free_object(struct drm_gem_object *gem_obj); 247 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv, 248 size_t size); 249 int v3d_create_bo_ioctl(struct drm_device *dev, void *data, 250 struct drm_file *file_priv); 251 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data, 252 struct drm_file *file_priv); 253 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data, 254 struct drm_file *file_priv); 255 int v3d_gem_fault(struct vm_fault *vmf); 256 int v3d_mmap(struct file *filp, struct vm_area_struct *vma); 257 struct reservation_object *v3d_prime_res_obj(struct drm_gem_object *obj); 258 int v3d_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 259 struct sg_table *v3d_prime_get_sg_table(struct drm_gem_object *obj); 260 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev, 261 struct dma_buf_attachment *attach, 262 struct sg_table *sgt); 263 264 /* v3d_debugfs.c */ 265 int v3d_debugfs_init(struct drm_minor *minor); 266 267 /* v3d_fence.c */ 268 extern const struct dma_fence_ops v3d_fence_ops; 269 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue); 270 271 /* v3d_gem.c */ 272 int v3d_gem_init(struct drm_device *dev); 273 void v3d_gem_destroy(struct drm_device *dev); 274 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data, 275 struct drm_file *file_priv); 276 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data, 277 struct drm_file *file_priv); 278 void v3d_exec_put(struct v3d_exec_info *exec); 279 void v3d_reset(struct v3d_dev *v3d); 280 void v3d_invalidate_caches(struct v3d_dev *v3d); 281 void v3d_flush_caches(struct v3d_dev *v3d); 282 283 /* v3d_irq.c */ 284 void v3d_irq_init(struct v3d_dev *v3d); 285 void v3d_irq_enable(struct v3d_dev *v3d); 286 void v3d_irq_disable(struct v3d_dev *v3d); 287 void v3d_irq_reset(struct v3d_dev *v3d); 288 289 /* v3d_mmu.c */ 290 int v3d_mmu_get_offset(struct drm_file *file_priv, struct v3d_bo *bo, 291 u32 *offset); 292 int v3d_mmu_set_page_table(struct v3d_dev *v3d); 293 void v3d_mmu_insert_ptes(struct v3d_bo *bo); 294 void v3d_mmu_remove_ptes(struct v3d_bo *bo); 295 296 /* v3d_sched.c */ 297 int v3d_sched_init(struct v3d_dev *v3d); 298 void v3d_sched_fini(struct v3d_dev *v3d); 299