1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 /** 5 * DOC: Broadcom V3D Graphics Driver 6 * 7 * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs. 8 * For V3D 2.x support, see the VC4 driver. 9 * 10 * Currently only single-core rendering using the binner and renderer 11 * is supported. The TFU (texture formatting unit) and V3D 4.x's CSD 12 * (compute shader dispatch) are not yet supported. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/device.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/of_platform.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <drm/drm_fb_cma_helper.h> 23 #include <drm/drm_fb_helper.h> 24 25 #include "uapi/drm/v3d_drm.h" 26 #include "v3d_drv.h" 27 #include "v3d_regs.h" 28 29 #define DRIVER_NAME "v3d" 30 #define DRIVER_DESC "Broadcom V3D graphics" 31 #define DRIVER_DATE "20180419" 32 #define DRIVER_MAJOR 1 33 #define DRIVER_MINOR 0 34 #define DRIVER_PATCHLEVEL 0 35 36 #ifdef CONFIG_PM 37 static int v3d_runtime_suspend(struct device *dev) 38 { 39 struct drm_device *drm = dev_get_drvdata(dev); 40 struct v3d_dev *v3d = to_v3d_dev(drm); 41 42 v3d_irq_disable(v3d); 43 44 clk_disable_unprepare(v3d->clk); 45 46 return 0; 47 } 48 49 static int v3d_runtime_resume(struct device *dev) 50 { 51 struct drm_device *drm = dev_get_drvdata(dev); 52 struct v3d_dev *v3d = to_v3d_dev(drm); 53 int ret; 54 55 ret = clk_prepare_enable(v3d->clk); 56 if (ret != 0) 57 return ret; 58 59 /* XXX: VPM base */ 60 61 v3d_mmu_set_page_table(v3d); 62 v3d_irq_enable(v3d); 63 64 return 0; 65 } 66 #endif 67 68 static const struct dev_pm_ops v3d_v3d_pm_ops = { 69 SET_RUNTIME_PM_OPS(v3d_runtime_suspend, v3d_runtime_resume, NULL) 70 }; 71 72 static int v3d_get_param_ioctl(struct drm_device *dev, void *data, 73 struct drm_file *file_priv) 74 { 75 struct v3d_dev *v3d = to_v3d_dev(dev); 76 struct drm_v3d_get_param *args = data; 77 int ret; 78 static const u32 reg_map[] = { 79 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG, 80 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1, 81 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2, 82 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3, 83 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0, 84 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1, 85 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2, 86 }; 87 88 if (args->pad != 0) 89 return -EINVAL; 90 91 /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need 92 * to explicitly allow it in the "the register in our 93 * parameter map" check. 94 */ 95 if (args->param < ARRAY_SIZE(reg_map) && 96 (reg_map[args->param] || 97 args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) { 98 u32 offset = reg_map[args->param]; 99 100 if (args->value != 0) 101 return -EINVAL; 102 103 ret = pm_runtime_get_sync(v3d->dev); 104 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 && 105 args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) { 106 args->value = V3D_CORE_READ(0, offset); 107 } else { 108 args->value = V3D_READ(offset); 109 } 110 pm_runtime_mark_last_busy(v3d->dev); 111 pm_runtime_put_autosuspend(v3d->dev); 112 return 0; 113 } 114 115 /* Any params that aren't just register reads would go here. */ 116 117 DRM_DEBUG("Unknown parameter %d\n", args->param); 118 return -EINVAL; 119 } 120 121 static int 122 v3d_open(struct drm_device *dev, struct drm_file *file) 123 { 124 struct v3d_dev *v3d = to_v3d_dev(dev); 125 struct v3d_file_priv *v3d_priv; 126 struct drm_sched_rq *rq; 127 int i; 128 129 v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL); 130 if (!v3d_priv) 131 return -ENOMEM; 132 133 v3d_priv->v3d = v3d; 134 135 for (i = 0; i < V3D_MAX_QUEUES; i++) { 136 rq = &v3d->queue[i].sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; 137 drm_sched_entity_init(&v3d_priv->sched_entity[i], &rq, 1, NULL); 138 } 139 140 file->driver_priv = v3d_priv; 141 142 return 0; 143 } 144 145 static void 146 v3d_postclose(struct drm_device *dev, struct drm_file *file) 147 { 148 struct v3d_file_priv *v3d_priv = file->driver_priv; 149 enum v3d_queue q; 150 151 for (q = 0; q < V3D_MAX_QUEUES; q++) { 152 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]); 153 } 154 155 kfree(v3d_priv); 156 } 157 158 static const struct file_operations v3d_drm_fops = { 159 .owner = THIS_MODULE, 160 .open = drm_open, 161 .release = drm_release, 162 .unlocked_ioctl = drm_ioctl, 163 .mmap = v3d_mmap, 164 .poll = drm_poll, 165 .read = drm_read, 166 .compat_ioctl = drm_compat_ioctl, 167 .llseek = noop_llseek, 168 }; 169 170 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP 171 * protection between clients. Note that render nodes would be be 172 * able to submit CLs that could access BOs from clients authenticated 173 * with the master node. 174 */ 175 static const struct drm_ioctl_desc v3d_drm_ioctls[] = { 176 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 177 DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW), 178 DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW), 179 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW), 180 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW), 181 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW), 182 }; 183 184 static const struct vm_operations_struct v3d_vm_ops = { 185 .fault = v3d_gem_fault, 186 .open = drm_gem_vm_open, 187 .close = drm_gem_vm_close, 188 }; 189 190 static struct drm_driver v3d_drm_driver = { 191 .driver_features = (DRIVER_GEM | 192 DRIVER_RENDER | 193 DRIVER_PRIME | 194 DRIVER_SYNCOBJ), 195 196 .open = v3d_open, 197 .postclose = v3d_postclose, 198 199 #if defined(CONFIG_DEBUG_FS) 200 .debugfs_init = v3d_debugfs_init, 201 #endif 202 203 .gem_free_object_unlocked = v3d_free_object, 204 .gem_vm_ops = &v3d_vm_ops, 205 206 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 207 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 208 .gem_prime_import = drm_gem_prime_import, 209 .gem_prime_export = drm_gem_prime_export, 210 .gem_prime_res_obj = v3d_prime_res_obj, 211 .gem_prime_get_sg_table = v3d_prime_get_sg_table, 212 .gem_prime_import_sg_table = v3d_prime_import_sg_table, 213 .gem_prime_mmap = v3d_prime_mmap, 214 215 .ioctls = v3d_drm_ioctls, 216 .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls), 217 .fops = &v3d_drm_fops, 218 219 .name = DRIVER_NAME, 220 .desc = DRIVER_DESC, 221 .date = DRIVER_DATE, 222 .major = DRIVER_MAJOR, 223 .minor = DRIVER_MINOR, 224 .patchlevel = DRIVER_PATCHLEVEL, 225 }; 226 227 static const struct of_device_id v3d_of_match[] = { 228 { .compatible = "brcm,7268-v3d" }, 229 { .compatible = "brcm,7278-v3d" }, 230 {}, 231 }; 232 MODULE_DEVICE_TABLE(of, v3d_of_match); 233 234 static int 235 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name) 236 { 237 struct resource *res = 238 platform_get_resource_byname(v3d->pdev, IORESOURCE_MEM, name); 239 240 *regs = devm_ioremap_resource(v3d->dev, res); 241 return PTR_ERR_OR_ZERO(*regs); 242 } 243 244 static int v3d_platform_drm_probe(struct platform_device *pdev) 245 { 246 struct device *dev = &pdev->dev; 247 struct drm_device *drm; 248 struct v3d_dev *v3d; 249 int ret; 250 u32 ident1; 251 252 dev->coherent_dma_mask = DMA_BIT_MASK(36); 253 254 v3d = kzalloc(sizeof(*v3d), GFP_KERNEL); 255 if (!v3d) 256 return -ENOMEM; 257 v3d->dev = dev; 258 v3d->pdev = pdev; 259 drm = &v3d->drm; 260 261 ret = map_regs(v3d, &v3d->bridge_regs, "bridge"); 262 if (ret) 263 goto dev_free; 264 265 ret = map_regs(v3d, &v3d->hub_regs, "hub"); 266 if (ret) 267 goto dev_free; 268 269 ret = map_regs(v3d, &v3d->core_regs[0], "core0"); 270 if (ret) 271 goto dev_free; 272 273 ident1 = V3D_READ(V3D_HUB_IDENT1); 274 v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 + 275 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV)); 276 v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); 277 WARN_ON(v3d->cores > 1); /* multicore not yet implemented */ 278 279 if (v3d->ver < 41) { 280 ret = map_regs(v3d, &v3d->gca_regs, "gca"); 281 if (ret) 282 goto dev_free; 283 } 284 285 v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr, 286 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 287 if (!v3d->mmu_scratch) { 288 dev_err(dev, "Failed to allocate MMU scratch page\n"); 289 ret = -ENOMEM; 290 goto dev_free; 291 } 292 293 pm_runtime_use_autosuspend(dev); 294 pm_runtime_set_autosuspend_delay(dev, 50); 295 pm_runtime_enable(dev); 296 297 ret = drm_dev_init(&v3d->drm, &v3d_drm_driver, dev); 298 if (ret) 299 goto dma_free; 300 301 platform_set_drvdata(pdev, drm); 302 drm->dev_private = v3d; 303 304 ret = v3d_gem_init(drm); 305 if (ret) 306 goto dev_destroy; 307 308 v3d_irq_init(v3d); 309 310 ret = drm_dev_register(drm, 0); 311 if (ret) 312 goto gem_destroy; 313 314 return 0; 315 316 gem_destroy: 317 v3d_gem_destroy(drm); 318 dev_destroy: 319 drm_dev_put(drm); 320 dma_free: 321 dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 322 dev_free: 323 kfree(v3d); 324 return ret; 325 } 326 327 static int v3d_platform_drm_remove(struct platform_device *pdev) 328 { 329 struct drm_device *drm = platform_get_drvdata(pdev); 330 struct v3d_dev *v3d = to_v3d_dev(drm); 331 332 drm_dev_unregister(drm); 333 334 v3d_gem_destroy(drm); 335 336 drm_dev_put(drm); 337 338 dma_free_wc(v3d->dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 339 340 return 0; 341 } 342 343 static struct platform_driver v3d_platform_driver = { 344 .probe = v3d_platform_drm_probe, 345 .remove = v3d_platform_drm_remove, 346 .driver = { 347 .name = "v3d", 348 .of_match_table = v3d_of_match, 349 }, 350 }; 351 352 static int __init v3d_drm_register(void) 353 { 354 return platform_driver_register(&v3d_platform_driver); 355 } 356 357 static void __exit v3d_drm_unregister(void) 358 { 359 platform_driver_unregister(&v3d_platform_driver); 360 } 361 362 module_init(v3d_drm_register); 363 module_exit(v3d_drm_unregister); 364 365 MODULE_ALIAS("platform:v3d-drm"); 366 MODULE_DESCRIPTION("Broadcom V3D DRM Driver"); 367 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 368 MODULE_LICENSE("GPL v2"); 369