1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 /** 5 * DOC: Broadcom V3D Graphics Driver 6 * 7 * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs. 8 * For V3D 2.x support, see the VC4 driver. 9 * 10 * Currently only single-core rendering using the binner and renderer, 11 * along with TFU (texture formatting unit) rendering is supported. 12 * V3D 4.x's CSD (compute shader dispatch) is not yet supported. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/device.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/of_platform.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/reset.h> 23 #include <drm/drm_fb_cma_helper.h> 24 #include <drm/drm_fb_helper.h> 25 26 #include "uapi/drm/v3d_drm.h" 27 #include "v3d_drv.h" 28 #include "v3d_regs.h" 29 30 #define DRIVER_NAME "v3d" 31 #define DRIVER_DESC "Broadcom V3D graphics" 32 #define DRIVER_DATE "20180419" 33 #define DRIVER_MAJOR 1 34 #define DRIVER_MINOR 0 35 #define DRIVER_PATCHLEVEL 0 36 37 #ifdef CONFIG_PM 38 static int v3d_runtime_suspend(struct device *dev) 39 { 40 struct drm_device *drm = dev_get_drvdata(dev); 41 struct v3d_dev *v3d = to_v3d_dev(drm); 42 43 v3d_irq_disable(v3d); 44 45 clk_disable_unprepare(v3d->clk); 46 47 return 0; 48 } 49 50 static int v3d_runtime_resume(struct device *dev) 51 { 52 struct drm_device *drm = dev_get_drvdata(dev); 53 struct v3d_dev *v3d = to_v3d_dev(drm); 54 int ret; 55 56 ret = clk_prepare_enable(v3d->clk); 57 if (ret != 0) 58 return ret; 59 60 /* XXX: VPM base */ 61 62 v3d_mmu_set_page_table(v3d); 63 v3d_irq_enable(v3d); 64 65 return 0; 66 } 67 #endif 68 69 static const struct dev_pm_ops v3d_v3d_pm_ops = { 70 SET_RUNTIME_PM_OPS(v3d_runtime_suspend, v3d_runtime_resume, NULL) 71 }; 72 73 static int v3d_get_param_ioctl(struct drm_device *dev, void *data, 74 struct drm_file *file_priv) 75 { 76 struct v3d_dev *v3d = to_v3d_dev(dev); 77 struct drm_v3d_get_param *args = data; 78 int ret; 79 static const u32 reg_map[] = { 80 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG, 81 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1, 82 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2, 83 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3, 84 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0, 85 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1, 86 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2, 87 }; 88 89 if (args->pad != 0) 90 return -EINVAL; 91 92 /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need 93 * to explicitly allow it in the "the register in our 94 * parameter map" check. 95 */ 96 if (args->param < ARRAY_SIZE(reg_map) && 97 (reg_map[args->param] || 98 args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) { 99 u32 offset = reg_map[args->param]; 100 101 if (args->value != 0) 102 return -EINVAL; 103 104 ret = pm_runtime_get_sync(v3d->dev); 105 if (ret < 0) 106 return ret; 107 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 && 108 args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) { 109 args->value = V3D_CORE_READ(0, offset); 110 } else { 111 args->value = V3D_READ(offset); 112 } 113 pm_runtime_mark_last_busy(v3d->dev); 114 pm_runtime_put_autosuspend(v3d->dev); 115 return 0; 116 } 117 118 119 switch (args->param) { 120 case DRM_V3D_PARAM_SUPPORTS_TFU: 121 args->value = 1; 122 return 0; 123 default: 124 DRM_DEBUG("Unknown parameter %d\n", args->param); 125 return -EINVAL; 126 } 127 } 128 129 static int 130 v3d_open(struct drm_device *dev, struct drm_file *file) 131 { 132 struct v3d_dev *v3d = to_v3d_dev(dev); 133 struct v3d_file_priv *v3d_priv; 134 struct drm_sched_rq *rq; 135 int i; 136 137 v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL); 138 if (!v3d_priv) 139 return -ENOMEM; 140 141 v3d_priv->v3d = v3d; 142 143 for (i = 0; i < V3D_MAX_QUEUES; i++) { 144 rq = &v3d->queue[i].sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL]; 145 drm_sched_entity_init(&v3d_priv->sched_entity[i], &rq, 1, NULL); 146 } 147 148 file->driver_priv = v3d_priv; 149 150 return 0; 151 } 152 153 static void 154 v3d_postclose(struct drm_device *dev, struct drm_file *file) 155 { 156 struct v3d_file_priv *v3d_priv = file->driver_priv; 157 enum v3d_queue q; 158 159 for (q = 0; q < V3D_MAX_QUEUES; q++) { 160 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]); 161 } 162 163 kfree(v3d_priv); 164 } 165 166 DEFINE_DRM_GEM_SHMEM_FOPS(v3d_drm_fops); 167 168 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP 169 * protection between clients. Note that render nodes would be be 170 * able to submit CLs that could access BOs from clients authenticated 171 * with the master node. The TFU doesn't use the GMP, so it would 172 * need to stay DRM_AUTH until we do buffer size/offset validation. 173 */ 174 static const struct drm_ioctl_desc v3d_drm_ioctls[] = { 175 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 176 DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW), 177 DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW), 178 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW), 179 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW), 180 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW), 181 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 182 }; 183 184 static struct drm_driver v3d_drm_driver = { 185 .driver_features = (DRIVER_GEM | 186 DRIVER_RENDER | 187 DRIVER_PRIME | 188 DRIVER_SYNCOBJ), 189 190 .open = v3d_open, 191 .postclose = v3d_postclose, 192 193 #if defined(CONFIG_DEBUG_FS) 194 .debugfs_init = v3d_debugfs_init, 195 #endif 196 197 .gem_create_object = v3d_create_object, 198 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 199 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 200 .gem_prime_import_sg_table = v3d_prime_import_sg_table, 201 .gem_prime_mmap = drm_gem_prime_mmap, 202 203 .ioctls = v3d_drm_ioctls, 204 .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls), 205 .fops = &v3d_drm_fops, 206 207 .name = DRIVER_NAME, 208 .desc = DRIVER_DESC, 209 .date = DRIVER_DATE, 210 .major = DRIVER_MAJOR, 211 .minor = DRIVER_MINOR, 212 .patchlevel = DRIVER_PATCHLEVEL, 213 }; 214 215 static const struct of_device_id v3d_of_match[] = { 216 { .compatible = "brcm,7268-v3d" }, 217 { .compatible = "brcm,7278-v3d" }, 218 {}, 219 }; 220 MODULE_DEVICE_TABLE(of, v3d_of_match); 221 222 static int 223 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name) 224 { 225 struct resource *res = 226 platform_get_resource_byname(v3d->pdev, IORESOURCE_MEM, name); 227 228 *regs = devm_ioremap_resource(v3d->dev, res); 229 return PTR_ERR_OR_ZERO(*regs); 230 } 231 232 static int v3d_platform_drm_probe(struct platform_device *pdev) 233 { 234 struct device *dev = &pdev->dev; 235 struct drm_device *drm; 236 struct v3d_dev *v3d; 237 int ret; 238 u32 ident1; 239 240 dev->coherent_dma_mask = DMA_BIT_MASK(36); 241 242 v3d = kzalloc(sizeof(*v3d), GFP_KERNEL); 243 if (!v3d) 244 return -ENOMEM; 245 v3d->dev = dev; 246 v3d->pdev = pdev; 247 drm = &v3d->drm; 248 249 ret = map_regs(v3d, &v3d->hub_regs, "hub"); 250 if (ret) 251 goto dev_free; 252 253 ret = map_regs(v3d, &v3d->core_regs[0], "core0"); 254 if (ret) 255 goto dev_free; 256 257 ident1 = V3D_READ(V3D_HUB_IDENT1); 258 v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 + 259 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV)); 260 v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); 261 WARN_ON(v3d->cores > 1); /* multicore not yet implemented */ 262 263 v3d->reset = devm_reset_control_get_exclusive(dev, NULL); 264 if (IS_ERR(v3d->reset)) { 265 ret = PTR_ERR(v3d->reset); 266 267 if (ret == -EPROBE_DEFER) 268 goto dev_free; 269 270 v3d->reset = NULL; 271 ret = map_regs(v3d, &v3d->bridge_regs, "bridge"); 272 if (ret) { 273 dev_err(dev, 274 "Failed to get reset control or bridge regs\n"); 275 goto dev_free; 276 } 277 } 278 279 if (v3d->ver < 41) { 280 ret = map_regs(v3d, &v3d->gca_regs, "gca"); 281 if (ret) 282 goto dev_free; 283 } 284 285 v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr, 286 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 287 if (!v3d->mmu_scratch) { 288 dev_err(dev, "Failed to allocate MMU scratch page\n"); 289 ret = -ENOMEM; 290 goto dev_free; 291 } 292 293 pm_runtime_use_autosuspend(dev); 294 pm_runtime_set_autosuspend_delay(dev, 50); 295 pm_runtime_enable(dev); 296 297 ret = drm_dev_init(&v3d->drm, &v3d_drm_driver, dev); 298 if (ret) 299 goto dma_free; 300 301 platform_set_drvdata(pdev, drm); 302 drm->dev_private = v3d; 303 304 ret = v3d_gem_init(drm); 305 if (ret) 306 goto dev_destroy; 307 308 ret = v3d_irq_init(v3d); 309 if (ret) 310 goto gem_destroy; 311 312 ret = drm_dev_register(drm, 0); 313 if (ret) 314 goto irq_disable; 315 316 return 0; 317 318 irq_disable: 319 v3d_irq_disable(v3d); 320 gem_destroy: 321 v3d_gem_destroy(drm); 322 dev_destroy: 323 drm_dev_put(drm); 324 dma_free: 325 dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 326 dev_free: 327 kfree(v3d); 328 return ret; 329 } 330 331 static int v3d_platform_drm_remove(struct platform_device *pdev) 332 { 333 struct drm_device *drm = platform_get_drvdata(pdev); 334 struct v3d_dev *v3d = to_v3d_dev(drm); 335 336 drm_dev_unregister(drm); 337 338 v3d_gem_destroy(drm); 339 340 drm_dev_put(drm); 341 342 dma_free_wc(v3d->dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 343 344 return 0; 345 } 346 347 static struct platform_driver v3d_platform_driver = { 348 .probe = v3d_platform_drm_probe, 349 .remove = v3d_platform_drm_remove, 350 .driver = { 351 .name = "v3d", 352 .of_match_table = v3d_of_match, 353 }, 354 }; 355 356 static int __init v3d_drm_register(void) 357 { 358 return platform_driver_register(&v3d_platform_driver); 359 } 360 361 static void __exit v3d_drm_unregister(void) 362 { 363 platform_driver_unregister(&v3d_platform_driver); 364 } 365 366 module_init(v3d_drm_register); 367 module_exit(v3d_drm_unregister); 368 369 MODULE_ALIAS("platform:v3d-drm"); 370 MODULE_DESCRIPTION("Broadcom V3D DRM Driver"); 371 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 372 MODULE_LICENSE("GPL v2"); 373