1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 /** 5 * DOC: Broadcom V3D Graphics Driver 6 * 7 * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs. 8 * For V3D 2.x support, see the VC4 driver. 9 * 10 * The V3D GPU includes a tiled render (composed of a bin and render 11 * pipelines), the TFU (texture formatting unit), and the CSD (compute 12 * shader dispatch). 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/device.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/reset.h> 23 24 #include <drm/drm_drv.h> 25 #include <drm/drm_fb_cma_helper.h> 26 #include <drm/drm_fb_helper.h> 27 #include <drm/drm_managed.h> 28 #include <uapi/drm/v3d_drm.h> 29 30 #include "v3d_drv.h" 31 #include "v3d_regs.h" 32 33 #define DRIVER_NAME "v3d" 34 #define DRIVER_DESC "Broadcom V3D graphics" 35 #define DRIVER_DATE "20180419" 36 #define DRIVER_MAJOR 1 37 #define DRIVER_MINOR 0 38 #define DRIVER_PATCHLEVEL 0 39 40 static int v3d_get_param_ioctl(struct drm_device *dev, void *data, 41 struct drm_file *file_priv) 42 { 43 struct v3d_dev *v3d = to_v3d_dev(dev); 44 struct drm_v3d_get_param *args = data; 45 static const u32 reg_map[] = { 46 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG, 47 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1, 48 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2, 49 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3, 50 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0, 51 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1, 52 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2, 53 }; 54 55 if (args->pad != 0) 56 return -EINVAL; 57 58 /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need 59 * to explicitly allow it in the "the register in our 60 * parameter map" check. 61 */ 62 if (args->param < ARRAY_SIZE(reg_map) && 63 (reg_map[args->param] || 64 args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) { 65 u32 offset = reg_map[args->param]; 66 67 if (args->value != 0) 68 return -EINVAL; 69 70 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 && 71 args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) { 72 args->value = V3D_CORE_READ(0, offset); 73 } else { 74 args->value = V3D_READ(offset); 75 } 76 return 0; 77 } 78 79 switch (args->param) { 80 case DRM_V3D_PARAM_SUPPORTS_TFU: 81 args->value = 1; 82 return 0; 83 case DRM_V3D_PARAM_SUPPORTS_CSD: 84 args->value = v3d_has_csd(v3d); 85 return 0; 86 case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH: 87 args->value = 1; 88 return 0; 89 case DRM_V3D_PARAM_SUPPORTS_PERFMON: 90 args->value = (v3d->ver >= 40); 91 return 0; 92 case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT: 93 args->value = 1; 94 return 0; 95 default: 96 DRM_DEBUG("Unknown parameter %d\n", args->param); 97 return -EINVAL; 98 } 99 } 100 101 static int 102 v3d_open(struct drm_device *dev, struct drm_file *file) 103 { 104 struct v3d_dev *v3d = to_v3d_dev(dev); 105 struct v3d_file_priv *v3d_priv; 106 struct drm_gpu_scheduler *sched; 107 int i; 108 109 v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL); 110 if (!v3d_priv) 111 return -ENOMEM; 112 113 v3d_priv->v3d = v3d; 114 115 for (i = 0; i < V3D_MAX_QUEUES; i++) { 116 sched = &v3d->queue[i].sched; 117 drm_sched_entity_init(&v3d_priv->sched_entity[i], 118 DRM_SCHED_PRIORITY_NORMAL, &sched, 119 1, NULL); 120 } 121 122 v3d_perfmon_open_file(v3d_priv); 123 file->driver_priv = v3d_priv; 124 125 return 0; 126 } 127 128 static void 129 v3d_postclose(struct drm_device *dev, struct drm_file *file) 130 { 131 struct v3d_file_priv *v3d_priv = file->driver_priv; 132 enum v3d_queue q; 133 134 for (q = 0; q < V3D_MAX_QUEUES; q++) 135 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]); 136 137 v3d_perfmon_close_file(v3d_priv); 138 kfree(v3d_priv); 139 } 140 141 DEFINE_DRM_GEM_FOPS(v3d_drm_fops); 142 143 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP 144 * protection between clients. Note that render nodes would be 145 * able to submit CLs that could access BOs from clients authenticated 146 * with the master node. The TFU doesn't use the GMP, so it would 147 * need to stay DRM_AUTH until we do buffer size/offset validation. 148 */ 149 static const struct drm_ioctl_desc v3d_drm_ioctls[] = { 150 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 151 DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW), 152 DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW), 153 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW), 154 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW), 155 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW), 156 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 157 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 158 DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW), 159 DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW), 160 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW), 161 }; 162 163 static const struct drm_driver v3d_drm_driver = { 164 .driver_features = (DRIVER_GEM | 165 DRIVER_RENDER | 166 DRIVER_SYNCOBJ), 167 168 .open = v3d_open, 169 .postclose = v3d_postclose, 170 171 #if defined(CONFIG_DEBUG_FS) 172 .debugfs_init = v3d_debugfs_init, 173 #endif 174 175 .gem_create_object = v3d_create_object, 176 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 177 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 178 .gem_prime_import_sg_table = v3d_prime_import_sg_table, 179 .gem_prime_mmap = drm_gem_prime_mmap, 180 181 .ioctls = v3d_drm_ioctls, 182 .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls), 183 .fops = &v3d_drm_fops, 184 185 .name = DRIVER_NAME, 186 .desc = DRIVER_DESC, 187 .date = DRIVER_DATE, 188 .major = DRIVER_MAJOR, 189 .minor = DRIVER_MINOR, 190 .patchlevel = DRIVER_PATCHLEVEL, 191 }; 192 193 static const struct of_device_id v3d_of_match[] = { 194 { .compatible = "brcm,2711-v3d" }, 195 { .compatible = "brcm,7268-v3d" }, 196 { .compatible = "brcm,7278-v3d" }, 197 {}, 198 }; 199 MODULE_DEVICE_TABLE(of, v3d_of_match); 200 201 static int 202 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name) 203 { 204 *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name); 205 return PTR_ERR_OR_ZERO(*regs); 206 } 207 208 static int v3d_platform_drm_probe(struct platform_device *pdev) 209 { 210 struct device *dev = &pdev->dev; 211 struct drm_device *drm; 212 struct v3d_dev *v3d; 213 int ret; 214 u32 mmu_debug; 215 u32 ident1; 216 u64 mask; 217 218 v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm); 219 if (IS_ERR(v3d)) 220 return PTR_ERR(v3d); 221 222 drm = &v3d->drm; 223 224 platform_set_drvdata(pdev, drm); 225 226 ret = map_regs(v3d, &v3d->hub_regs, "hub"); 227 if (ret) 228 return ret; 229 230 ret = map_regs(v3d, &v3d->core_regs[0], "core0"); 231 if (ret) 232 return ret; 233 234 mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO); 235 mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)); 236 ret = dma_set_mask_and_coherent(dev, mask); 237 if (ret) 238 return ret; 239 240 v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH); 241 242 ident1 = V3D_READ(V3D_HUB_IDENT1); 243 v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 + 244 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV)); 245 v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); 246 WARN_ON(v3d->cores > 1); /* multicore not yet implemented */ 247 248 v3d->reset = devm_reset_control_get_exclusive(dev, NULL); 249 if (IS_ERR(v3d->reset)) { 250 ret = PTR_ERR(v3d->reset); 251 252 if (ret == -EPROBE_DEFER) 253 return ret; 254 255 v3d->reset = NULL; 256 ret = map_regs(v3d, &v3d->bridge_regs, "bridge"); 257 if (ret) { 258 dev_err(dev, 259 "Failed to get reset control or bridge regs\n"); 260 return ret; 261 } 262 } 263 264 if (v3d->ver < 41) { 265 ret = map_regs(v3d, &v3d->gca_regs, "gca"); 266 if (ret) 267 return ret; 268 } 269 270 v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr, 271 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 272 if (!v3d->mmu_scratch) { 273 dev_err(dev, "Failed to allocate MMU scratch page\n"); 274 return -ENOMEM; 275 } 276 277 ret = v3d_gem_init(drm); 278 if (ret) 279 goto dma_free; 280 281 ret = v3d_irq_init(v3d); 282 if (ret) 283 goto gem_destroy; 284 285 ret = drm_dev_register(drm, 0); 286 if (ret) 287 goto irq_disable; 288 289 return 0; 290 291 irq_disable: 292 v3d_irq_disable(v3d); 293 gem_destroy: 294 v3d_gem_destroy(drm); 295 dma_free: 296 dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 297 return ret; 298 } 299 300 static int v3d_platform_drm_remove(struct platform_device *pdev) 301 { 302 struct drm_device *drm = platform_get_drvdata(pdev); 303 struct v3d_dev *v3d = to_v3d_dev(drm); 304 305 drm_dev_unregister(drm); 306 307 v3d_gem_destroy(drm); 308 309 dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch, 310 v3d->mmu_scratch_paddr); 311 312 return 0; 313 } 314 315 static struct platform_driver v3d_platform_driver = { 316 .probe = v3d_platform_drm_probe, 317 .remove = v3d_platform_drm_remove, 318 .driver = { 319 .name = "v3d", 320 .of_match_table = v3d_of_match, 321 }, 322 }; 323 324 module_platform_driver(v3d_platform_driver); 325 326 MODULE_ALIAS("platform:v3d-drm"); 327 MODULE_DESCRIPTION("Broadcom V3D DRM Driver"); 328 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 329 MODULE_LICENSE("GPL v2"); 330