1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (C) 2014-2018 Broadcom */ 3 4 /** 5 * DOC: Broadcom V3D Graphics Driver 6 * 7 * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs. 8 * For V3D 2.x support, see the VC4 driver. 9 * 10 * The V3D GPU includes a tiled render (composed of a bin and render 11 * pipelines), the TFU (texture formatting unit), and the CSD (compute 12 * shader dispatch). 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/device.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/reset.h> 23 24 #include <drm/drm_drv.h> 25 #include <drm/drm_fb_helper.h> 26 #include <drm/drm_managed.h> 27 #include <uapi/drm/v3d_drm.h> 28 29 #include "v3d_drv.h" 30 #include "v3d_regs.h" 31 32 #define DRIVER_NAME "v3d" 33 #define DRIVER_DESC "Broadcom V3D graphics" 34 #define DRIVER_DATE "20180419" 35 #define DRIVER_MAJOR 1 36 #define DRIVER_MINOR 0 37 #define DRIVER_PATCHLEVEL 0 38 39 static int v3d_get_param_ioctl(struct drm_device *dev, void *data, 40 struct drm_file *file_priv) 41 { 42 struct v3d_dev *v3d = to_v3d_dev(dev); 43 struct drm_v3d_get_param *args = data; 44 static const u32 reg_map[] = { 45 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG, 46 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1, 47 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2, 48 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3, 49 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0, 50 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1, 51 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2, 52 }; 53 54 if (args->pad != 0) 55 return -EINVAL; 56 57 /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need 58 * to explicitly allow it in the "the register in our 59 * parameter map" check. 60 */ 61 if (args->param < ARRAY_SIZE(reg_map) && 62 (reg_map[args->param] || 63 args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) { 64 u32 offset = reg_map[args->param]; 65 66 if (args->value != 0) 67 return -EINVAL; 68 69 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 && 70 args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) { 71 args->value = V3D_CORE_READ(0, offset); 72 } else { 73 args->value = V3D_READ(offset); 74 } 75 return 0; 76 } 77 78 switch (args->param) { 79 case DRM_V3D_PARAM_SUPPORTS_TFU: 80 args->value = 1; 81 return 0; 82 case DRM_V3D_PARAM_SUPPORTS_CSD: 83 args->value = v3d_has_csd(v3d); 84 return 0; 85 case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH: 86 args->value = 1; 87 return 0; 88 case DRM_V3D_PARAM_SUPPORTS_PERFMON: 89 args->value = (v3d->ver >= 40); 90 return 0; 91 case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT: 92 args->value = 1; 93 return 0; 94 default: 95 DRM_DEBUG("Unknown parameter %d\n", args->param); 96 return -EINVAL; 97 } 98 } 99 100 static int 101 v3d_open(struct drm_device *dev, struct drm_file *file) 102 { 103 struct v3d_dev *v3d = to_v3d_dev(dev); 104 struct v3d_file_priv *v3d_priv; 105 struct drm_gpu_scheduler *sched; 106 int i; 107 108 v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL); 109 if (!v3d_priv) 110 return -ENOMEM; 111 112 v3d_priv->v3d = v3d; 113 114 for (i = 0; i < V3D_MAX_QUEUES; i++) { 115 sched = &v3d->queue[i].sched; 116 drm_sched_entity_init(&v3d_priv->sched_entity[i], 117 DRM_SCHED_PRIORITY_NORMAL, &sched, 118 1, NULL); 119 } 120 121 v3d_perfmon_open_file(v3d_priv); 122 file->driver_priv = v3d_priv; 123 124 return 0; 125 } 126 127 static void 128 v3d_postclose(struct drm_device *dev, struct drm_file *file) 129 { 130 struct v3d_file_priv *v3d_priv = file->driver_priv; 131 enum v3d_queue q; 132 133 for (q = 0; q < V3D_MAX_QUEUES; q++) 134 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]); 135 136 v3d_perfmon_close_file(v3d_priv); 137 kfree(v3d_priv); 138 } 139 140 DEFINE_DRM_GEM_FOPS(v3d_drm_fops); 141 142 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP 143 * protection between clients. Note that render nodes would be 144 * able to submit CLs that could access BOs from clients authenticated 145 * with the master node. The TFU doesn't use the GMP, so it would 146 * need to stay DRM_AUTH until we do buffer size/offset validation. 147 */ 148 static const struct drm_ioctl_desc v3d_drm_ioctls[] = { 149 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 150 DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW), 151 DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW), 152 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW), 153 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW), 154 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW), 155 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 156 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH), 157 DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW), 158 DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW), 159 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW), 160 }; 161 162 static const struct drm_driver v3d_drm_driver = { 163 .driver_features = (DRIVER_GEM | 164 DRIVER_RENDER | 165 DRIVER_SYNCOBJ), 166 167 .open = v3d_open, 168 .postclose = v3d_postclose, 169 170 #if defined(CONFIG_DEBUG_FS) 171 .debugfs_init = v3d_debugfs_init, 172 #endif 173 174 .gem_create_object = v3d_create_object, 175 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 176 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 177 .gem_prime_import_sg_table = v3d_prime_import_sg_table, 178 .gem_prime_mmap = drm_gem_prime_mmap, 179 180 .ioctls = v3d_drm_ioctls, 181 .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls), 182 .fops = &v3d_drm_fops, 183 184 .name = DRIVER_NAME, 185 .desc = DRIVER_DESC, 186 .date = DRIVER_DATE, 187 .major = DRIVER_MAJOR, 188 .minor = DRIVER_MINOR, 189 .patchlevel = DRIVER_PATCHLEVEL, 190 }; 191 192 static const struct of_device_id v3d_of_match[] = { 193 { .compatible = "brcm,2711-v3d" }, 194 { .compatible = "brcm,7268-v3d" }, 195 { .compatible = "brcm,7278-v3d" }, 196 {}, 197 }; 198 MODULE_DEVICE_TABLE(of, v3d_of_match); 199 200 static int 201 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name) 202 { 203 *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name); 204 return PTR_ERR_OR_ZERO(*regs); 205 } 206 207 static int v3d_platform_drm_probe(struct platform_device *pdev) 208 { 209 struct device *dev = &pdev->dev; 210 struct drm_device *drm; 211 struct v3d_dev *v3d; 212 int ret; 213 u32 mmu_debug; 214 u32 ident1; 215 u64 mask; 216 217 v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm); 218 if (IS_ERR(v3d)) 219 return PTR_ERR(v3d); 220 221 drm = &v3d->drm; 222 223 platform_set_drvdata(pdev, drm); 224 225 ret = map_regs(v3d, &v3d->hub_regs, "hub"); 226 if (ret) 227 return ret; 228 229 ret = map_regs(v3d, &v3d->core_regs[0], "core0"); 230 if (ret) 231 return ret; 232 233 mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO); 234 mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH)); 235 ret = dma_set_mask_and_coherent(dev, mask); 236 if (ret) 237 return ret; 238 239 v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH); 240 241 ident1 = V3D_READ(V3D_HUB_IDENT1); 242 v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 + 243 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV)); 244 v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES); 245 WARN_ON(v3d->cores > 1); /* multicore not yet implemented */ 246 247 v3d->reset = devm_reset_control_get_exclusive(dev, NULL); 248 if (IS_ERR(v3d->reset)) { 249 ret = PTR_ERR(v3d->reset); 250 251 if (ret == -EPROBE_DEFER) 252 return ret; 253 254 v3d->reset = NULL; 255 ret = map_regs(v3d, &v3d->bridge_regs, "bridge"); 256 if (ret) { 257 dev_err(dev, 258 "Failed to get reset control or bridge regs\n"); 259 return ret; 260 } 261 } 262 263 if (v3d->ver < 41) { 264 ret = map_regs(v3d, &v3d->gca_regs, "gca"); 265 if (ret) 266 return ret; 267 } 268 269 v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr, 270 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO); 271 if (!v3d->mmu_scratch) { 272 dev_err(dev, "Failed to allocate MMU scratch page\n"); 273 return -ENOMEM; 274 } 275 276 ret = v3d_gem_init(drm); 277 if (ret) 278 goto dma_free; 279 280 ret = v3d_irq_init(v3d); 281 if (ret) 282 goto gem_destroy; 283 284 ret = drm_dev_register(drm, 0); 285 if (ret) 286 goto irq_disable; 287 288 return 0; 289 290 irq_disable: 291 v3d_irq_disable(v3d); 292 gem_destroy: 293 v3d_gem_destroy(drm); 294 dma_free: 295 dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr); 296 return ret; 297 } 298 299 static int v3d_platform_drm_remove(struct platform_device *pdev) 300 { 301 struct drm_device *drm = platform_get_drvdata(pdev); 302 struct v3d_dev *v3d = to_v3d_dev(drm); 303 304 drm_dev_unregister(drm); 305 306 v3d_gem_destroy(drm); 307 308 dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch, 309 v3d->mmu_scratch_paddr); 310 311 return 0; 312 } 313 314 static struct platform_driver v3d_platform_driver = { 315 .probe = v3d_platform_drm_probe, 316 .remove = v3d_platform_drm_remove, 317 .driver = { 318 .name = "v3d", 319 .of_match_table = v3d_of_match, 320 }, 321 }; 322 323 module_platform_driver(v3d_platform_driver); 324 325 MODULE_ALIAS("platform:v3d-drm"); 326 MODULE_DESCRIPTION("Broadcom V3D DRM Driver"); 327 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 328 MODULE_LICENSE("GPL v2"); 329