1ff76e82cSThomas Zimmermann /* SPDX-License-Identifier: GPL-2.0-only */ 2ff76e82cSThomas Zimmermann 3ff76e82cSThomas Zimmermann #ifndef UDL_PROTO_H 4ff76e82cSThomas Zimmermann #define UDL_PROTO_H 5ff76e82cSThomas Zimmermann 6*44f29ad9SThomas Zimmermann #include <linux/bits.h> 7*44f29ad9SThomas Zimmermann 8ed24ed48SThomas Zimmermann /* Color depth */ 9ed24ed48SThomas Zimmermann #define UDL_REG_COLORDEPTH 0x00 10ff76e82cSThomas Zimmermann #define UDL_COLORDEPTH_16BPP 0 11ed24ed48SThomas Zimmermann #define UDL_COLORDEPTH_24BPP 1 12ff76e82cSThomas Zimmermann 139869e40dSThomas Zimmermann /* Display-mode settings */ 149869e40dSThomas Zimmermann #define UDL_REG_XDISPLAYSTART 0x01 159869e40dSThomas Zimmermann #define UDL_REG_XDISPLAYEND 0x03 169869e40dSThomas Zimmermann #define UDL_REG_YDISPLAYSTART 0x05 179869e40dSThomas Zimmermann #define UDL_REG_YDISPLAYEND 0x07 189869e40dSThomas Zimmermann #define UDL_REG_XENDCOUNT 0x09 199869e40dSThomas Zimmermann #define UDL_REG_HSYNCSTART 0x0b 209869e40dSThomas Zimmermann #define UDL_REG_HSYNCEND 0x0d 219869e40dSThomas Zimmermann #define UDL_REG_HPIXELS 0x0f 229869e40dSThomas Zimmermann #define UDL_REG_YENDCOUNT 0x11 239869e40dSThomas Zimmermann #define UDL_REG_VSYNCSTART 0x13 249869e40dSThomas Zimmermann #define UDL_REG_VSYNCEND 0x15 259869e40dSThomas Zimmermann #define UDL_REG_VPIXELS 0x17 269869e40dSThomas Zimmermann #define UDL_REG_PIXELCLOCK5KHZ 0x1b 279869e40dSThomas Zimmermann 28ff76e82cSThomas Zimmermann /* On/Off for driving the DisplayLink framebuffer to the display */ 29ff76e82cSThomas Zimmermann #define UDL_REG_BLANKMODE 0x1f 30ff76e82cSThomas Zimmermann #define UDL_BLANKMODE_ON 0x00 /* hsync and vsync on, visible */ 31ff76e82cSThomas Zimmermann #define UDL_BLANKMODE_BLANKED 0x01 /* hsync and vsync on, blanked */ 32ff76e82cSThomas Zimmermann #define UDL_BLANKMODE_VSYNC_OFF 0x03 /* vsync off, blanked */ 33ff76e82cSThomas Zimmermann #define UDL_BLANKMODE_HSYNC_OFF 0x05 /* hsync off, blanked */ 34ff76e82cSThomas Zimmermann #define UDL_BLANKMODE_POWERDOWN 0x07 /* powered off; requires modeset */ 35ff76e82cSThomas Zimmermann 36*44f29ad9SThomas Zimmermann /* Framebuffer address */ 37*44f29ad9SThomas Zimmermann #define UDL_REG_BASE16BPP_ADDR2 0x20 38*44f29ad9SThomas Zimmermann #define UDL_REG_BASE16BPP_ADDR1 0x21 39*44f29ad9SThomas Zimmermann #define UDL_REG_BASE16BPP_ADDR0 0x22 40*44f29ad9SThomas Zimmermann #define UDL_REG_BASE8BPP_ADDR2 0x26 41*44f29ad9SThomas Zimmermann #define UDL_REG_BASE8BPP_ADDR1 0x27 42*44f29ad9SThomas Zimmermann #define UDL_REG_BASE8BPP_ADDR0 0x28 43*44f29ad9SThomas Zimmermann 44*44f29ad9SThomas Zimmermann #define UDL_BASE_ADDR0_MASK GENMASK(7, 0) 45*44f29ad9SThomas Zimmermann #define UDL_BASE_ADDR1_MASK GENMASK(15, 8) 46*44f29ad9SThomas Zimmermann #define UDL_BASE_ADDR2_MASK GENMASK(23, 16) 47*44f29ad9SThomas Zimmermann 48cb7b995dSThomas Zimmermann /* Lock/unlock video registers */ 49cb7b995dSThomas Zimmermann #define UDL_REG_VIDREG 0xff 50cb7b995dSThomas Zimmermann #define UDL_VIDREG_LOCK 0x00 51cb7b995dSThomas Zimmermann #define UDL_VIDREG_UNLOCK 0xff 52cb7b995dSThomas Zimmermann 53ff76e82cSThomas Zimmermann #endif 54