1ff76e82cSThomas Zimmermann /* SPDX-License-Identifier: GPL-2.0-only */ 2ff76e82cSThomas Zimmermann 3ff76e82cSThomas Zimmermann #ifndef UDL_PROTO_H 4ff76e82cSThomas Zimmermann #define UDL_PROTO_H 5ff76e82cSThomas Zimmermann 644f29ad9SThomas Zimmermann #include <linux/bits.h> 744f29ad9SThomas Zimmermann 8*1b8db07fSThomas Zimmermann #define UDL_MSG_BULK 0xaf 9*1b8db07fSThomas Zimmermann 10*1b8db07fSThomas Zimmermann /* Register access */ 11*1b8db07fSThomas Zimmermann #define UDL_CMD_WRITEREG 0x20 /* See register constants below */ 12*1b8db07fSThomas Zimmermann 13*1b8db07fSThomas Zimmermann /* Framebuffer access */ 14*1b8db07fSThomas Zimmermann #define UDL_CMD_WRITERAW8 0x60 /* 8 bit raw write command. */ 15*1b8db07fSThomas Zimmermann #define UDL_CMD_WRITERL8 0x61 /* 8 bit run length command. */ 16*1b8db07fSThomas Zimmermann #define UDL_CMD_WRITECOPY8 0x62 /* 8 bit copy command. */ 17*1b8db07fSThomas Zimmermann #define UDL_CMD_WRITERLX8 0x63 /* 8 bit extended run length command. */ 18*1b8db07fSThomas Zimmermann #define UDL_CMD_WRITERAW16 0x68 /* 16 bit raw write command. */ 19*1b8db07fSThomas Zimmermann #define UDL_CMD_WRITERL16 0x69 /* 16 bit run length command. */ 20*1b8db07fSThomas Zimmermann #define UDL_CMD_WRITECOPY16 0x6a /* 16 bit copy command. */ 21*1b8db07fSThomas Zimmermann #define UDL_CMD_WRITERLX16 0x6b /* 16 bit extended run length command. */ 22*1b8db07fSThomas Zimmermann 23ed24ed48SThomas Zimmermann /* Color depth */ 24ed24ed48SThomas Zimmermann #define UDL_REG_COLORDEPTH 0x00 25ff76e82cSThomas Zimmermann #define UDL_COLORDEPTH_16BPP 0 26ed24ed48SThomas Zimmermann #define UDL_COLORDEPTH_24BPP 1 27ff76e82cSThomas Zimmermann 289869e40dSThomas Zimmermann /* Display-mode settings */ 299869e40dSThomas Zimmermann #define UDL_REG_XDISPLAYSTART 0x01 309869e40dSThomas Zimmermann #define UDL_REG_XDISPLAYEND 0x03 319869e40dSThomas Zimmermann #define UDL_REG_YDISPLAYSTART 0x05 329869e40dSThomas Zimmermann #define UDL_REG_YDISPLAYEND 0x07 339869e40dSThomas Zimmermann #define UDL_REG_XENDCOUNT 0x09 349869e40dSThomas Zimmermann #define UDL_REG_HSYNCSTART 0x0b 359869e40dSThomas Zimmermann #define UDL_REG_HSYNCEND 0x0d 369869e40dSThomas Zimmermann #define UDL_REG_HPIXELS 0x0f 379869e40dSThomas Zimmermann #define UDL_REG_YENDCOUNT 0x11 389869e40dSThomas Zimmermann #define UDL_REG_VSYNCSTART 0x13 399869e40dSThomas Zimmermann #define UDL_REG_VSYNCEND 0x15 409869e40dSThomas Zimmermann #define UDL_REG_VPIXELS 0x17 419869e40dSThomas Zimmermann #define UDL_REG_PIXELCLOCK5KHZ 0x1b 429869e40dSThomas Zimmermann 43ff76e82cSThomas Zimmermann /* On/Off for driving the DisplayLink framebuffer to the display */ 44ff76e82cSThomas Zimmermann #define UDL_REG_BLANKMODE 0x1f 45ff76e82cSThomas Zimmermann #define UDL_BLANKMODE_ON 0x00 /* hsync and vsync on, visible */ 46ff76e82cSThomas Zimmermann #define UDL_BLANKMODE_BLANKED 0x01 /* hsync and vsync on, blanked */ 47ff76e82cSThomas Zimmermann #define UDL_BLANKMODE_VSYNC_OFF 0x03 /* vsync off, blanked */ 48ff76e82cSThomas Zimmermann #define UDL_BLANKMODE_HSYNC_OFF 0x05 /* hsync off, blanked */ 49ff76e82cSThomas Zimmermann #define UDL_BLANKMODE_POWERDOWN 0x07 /* powered off; requires modeset */ 50ff76e82cSThomas Zimmermann 5144f29ad9SThomas Zimmermann /* Framebuffer address */ 5244f29ad9SThomas Zimmermann #define UDL_REG_BASE16BPP_ADDR2 0x20 5344f29ad9SThomas Zimmermann #define UDL_REG_BASE16BPP_ADDR1 0x21 5444f29ad9SThomas Zimmermann #define UDL_REG_BASE16BPP_ADDR0 0x22 5544f29ad9SThomas Zimmermann #define UDL_REG_BASE8BPP_ADDR2 0x26 5644f29ad9SThomas Zimmermann #define UDL_REG_BASE8BPP_ADDR1 0x27 5744f29ad9SThomas Zimmermann #define UDL_REG_BASE8BPP_ADDR0 0x28 5844f29ad9SThomas Zimmermann 5944f29ad9SThomas Zimmermann #define UDL_BASE_ADDR0_MASK GENMASK(7, 0) 6044f29ad9SThomas Zimmermann #define UDL_BASE_ADDR1_MASK GENMASK(15, 8) 6144f29ad9SThomas Zimmermann #define UDL_BASE_ADDR2_MASK GENMASK(23, 16) 6244f29ad9SThomas Zimmermann 63cb7b995dSThomas Zimmermann /* Lock/unlock video registers */ 64cb7b995dSThomas Zimmermann #define UDL_REG_VIDREG 0xff 65cb7b995dSThomas Zimmermann #define UDL_VIDREG_LOCK 0x00 66cb7b995dSThomas Zimmermann #define UDL_VIDREG_UNLOCK 0xff 67cb7b995dSThomas Zimmermann 68ff76e82cSThomas Zimmermann #endif 69