1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Red Hat 4 * 5 * based in parts on udlfb.c: 6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it> 7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com> 8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com> 9 10 */ 11 12 #include <drm/drm_crtc_helper.h> 13 #include <drm/drm_modeset_helper_vtables.h> 14 #include <drm/drm_vblank.h> 15 16 #include "udl_drv.h" 17 18 /* 19 * All DisplayLink bulk operations start with 0xAF, followed by specific code 20 * All operations are written to buffers which then later get sent to device 21 */ 22 static char *udl_set_register(char *buf, u8 reg, u8 val) 23 { 24 *buf++ = 0xAF; 25 *buf++ = 0x20; 26 *buf++ = reg; 27 *buf++ = val; 28 return buf; 29 } 30 31 static char *udl_vidreg_lock(char *buf) 32 { 33 return udl_set_register(buf, 0xFF, 0x00); 34 } 35 36 static char *udl_vidreg_unlock(char *buf) 37 { 38 return udl_set_register(buf, 0xFF, 0xFF); 39 } 40 41 /* 42 * On/Off for driving the DisplayLink framebuffer to the display 43 * 0x00 H and V sync on 44 * 0x01 H and V sync off (screen blank but powered) 45 * 0x07 DPMS powerdown (requires modeset to come back) 46 */ 47 static char *udl_set_blank(char *buf, int dpms_mode) 48 { 49 u8 reg; 50 switch (dpms_mode) { 51 case DRM_MODE_DPMS_OFF: 52 reg = 0x07; 53 break; 54 case DRM_MODE_DPMS_STANDBY: 55 reg = 0x05; 56 break; 57 case DRM_MODE_DPMS_SUSPEND: 58 reg = 0x01; 59 break; 60 case DRM_MODE_DPMS_ON: 61 reg = 0x00; 62 break; 63 } 64 65 return udl_set_register(buf, 0x1f, reg); 66 } 67 68 static char *udl_set_color_depth(char *buf, u8 selection) 69 { 70 return udl_set_register(buf, 0x00, selection); 71 } 72 73 static char *udl_set_base16bpp(char *wrptr, u32 base) 74 { 75 /* the base pointer is 16 bits wide, 0x20 is hi byte. */ 76 wrptr = udl_set_register(wrptr, 0x20, base >> 16); 77 wrptr = udl_set_register(wrptr, 0x21, base >> 8); 78 return udl_set_register(wrptr, 0x22, base); 79 } 80 81 /* 82 * DisplayLink HW has separate 16bpp and 8bpp framebuffers. 83 * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer 84 */ 85 static char *udl_set_base8bpp(char *wrptr, u32 base) 86 { 87 wrptr = udl_set_register(wrptr, 0x26, base >> 16); 88 wrptr = udl_set_register(wrptr, 0x27, base >> 8); 89 return udl_set_register(wrptr, 0x28, base); 90 } 91 92 static char *udl_set_register_16(char *wrptr, u8 reg, u16 value) 93 { 94 wrptr = udl_set_register(wrptr, reg, value >> 8); 95 return udl_set_register(wrptr, reg+1, value); 96 } 97 98 /* 99 * This is kind of weird because the controller takes some 100 * register values in a different byte order than other registers. 101 */ 102 static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value) 103 { 104 wrptr = udl_set_register(wrptr, reg, value); 105 return udl_set_register(wrptr, reg+1, value >> 8); 106 } 107 108 /* 109 * LFSR is linear feedback shift register. The reason we have this is 110 * because the display controller needs to minimize the clock depth of 111 * various counters used in the display path. So this code reverses the 112 * provided value into the lfsr16 value by counting backwards to get 113 * the value that needs to be set in the hardware comparator to get the 114 * same actual count. This makes sense once you read above a couple of 115 * times and think about it from a hardware perspective. 116 */ 117 static u16 udl_lfsr16(u16 actual_count) 118 { 119 u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */ 120 121 while (actual_count--) { 122 lv = ((lv << 1) | 123 (((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1)) 124 & 0xFFFF; 125 } 126 127 return (u16) lv; 128 } 129 130 /* 131 * This does LFSR conversion on the value that is to be written. 132 * See LFSR explanation above for more detail. 133 */ 134 static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value) 135 { 136 return udl_set_register_16(wrptr, reg, udl_lfsr16(value)); 137 } 138 139 /* 140 * This takes a standard fbdev screeninfo struct and all of its monitor mode 141 * details and converts them into the DisplayLink equivalent register commands. 142 ERR(vreg(dev, 0x00, (color_depth == 16) ? 0 : 1)); 143 ERR(vreg_lfsr16(dev, 0x01, xDisplayStart)); 144 ERR(vreg_lfsr16(dev, 0x03, xDisplayEnd)); 145 ERR(vreg_lfsr16(dev, 0x05, yDisplayStart)); 146 ERR(vreg_lfsr16(dev, 0x07, yDisplayEnd)); 147 ERR(vreg_lfsr16(dev, 0x09, xEndCount)); 148 ERR(vreg_lfsr16(dev, 0x0B, hSyncStart)); 149 ERR(vreg_lfsr16(dev, 0x0D, hSyncEnd)); 150 ERR(vreg_big_endian(dev, 0x0F, hPixels)); 151 ERR(vreg_lfsr16(dev, 0x11, yEndCount)); 152 ERR(vreg_lfsr16(dev, 0x13, vSyncStart)); 153 ERR(vreg_lfsr16(dev, 0x15, vSyncEnd)); 154 ERR(vreg_big_endian(dev, 0x17, vPixels)); 155 ERR(vreg_little_endian(dev, 0x1B, pixelClock5KHz)); 156 157 ERR(vreg(dev, 0x1F, 0)); 158 159 ERR(vbuf(dev, WRITE_VIDREG_UNLOCK, DSIZEOF(WRITE_VIDREG_UNLOCK))); 160 */ 161 static char *udl_set_vid_cmds(char *wrptr, struct drm_display_mode *mode) 162 { 163 u16 xds, yds; 164 u16 xde, yde; 165 u16 yec; 166 167 /* x display start */ 168 xds = mode->crtc_htotal - mode->crtc_hsync_start; 169 wrptr = udl_set_register_lfsr16(wrptr, 0x01, xds); 170 /* x display end */ 171 xde = xds + mode->crtc_hdisplay; 172 wrptr = udl_set_register_lfsr16(wrptr, 0x03, xde); 173 174 /* y display start */ 175 yds = mode->crtc_vtotal - mode->crtc_vsync_start; 176 wrptr = udl_set_register_lfsr16(wrptr, 0x05, yds); 177 /* y display end */ 178 yde = yds + mode->crtc_vdisplay; 179 wrptr = udl_set_register_lfsr16(wrptr, 0x07, yde); 180 181 /* x end count is active + blanking - 1 */ 182 wrptr = udl_set_register_lfsr16(wrptr, 0x09, 183 mode->crtc_htotal - 1); 184 185 /* libdlo hardcodes hsync start to 1 */ 186 wrptr = udl_set_register_lfsr16(wrptr, 0x0B, 1); 187 188 /* hsync end is width of sync pulse + 1 */ 189 wrptr = udl_set_register_lfsr16(wrptr, 0x0D, 190 mode->crtc_hsync_end - mode->crtc_hsync_start + 1); 191 192 /* hpixels is active pixels */ 193 wrptr = udl_set_register_16(wrptr, 0x0F, mode->hdisplay); 194 195 /* yendcount is vertical active + vertical blanking */ 196 yec = mode->crtc_vtotal; 197 wrptr = udl_set_register_lfsr16(wrptr, 0x11, yec); 198 199 /* libdlo hardcodes vsync start to 0 */ 200 wrptr = udl_set_register_lfsr16(wrptr, 0x13, 0); 201 202 /* vsync end is width of vsync pulse */ 203 wrptr = udl_set_register_lfsr16(wrptr, 0x15, mode->crtc_vsync_end - mode->crtc_vsync_start); 204 205 /* vpixels is active pixels */ 206 wrptr = udl_set_register_16(wrptr, 0x17, mode->crtc_vdisplay); 207 208 wrptr = udl_set_register_16be(wrptr, 0x1B, 209 mode->clock / 5); 210 211 return wrptr; 212 } 213 214 static char *udl_dummy_render(char *wrptr) 215 { 216 *wrptr++ = 0xAF; 217 *wrptr++ = 0x6A; /* copy */ 218 *wrptr++ = 0x00; /* from addr */ 219 *wrptr++ = 0x00; 220 *wrptr++ = 0x00; 221 *wrptr++ = 0x01; /* one pixel */ 222 *wrptr++ = 0x00; /* to address */ 223 *wrptr++ = 0x00; 224 *wrptr++ = 0x00; 225 return wrptr; 226 } 227 228 static int udl_crtc_write_mode_to_hw(struct drm_crtc *crtc) 229 { 230 struct drm_device *dev = crtc->dev; 231 struct udl_device *udl = dev->dev_private; 232 struct urb *urb; 233 char *buf; 234 int retval; 235 236 urb = udl_get_urb(dev); 237 if (!urb) 238 return -ENOMEM; 239 240 buf = (char *)urb->transfer_buffer; 241 242 memcpy(buf, udl->mode_buf, udl->mode_buf_len); 243 retval = udl_submit_urb(dev, urb, udl->mode_buf_len); 244 DRM_DEBUG("write mode info %d\n", udl->mode_buf_len); 245 return retval; 246 } 247 248 249 static void udl_crtc_dpms(struct drm_crtc *crtc, int mode) 250 { 251 struct drm_device *dev = crtc->dev; 252 struct udl_device *udl = dev->dev_private; 253 int retval; 254 255 if (mode == DRM_MODE_DPMS_OFF) { 256 char *buf; 257 struct urb *urb; 258 urb = udl_get_urb(dev); 259 if (!urb) 260 return; 261 262 buf = (char *)urb->transfer_buffer; 263 buf = udl_vidreg_lock(buf); 264 buf = udl_set_blank(buf, mode); 265 buf = udl_vidreg_unlock(buf); 266 267 buf = udl_dummy_render(buf); 268 retval = udl_submit_urb(dev, urb, buf - (char *) 269 urb->transfer_buffer); 270 } else { 271 if (udl->mode_buf_len == 0) { 272 DRM_ERROR("Trying to enable DPMS with no mode\n"); 273 return; 274 } 275 udl_crtc_write_mode_to_hw(crtc); 276 } 277 278 } 279 280 #if 0 281 static int 282 udl_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, 283 int x, int y, enum mode_set_atomic state) 284 { 285 return 0; 286 } 287 288 static int 289 udl_pipe_set_base(struct drm_crtc *crtc, int x, int y, 290 struct drm_framebuffer *old_fb) 291 { 292 return 0; 293 } 294 #endif 295 296 static int udl_crtc_mode_set(struct drm_crtc *crtc, 297 struct drm_display_mode *mode, 298 struct drm_display_mode *adjusted_mode, 299 int x, int y, 300 struct drm_framebuffer *old_fb) 301 302 { 303 struct drm_device *dev = crtc->dev; 304 struct udl_framebuffer *ufb = to_udl_fb(crtc->primary->fb); 305 struct udl_device *udl = dev->dev_private; 306 char *buf; 307 char *wrptr; 308 int color_depth = 0; 309 310 udl->crtc = crtc; 311 312 buf = (char *)udl->mode_buf; 313 314 /* for now we just clip 24 -> 16 - if we fix that fix this */ 315 /*if (crtc->fb->bits_per_pixel != 16) 316 color_depth = 1; */ 317 318 /* This first section has to do with setting the base address on the 319 * controller * associated with the display. There are 2 base 320 * pointers, currently, we only * use the 16 bpp segment. 321 */ 322 wrptr = udl_vidreg_lock(buf); 323 wrptr = udl_set_color_depth(wrptr, color_depth); 324 /* set base for 16bpp segment to 0 */ 325 wrptr = udl_set_base16bpp(wrptr, 0); 326 /* set base for 8bpp segment to end of fb */ 327 wrptr = udl_set_base8bpp(wrptr, 2 * mode->vdisplay * mode->hdisplay); 328 329 wrptr = udl_set_vid_cmds(wrptr, adjusted_mode); 330 wrptr = udl_set_blank(wrptr, DRM_MODE_DPMS_ON); 331 wrptr = udl_vidreg_unlock(wrptr); 332 333 wrptr = udl_dummy_render(wrptr); 334 335 spin_lock(&udl->active_fb_16_lock); 336 udl->active_fb_16 = &ufb->base; 337 spin_unlock(&udl->active_fb_16_lock); 338 udl->mode_buf_len = wrptr - buf; 339 340 /* damage all of it */ 341 udl_handle_damage(ufb, 0, 0, ufb->base.width, ufb->base.height); 342 return 0; 343 } 344 345 346 static void udl_crtc_disable(struct drm_crtc *crtc) 347 { 348 udl_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 349 } 350 351 static void udl_crtc_destroy(struct drm_crtc *crtc) 352 { 353 drm_crtc_cleanup(crtc); 354 kfree(crtc); 355 } 356 357 static int udl_crtc_page_flip(struct drm_crtc *crtc, 358 struct drm_framebuffer *fb, 359 struct drm_pending_vblank_event *event, 360 uint32_t page_flip_flags, 361 struct drm_modeset_acquire_ctx *ctx) 362 { 363 struct udl_framebuffer *ufb = to_udl_fb(fb); 364 struct drm_device *dev = crtc->dev; 365 struct udl_device *udl = dev->dev_private; 366 367 spin_lock(&udl->active_fb_16_lock); 368 udl->active_fb_16 = fb; 369 spin_unlock(&udl->active_fb_16_lock); 370 371 udl_handle_damage(ufb, 0, 0, fb->width, fb->height); 372 373 spin_lock_irq(&dev->event_lock); 374 if (event) 375 drm_crtc_send_vblank_event(crtc, event); 376 spin_unlock_irq(&dev->event_lock); 377 crtc->primary->fb = fb; 378 379 return 0; 380 } 381 382 static void udl_crtc_prepare(struct drm_crtc *crtc) 383 { 384 } 385 386 static void udl_crtc_commit(struct drm_crtc *crtc) 387 { 388 udl_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 389 } 390 391 static const struct drm_crtc_helper_funcs udl_helper_funcs = { 392 .dpms = udl_crtc_dpms, 393 .mode_set = udl_crtc_mode_set, 394 .prepare = udl_crtc_prepare, 395 .commit = udl_crtc_commit, 396 .disable = udl_crtc_disable, 397 }; 398 399 static const struct drm_crtc_funcs udl_crtc_funcs = { 400 .set_config = drm_crtc_helper_set_config, 401 .destroy = udl_crtc_destroy, 402 .page_flip = udl_crtc_page_flip, 403 }; 404 405 static int udl_crtc_init(struct drm_device *dev) 406 { 407 struct drm_crtc *crtc; 408 409 crtc = kzalloc(sizeof(struct drm_crtc) + sizeof(struct drm_connector *), GFP_KERNEL); 410 if (crtc == NULL) 411 return -ENOMEM; 412 413 drm_crtc_init(dev, crtc, &udl_crtc_funcs); 414 drm_crtc_helper_add(crtc, &udl_helper_funcs); 415 416 return 0; 417 } 418 419 static const struct drm_mode_config_funcs udl_mode_funcs = { 420 .fb_create = udl_fb_user_fb_create, 421 }; 422 423 int udl_modeset_init(struct drm_device *dev) 424 { 425 struct drm_encoder *encoder; 426 drm_mode_config_init(dev); 427 428 dev->mode_config.min_width = 640; 429 dev->mode_config.min_height = 480; 430 431 dev->mode_config.max_width = 2048; 432 dev->mode_config.max_height = 2048; 433 434 dev->mode_config.prefer_shadow = 0; 435 dev->mode_config.preferred_depth = 24; 436 437 dev->mode_config.funcs = &udl_mode_funcs; 438 439 udl_crtc_init(dev); 440 441 encoder = udl_encoder_init(dev); 442 443 udl_connector_init(dev, encoder); 444 445 return 0; 446 } 447 448 void udl_modeset_restore(struct drm_device *dev) 449 { 450 struct udl_device *udl = dev->dev_private; 451 struct udl_framebuffer *ufb; 452 453 if (!udl->crtc || !udl->crtc->primary->fb) 454 return; 455 udl_crtc_commit(udl->crtc); 456 ufb = to_udl_fb(udl->crtc->primary->fb); 457 udl_handle_damage(ufb, 0, 0, ufb->base.width, ufb->base.height); 458 } 459 460 void udl_modeset_cleanup(struct drm_device *dev) 461 { 462 drm_mode_config_cleanup(dev); 463 } 464