1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Red Hat 4 * 5 * based in parts on udlfb.c: 6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it> 7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com> 8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com> 9 10 */ 11 12 #include <drm/drm_atomic_helper.h> 13 #include <drm/drm_crtc_helper.h> 14 #include <drm/drm_gem_framebuffer_helper.h> 15 #include <drm/drm_modeset_helper_vtables.h> 16 #include <drm/drm_vblank.h> 17 18 #include "udl_drv.h" 19 20 #define UDL_COLOR_DEPTH_16BPP 0 21 22 /* 23 * All DisplayLink bulk operations start with 0xAF, followed by specific code 24 * All operations are written to buffers which then later get sent to device 25 */ 26 static char *udl_set_register(char *buf, u8 reg, u8 val) 27 { 28 *buf++ = 0xAF; 29 *buf++ = 0x20; 30 *buf++ = reg; 31 *buf++ = val; 32 return buf; 33 } 34 35 static char *udl_vidreg_lock(char *buf) 36 { 37 return udl_set_register(buf, 0xFF, 0x00); 38 } 39 40 static char *udl_vidreg_unlock(char *buf) 41 { 42 return udl_set_register(buf, 0xFF, 0xFF); 43 } 44 45 /* 46 * On/Off for driving the DisplayLink framebuffer to the display 47 * 0x00 H and V sync on 48 * 0x01 H and V sync off (screen blank but powered) 49 * 0x07 DPMS powerdown (requires modeset to come back) 50 */ 51 static char *udl_set_blank(char *buf, int dpms_mode) 52 { 53 u8 reg; 54 switch (dpms_mode) { 55 case DRM_MODE_DPMS_OFF: 56 reg = 0x07; 57 break; 58 case DRM_MODE_DPMS_STANDBY: 59 reg = 0x05; 60 break; 61 case DRM_MODE_DPMS_SUSPEND: 62 reg = 0x01; 63 break; 64 case DRM_MODE_DPMS_ON: 65 reg = 0x00; 66 break; 67 } 68 69 return udl_set_register(buf, 0x1f, reg); 70 } 71 72 static char *udl_set_color_depth(char *buf, u8 selection) 73 { 74 return udl_set_register(buf, 0x00, selection); 75 } 76 77 static char *udl_set_base16bpp(char *wrptr, u32 base) 78 { 79 /* the base pointer is 16 bits wide, 0x20 is hi byte. */ 80 wrptr = udl_set_register(wrptr, 0x20, base >> 16); 81 wrptr = udl_set_register(wrptr, 0x21, base >> 8); 82 return udl_set_register(wrptr, 0x22, base); 83 } 84 85 /* 86 * DisplayLink HW has separate 16bpp and 8bpp framebuffers. 87 * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer 88 */ 89 static char *udl_set_base8bpp(char *wrptr, u32 base) 90 { 91 wrptr = udl_set_register(wrptr, 0x26, base >> 16); 92 wrptr = udl_set_register(wrptr, 0x27, base >> 8); 93 return udl_set_register(wrptr, 0x28, base); 94 } 95 96 static char *udl_set_register_16(char *wrptr, u8 reg, u16 value) 97 { 98 wrptr = udl_set_register(wrptr, reg, value >> 8); 99 return udl_set_register(wrptr, reg+1, value); 100 } 101 102 /* 103 * This is kind of weird because the controller takes some 104 * register values in a different byte order than other registers. 105 */ 106 static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value) 107 { 108 wrptr = udl_set_register(wrptr, reg, value); 109 return udl_set_register(wrptr, reg+1, value >> 8); 110 } 111 112 /* 113 * LFSR is linear feedback shift register. The reason we have this is 114 * because the display controller needs to minimize the clock depth of 115 * various counters used in the display path. So this code reverses the 116 * provided value into the lfsr16 value by counting backwards to get 117 * the value that needs to be set in the hardware comparator to get the 118 * same actual count. This makes sense once you read above a couple of 119 * times and think about it from a hardware perspective. 120 */ 121 static u16 udl_lfsr16(u16 actual_count) 122 { 123 u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */ 124 125 while (actual_count--) { 126 lv = ((lv << 1) | 127 (((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1)) 128 & 0xFFFF; 129 } 130 131 return (u16) lv; 132 } 133 134 /* 135 * This does LFSR conversion on the value that is to be written. 136 * See LFSR explanation above for more detail. 137 */ 138 static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value) 139 { 140 return udl_set_register_16(wrptr, reg, udl_lfsr16(value)); 141 } 142 143 /* 144 * This takes a standard fbdev screeninfo struct and all of its monitor mode 145 * details and converts them into the DisplayLink equivalent register commands. 146 ERR(vreg(dev, 0x00, (color_depth == 16) ? 0 : 1)); 147 ERR(vreg_lfsr16(dev, 0x01, xDisplayStart)); 148 ERR(vreg_lfsr16(dev, 0x03, xDisplayEnd)); 149 ERR(vreg_lfsr16(dev, 0x05, yDisplayStart)); 150 ERR(vreg_lfsr16(dev, 0x07, yDisplayEnd)); 151 ERR(vreg_lfsr16(dev, 0x09, xEndCount)); 152 ERR(vreg_lfsr16(dev, 0x0B, hSyncStart)); 153 ERR(vreg_lfsr16(dev, 0x0D, hSyncEnd)); 154 ERR(vreg_big_endian(dev, 0x0F, hPixels)); 155 ERR(vreg_lfsr16(dev, 0x11, yEndCount)); 156 ERR(vreg_lfsr16(dev, 0x13, vSyncStart)); 157 ERR(vreg_lfsr16(dev, 0x15, vSyncEnd)); 158 ERR(vreg_big_endian(dev, 0x17, vPixels)); 159 ERR(vreg_little_endian(dev, 0x1B, pixelClock5KHz)); 160 161 ERR(vreg(dev, 0x1F, 0)); 162 163 ERR(vbuf(dev, WRITE_VIDREG_UNLOCK, DSIZEOF(WRITE_VIDREG_UNLOCK))); 164 */ 165 static char *udl_set_vid_cmds(char *wrptr, struct drm_display_mode *mode) 166 { 167 u16 xds, yds; 168 u16 xde, yde; 169 u16 yec; 170 171 /* x display start */ 172 xds = mode->crtc_htotal - mode->crtc_hsync_start; 173 wrptr = udl_set_register_lfsr16(wrptr, 0x01, xds); 174 /* x display end */ 175 xde = xds + mode->crtc_hdisplay; 176 wrptr = udl_set_register_lfsr16(wrptr, 0x03, xde); 177 178 /* y display start */ 179 yds = mode->crtc_vtotal - mode->crtc_vsync_start; 180 wrptr = udl_set_register_lfsr16(wrptr, 0x05, yds); 181 /* y display end */ 182 yde = yds + mode->crtc_vdisplay; 183 wrptr = udl_set_register_lfsr16(wrptr, 0x07, yde); 184 185 /* x end count is active + blanking - 1 */ 186 wrptr = udl_set_register_lfsr16(wrptr, 0x09, 187 mode->crtc_htotal - 1); 188 189 /* libdlo hardcodes hsync start to 1 */ 190 wrptr = udl_set_register_lfsr16(wrptr, 0x0B, 1); 191 192 /* hsync end is width of sync pulse + 1 */ 193 wrptr = udl_set_register_lfsr16(wrptr, 0x0D, 194 mode->crtc_hsync_end - mode->crtc_hsync_start + 1); 195 196 /* hpixels is active pixels */ 197 wrptr = udl_set_register_16(wrptr, 0x0F, mode->hdisplay); 198 199 /* yendcount is vertical active + vertical blanking */ 200 yec = mode->crtc_vtotal; 201 wrptr = udl_set_register_lfsr16(wrptr, 0x11, yec); 202 203 /* libdlo hardcodes vsync start to 0 */ 204 wrptr = udl_set_register_lfsr16(wrptr, 0x13, 0); 205 206 /* vsync end is width of vsync pulse */ 207 wrptr = udl_set_register_lfsr16(wrptr, 0x15, mode->crtc_vsync_end - mode->crtc_vsync_start); 208 209 /* vpixels is active pixels */ 210 wrptr = udl_set_register_16(wrptr, 0x17, mode->crtc_vdisplay); 211 212 wrptr = udl_set_register_16be(wrptr, 0x1B, 213 mode->clock / 5); 214 215 return wrptr; 216 } 217 218 static char *udl_dummy_render(char *wrptr) 219 { 220 *wrptr++ = 0xAF; 221 *wrptr++ = 0x6A; /* copy */ 222 *wrptr++ = 0x00; /* from addr */ 223 *wrptr++ = 0x00; 224 *wrptr++ = 0x00; 225 *wrptr++ = 0x01; /* one pixel */ 226 *wrptr++ = 0x00; /* to address */ 227 *wrptr++ = 0x00; 228 *wrptr++ = 0x00; 229 return wrptr; 230 } 231 232 static int udl_crtc_write_mode_to_hw(struct drm_crtc *crtc) 233 { 234 struct drm_device *dev = crtc->dev; 235 struct udl_device *udl = dev->dev_private; 236 struct urb *urb; 237 char *buf; 238 int retval; 239 240 urb = udl_get_urb(dev); 241 if (!urb) 242 return -ENOMEM; 243 244 buf = (char *)urb->transfer_buffer; 245 246 memcpy(buf, udl->mode_buf, udl->mode_buf_len); 247 retval = udl_submit_urb(dev, urb, udl->mode_buf_len); 248 DRM_DEBUG("write mode info %d\n", udl->mode_buf_len); 249 return retval; 250 } 251 252 253 static void udl_crtc_dpms(struct drm_crtc *crtc, int mode) 254 { 255 struct drm_device *dev = crtc->dev; 256 struct udl_device *udl = dev->dev_private; 257 int retval; 258 259 if (mode == DRM_MODE_DPMS_OFF) { 260 char *buf; 261 struct urb *urb; 262 urb = udl_get_urb(dev); 263 if (!urb) 264 return; 265 266 buf = (char *)urb->transfer_buffer; 267 buf = udl_vidreg_lock(buf); 268 buf = udl_set_blank(buf, mode); 269 buf = udl_vidreg_unlock(buf); 270 271 buf = udl_dummy_render(buf); 272 retval = udl_submit_urb(dev, urb, buf - (char *) 273 urb->transfer_buffer); 274 } else { 275 if (udl->mode_buf_len == 0) { 276 DRM_ERROR("Trying to enable DPMS with no mode\n"); 277 return; 278 } 279 udl_crtc_write_mode_to_hw(crtc); 280 } 281 282 } 283 284 /* 285 * Simple display pipeline 286 */ 287 288 static const uint32_t udl_simple_display_pipe_formats[] = { 289 DRM_FORMAT_RGB565, 290 DRM_FORMAT_XRGB8888, 291 }; 292 293 static enum drm_mode_status 294 udl_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe, 295 const struct drm_display_mode *mode) 296 { 297 return MODE_OK; 298 } 299 300 static void 301 udl_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe, 302 struct drm_crtc_state *crtc_state, 303 struct drm_plane_state *plane_state) 304 { 305 struct drm_crtc *crtc = &pipe->crtc; 306 struct drm_device *dev = crtc->dev; 307 struct drm_framebuffer *fb = plane_state->fb; 308 struct udl_device *udl = dev->dev_private; 309 struct drm_display_mode *mode = &crtc_state->mode; 310 char *buf; 311 char *wrptr; 312 int color_depth = UDL_COLOR_DEPTH_16BPP; 313 314 crtc_state->no_vblank = true; 315 316 buf = (char *)udl->mode_buf; 317 318 /* This first section has to do with setting the base address on the 319 * controller associated with the display. There are 2 base 320 * pointers, currently, we only use the 16 bpp segment. 321 */ 322 wrptr = udl_vidreg_lock(buf); 323 wrptr = udl_set_color_depth(wrptr, color_depth); 324 /* set base for 16bpp segment to 0 */ 325 wrptr = udl_set_base16bpp(wrptr, 0); 326 /* set base for 8bpp segment to end of fb */ 327 wrptr = udl_set_base8bpp(wrptr, 2 * mode->vdisplay * mode->hdisplay); 328 329 wrptr = udl_set_vid_cmds(wrptr, mode); 330 wrptr = udl_set_blank(wrptr, DRM_MODE_DPMS_ON); 331 wrptr = udl_vidreg_unlock(wrptr); 332 333 wrptr = udl_dummy_render(wrptr); 334 335 spin_lock(&udl->active_fb_16_lock); 336 udl->active_fb_16 = fb; 337 spin_unlock(&udl->active_fb_16_lock); 338 udl->mode_buf_len = wrptr - buf; 339 340 udl_handle_damage(fb, 0, 0, fb->width, fb->height); 341 342 udl_crtc_dpms(&pipe->crtc, DRM_MODE_DPMS_ON); 343 } 344 345 static void 346 udl_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe) 347 { 348 udl_crtc_dpms(&pipe->crtc, DRM_MODE_DPMS_OFF); 349 } 350 351 static int 352 udl_simple_display_pipe_check(struct drm_simple_display_pipe *pipe, 353 struct drm_plane_state *plane_state, 354 struct drm_crtc_state *crtc_state) 355 { 356 return 0; 357 } 358 359 static void 360 udl_simple_display_pipe_update(struct drm_simple_display_pipe *pipe, 361 struct drm_plane_state *old_plane_state) 362 { 363 struct drm_device *dev = pipe->crtc.dev; 364 struct udl_device *udl = dev->dev_private; 365 struct drm_framebuffer *fb = pipe->plane.state->fb; 366 367 spin_lock(&udl->active_fb_16_lock); 368 udl->active_fb_16 = fb; 369 spin_unlock(&udl->active_fb_16_lock); 370 371 if (!fb) 372 return; 373 374 udl_handle_damage(fb, 0, 0, fb->width, fb->height); 375 } 376 377 static const 378 struct drm_simple_display_pipe_funcs udl_simple_display_pipe_funcs = { 379 .mode_valid = udl_simple_display_pipe_mode_valid, 380 .enable = udl_simple_display_pipe_enable, 381 .disable = udl_simple_display_pipe_disable, 382 .check = udl_simple_display_pipe_check, 383 .update = udl_simple_display_pipe_update, 384 .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb, 385 }; 386 387 /* 388 * Modesetting 389 */ 390 391 static const struct drm_mode_config_funcs udl_mode_funcs = { 392 .fb_create = udl_fb_user_fb_create, 393 .atomic_check = drm_atomic_helper_check, 394 .atomic_commit = drm_atomic_helper_commit, 395 }; 396 397 int udl_modeset_init(struct drm_device *dev) 398 { 399 size_t format_count = ARRAY_SIZE(udl_simple_display_pipe_formats); 400 struct udl_device *udl = dev->dev_private; 401 struct drm_connector *connector; 402 int ret; 403 404 drm_mode_config_init(dev); 405 406 dev->mode_config.min_width = 640; 407 dev->mode_config.min_height = 480; 408 409 dev->mode_config.max_width = 2048; 410 dev->mode_config.max_height = 2048; 411 412 dev->mode_config.prefer_shadow = 0; 413 dev->mode_config.preferred_depth = 24; 414 415 dev->mode_config.funcs = &udl_mode_funcs; 416 417 connector = udl_connector_init(dev); 418 if (IS_ERR(connector)) { 419 ret = PTR_ERR(connector); 420 goto err_drm_mode_config_cleanup; 421 } 422 423 format_count = ARRAY_SIZE(udl_simple_display_pipe_formats); 424 425 ret = drm_simple_display_pipe_init(dev, &udl->display_pipe, 426 &udl_simple_display_pipe_funcs, 427 udl_simple_display_pipe_formats, 428 format_count, NULL, connector); 429 if (ret) 430 goto err_drm_mode_config_cleanup; 431 432 drm_mode_config_reset(dev); 433 434 return 0; 435 436 err_drm_mode_config_cleanup: 437 drm_mode_config_cleanup(dev); 438 return ret; 439 } 440 441 void udl_modeset_restore(struct drm_device *dev) 442 { 443 struct udl_device *udl = dev->dev_private; 444 struct drm_crtc *crtc = &udl->display_pipe.crtc; 445 struct drm_plane *primary = &udl->display_pipe.plane; 446 struct drm_framebuffer *fb = primary->fb; 447 448 if (!fb) 449 return; 450 451 udl_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 452 udl_handle_damage(fb, 0, 0, fb->width, fb->height); 453 } 454 455 void udl_modeset_cleanup(struct drm_device *dev) 456 { 457 drm_mode_config_cleanup(dev); 458 } 459