1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Red Hat 4 * 5 * based in parts on udlfb.c: 6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it> 7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com> 8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com> 9 10 */ 11 12 #include <drm/drm_atomic_helper.h> 13 #include <drm/drm_crtc_helper.h> 14 #include <drm/drm_gem_framebuffer_helper.h> 15 #include <drm/drm_modeset_helper_vtables.h> 16 #include <drm/drm_vblank.h> 17 18 #include "udl_drv.h" 19 20 #define UDL_COLOR_DEPTH_16BPP 0 21 22 /* 23 * All DisplayLink bulk operations start with 0xAF, followed by specific code 24 * All operations are written to buffers which then later get sent to device 25 */ 26 static char *udl_set_register(char *buf, u8 reg, u8 val) 27 { 28 *buf++ = 0xAF; 29 *buf++ = 0x20; 30 *buf++ = reg; 31 *buf++ = val; 32 return buf; 33 } 34 35 static char *udl_vidreg_lock(char *buf) 36 { 37 return udl_set_register(buf, 0xFF, 0x00); 38 } 39 40 static char *udl_vidreg_unlock(char *buf) 41 { 42 return udl_set_register(buf, 0xFF, 0xFF); 43 } 44 45 static char *udl_set_blank_mode(char *buf, u8 mode) 46 { 47 return udl_set_register(buf, UDL_REG_BLANK_MODE, mode); 48 } 49 50 static char *udl_set_color_depth(char *buf, u8 selection) 51 { 52 return udl_set_register(buf, 0x00, selection); 53 } 54 55 static char *udl_set_base16bpp(char *wrptr, u32 base) 56 { 57 /* the base pointer is 16 bits wide, 0x20 is hi byte. */ 58 wrptr = udl_set_register(wrptr, 0x20, base >> 16); 59 wrptr = udl_set_register(wrptr, 0x21, base >> 8); 60 return udl_set_register(wrptr, 0x22, base); 61 } 62 63 /* 64 * DisplayLink HW has separate 16bpp and 8bpp framebuffers. 65 * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer 66 */ 67 static char *udl_set_base8bpp(char *wrptr, u32 base) 68 { 69 wrptr = udl_set_register(wrptr, 0x26, base >> 16); 70 wrptr = udl_set_register(wrptr, 0x27, base >> 8); 71 return udl_set_register(wrptr, 0x28, base); 72 } 73 74 static char *udl_set_register_16(char *wrptr, u8 reg, u16 value) 75 { 76 wrptr = udl_set_register(wrptr, reg, value >> 8); 77 return udl_set_register(wrptr, reg+1, value); 78 } 79 80 /* 81 * This is kind of weird because the controller takes some 82 * register values in a different byte order than other registers. 83 */ 84 static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value) 85 { 86 wrptr = udl_set_register(wrptr, reg, value); 87 return udl_set_register(wrptr, reg+1, value >> 8); 88 } 89 90 /* 91 * LFSR is linear feedback shift register. The reason we have this is 92 * because the display controller needs to minimize the clock depth of 93 * various counters used in the display path. So this code reverses the 94 * provided value into the lfsr16 value by counting backwards to get 95 * the value that needs to be set in the hardware comparator to get the 96 * same actual count. This makes sense once you read above a couple of 97 * times and think about it from a hardware perspective. 98 */ 99 static u16 udl_lfsr16(u16 actual_count) 100 { 101 u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */ 102 103 while (actual_count--) { 104 lv = ((lv << 1) | 105 (((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1)) 106 & 0xFFFF; 107 } 108 109 return (u16) lv; 110 } 111 112 /* 113 * This does LFSR conversion on the value that is to be written. 114 * See LFSR explanation above for more detail. 115 */ 116 static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value) 117 { 118 return udl_set_register_16(wrptr, reg, udl_lfsr16(value)); 119 } 120 121 /* 122 * This takes a standard fbdev screeninfo struct and all of its monitor mode 123 * details and converts them into the DisplayLink equivalent register commands. 124 ERR(vreg(dev, 0x00, (color_depth == 16) ? 0 : 1)); 125 ERR(vreg_lfsr16(dev, 0x01, xDisplayStart)); 126 ERR(vreg_lfsr16(dev, 0x03, xDisplayEnd)); 127 ERR(vreg_lfsr16(dev, 0x05, yDisplayStart)); 128 ERR(vreg_lfsr16(dev, 0x07, yDisplayEnd)); 129 ERR(vreg_lfsr16(dev, 0x09, xEndCount)); 130 ERR(vreg_lfsr16(dev, 0x0B, hSyncStart)); 131 ERR(vreg_lfsr16(dev, 0x0D, hSyncEnd)); 132 ERR(vreg_big_endian(dev, 0x0F, hPixels)); 133 ERR(vreg_lfsr16(dev, 0x11, yEndCount)); 134 ERR(vreg_lfsr16(dev, 0x13, vSyncStart)); 135 ERR(vreg_lfsr16(dev, 0x15, vSyncEnd)); 136 ERR(vreg_big_endian(dev, 0x17, vPixels)); 137 ERR(vreg_little_endian(dev, 0x1B, pixelClock5KHz)); 138 139 ERR(vreg(dev, 0x1F, 0)); 140 141 ERR(vbuf(dev, WRITE_VIDREG_UNLOCK, DSIZEOF(WRITE_VIDREG_UNLOCK))); 142 */ 143 static char *udl_set_vid_cmds(char *wrptr, struct drm_display_mode *mode) 144 { 145 u16 xds, yds; 146 u16 xde, yde; 147 u16 yec; 148 149 /* x display start */ 150 xds = mode->crtc_htotal - mode->crtc_hsync_start; 151 wrptr = udl_set_register_lfsr16(wrptr, 0x01, xds); 152 /* x display end */ 153 xde = xds + mode->crtc_hdisplay; 154 wrptr = udl_set_register_lfsr16(wrptr, 0x03, xde); 155 156 /* y display start */ 157 yds = mode->crtc_vtotal - mode->crtc_vsync_start; 158 wrptr = udl_set_register_lfsr16(wrptr, 0x05, yds); 159 /* y display end */ 160 yde = yds + mode->crtc_vdisplay; 161 wrptr = udl_set_register_lfsr16(wrptr, 0x07, yde); 162 163 /* x end count is active + blanking - 1 */ 164 wrptr = udl_set_register_lfsr16(wrptr, 0x09, 165 mode->crtc_htotal - 1); 166 167 /* libdlo hardcodes hsync start to 1 */ 168 wrptr = udl_set_register_lfsr16(wrptr, 0x0B, 1); 169 170 /* hsync end is width of sync pulse + 1 */ 171 wrptr = udl_set_register_lfsr16(wrptr, 0x0D, 172 mode->crtc_hsync_end - mode->crtc_hsync_start + 1); 173 174 /* hpixels is active pixels */ 175 wrptr = udl_set_register_16(wrptr, 0x0F, mode->hdisplay); 176 177 /* yendcount is vertical active + vertical blanking */ 178 yec = mode->crtc_vtotal; 179 wrptr = udl_set_register_lfsr16(wrptr, 0x11, yec); 180 181 /* libdlo hardcodes vsync start to 0 */ 182 wrptr = udl_set_register_lfsr16(wrptr, 0x13, 0); 183 184 /* vsync end is width of vsync pulse */ 185 wrptr = udl_set_register_lfsr16(wrptr, 0x15, mode->crtc_vsync_end - mode->crtc_vsync_start); 186 187 /* vpixels is active pixels */ 188 wrptr = udl_set_register_16(wrptr, 0x17, mode->crtc_vdisplay); 189 190 wrptr = udl_set_register_16be(wrptr, 0x1B, 191 mode->clock / 5); 192 193 return wrptr; 194 } 195 196 static char *udl_dummy_render(char *wrptr) 197 { 198 *wrptr++ = 0xAF; 199 *wrptr++ = 0x6A; /* copy */ 200 *wrptr++ = 0x00; /* from addr */ 201 *wrptr++ = 0x00; 202 *wrptr++ = 0x00; 203 *wrptr++ = 0x01; /* one pixel */ 204 *wrptr++ = 0x00; /* to address */ 205 *wrptr++ = 0x00; 206 *wrptr++ = 0x00; 207 return wrptr; 208 } 209 210 static int udl_crtc_write_mode_to_hw(struct drm_crtc *crtc) 211 { 212 struct drm_device *dev = crtc->dev; 213 struct udl_device *udl = dev->dev_private; 214 struct urb *urb; 215 char *buf; 216 int retval; 217 218 if (udl->mode_buf_len == 0) { 219 DRM_ERROR("No mode set\n"); 220 return -EINVAL; 221 } 222 223 urb = udl_get_urb(dev); 224 if (!urb) 225 return -ENOMEM; 226 227 buf = (char *)urb->transfer_buffer; 228 229 memcpy(buf, udl->mode_buf, udl->mode_buf_len); 230 retval = udl_submit_urb(dev, urb, udl->mode_buf_len); 231 DRM_DEBUG("write mode info %d\n", udl->mode_buf_len); 232 return retval; 233 } 234 235 /* 236 * Simple display pipeline 237 */ 238 239 static const uint32_t udl_simple_display_pipe_formats[] = { 240 DRM_FORMAT_RGB565, 241 DRM_FORMAT_XRGB8888, 242 }; 243 244 static enum drm_mode_status 245 udl_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe, 246 const struct drm_display_mode *mode) 247 { 248 return MODE_OK; 249 } 250 251 static void 252 udl_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe, 253 struct drm_crtc_state *crtc_state, 254 struct drm_plane_state *plane_state) 255 { 256 struct drm_crtc *crtc = &pipe->crtc; 257 struct drm_device *dev = crtc->dev; 258 struct drm_framebuffer *fb = plane_state->fb; 259 struct udl_device *udl = dev->dev_private; 260 struct drm_display_mode *mode = &crtc_state->mode; 261 char *buf; 262 char *wrptr; 263 int color_depth = UDL_COLOR_DEPTH_16BPP; 264 265 crtc_state->no_vblank = true; 266 267 buf = (char *)udl->mode_buf; 268 269 /* This first section has to do with setting the base address on the 270 * controller associated with the display. There are 2 base 271 * pointers, currently, we only use the 16 bpp segment. 272 */ 273 wrptr = udl_vidreg_lock(buf); 274 wrptr = udl_set_color_depth(wrptr, color_depth); 275 /* set base for 16bpp segment to 0 */ 276 wrptr = udl_set_base16bpp(wrptr, 0); 277 /* set base for 8bpp segment to end of fb */ 278 wrptr = udl_set_base8bpp(wrptr, 2 * mode->vdisplay * mode->hdisplay); 279 280 wrptr = udl_set_vid_cmds(wrptr, mode); 281 wrptr = udl_set_blank_mode(wrptr, UDL_BLANK_MODE_ON); 282 wrptr = udl_vidreg_unlock(wrptr); 283 284 wrptr = udl_dummy_render(wrptr); 285 286 spin_lock(&udl->active_fb_16_lock); 287 udl->active_fb_16 = fb; 288 spin_unlock(&udl->active_fb_16_lock); 289 udl->mode_buf_len = wrptr - buf; 290 291 udl_handle_damage(fb, 0, 0, fb->width, fb->height); 292 293 if (!crtc_state->mode_changed) 294 return; 295 296 /* enable display */ 297 udl_crtc_write_mode_to_hw(crtc); 298 } 299 300 static void 301 udl_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe) 302 { 303 struct drm_crtc *crtc = &pipe->crtc; 304 struct drm_device *dev = crtc->dev; 305 struct urb *urb; 306 char *buf; 307 308 urb = udl_get_urb(dev); 309 if (!urb) 310 return; 311 312 buf = (char *)urb->transfer_buffer; 313 buf = udl_vidreg_lock(buf); 314 buf = udl_set_blank_mode(buf, UDL_BLANK_MODE_POWERDOWN); 315 buf = udl_vidreg_unlock(buf); 316 buf = udl_dummy_render(buf); 317 318 udl_submit_urb(dev, urb, buf - (char *)urb->transfer_buffer); 319 } 320 321 static int 322 udl_simple_display_pipe_check(struct drm_simple_display_pipe *pipe, 323 struct drm_plane_state *plane_state, 324 struct drm_crtc_state *crtc_state) 325 { 326 return 0; 327 } 328 329 static void 330 udl_simple_display_pipe_update(struct drm_simple_display_pipe *pipe, 331 struct drm_plane_state *old_plane_state) 332 { 333 struct drm_device *dev = pipe->crtc.dev; 334 struct udl_device *udl = dev->dev_private; 335 struct drm_framebuffer *fb = pipe->plane.state->fb; 336 337 spin_lock(&udl->active_fb_16_lock); 338 udl->active_fb_16 = fb; 339 spin_unlock(&udl->active_fb_16_lock); 340 341 if (!fb) 342 return; 343 344 udl_handle_damage(fb, 0, 0, fb->width, fb->height); 345 } 346 347 static const 348 struct drm_simple_display_pipe_funcs udl_simple_display_pipe_funcs = { 349 .mode_valid = udl_simple_display_pipe_mode_valid, 350 .enable = udl_simple_display_pipe_enable, 351 .disable = udl_simple_display_pipe_disable, 352 .check = udl_simple_display_pipe_check, 353 .update = udl_simple_display_pipe_update, 354 .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb, 355 }; 356 357 /* 358 * Modesetting 359 */ 360 361 static const struct drm_mode_config_funcs udl_mode_funcs = { 362 .fb_create = udl_fb_user_fb_create, 363 .atomic_check = drm_atomic_helper_check, 364 .atomic_commit = drm_atomic_helper_commit, 365 }; 366 367 int udl_modeset_init(struct drm_device *dev) 368 { 369 size_t format_count = ARRAY_SIZE(udl_simple_display_pipe_formats); 370 struct udl_device *udl = dev->dev_private; 371 struct drm_connector *connector; 372 int ret; 373 374 drm_mode_config_init(dev); 375 376 dev->mode_config.min_width = 640; 377 dev->mode_config.min_height = 480; 378 379 dev->mode_config.max_width = 2048; 380 dev->mode_config.max_height = 2048; 381 382 dev->mode_config.prefer_shadow = 0; 383 dev->mode_config.preferred_depth = 24; 384 385 dev->mode_config.funcs = &udl_mode_funcs; 386 387 connector = udl_connector_init(dev); 388 if (IS_ERR(connector)) { 389 ret = PTR_ERR(connector); 390 goto err_drm_mode_config_cleanup; 391 } 392 393 format_count = ARRAY_SIZE(udl_simple_display_pipe_formats); 394 395 ret = drm_simple_display_pipe_init(dev, &udl->display_pipe, 396 &udl_simple_display_pipe_funcs, 397 udl_simple_display_pipe_formats, 398 format_count, NULL, connector); 399 if (ret) 400 goto err_drm_mode_config_cleanup; 401 402 drm_mode_config_reset(dev); 403 404 return 0; 405 406 err_drm_mode_config_cleanup: 407 drm_mode_config_cleanup(dev); 408 return ret; 409 } 410 411 void udl_modeset_cleanup(struct drm_device *dev) 412 { 413 drm_mode_config_cleanup(dev); 414 } 415