1 /* 2 * Copyright (C) 2012 Red Hat 3 * 4 * based in parts on udlfb.c: 5 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it> 6 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com> 7 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com> 8 9 * This file is subject to the terms and conditions of the GNU General Public 10 * License v2. See the file COPYING in the main directory of this archive for 11 * more details. 12 */ 13 14 #include <drm/drmP.h> 15 #include <drm/drm_crtc.h> 16 #include <drm/drm_crtc_helper.h> 17 #include <drm/drm_plane_helper.h> 18 #include "udl_drv.h" 19 20 /* 21 * All DisplayLink bulk operations start with 0xAF, followed by specific code 22 * All operations are written to buffers which then later get sent to device 23 */ 24 static char *udl_set_register(char *buf, u8 reg, u8 val) 25 { 26 *buf++ = 0xAF; 27 *buf++ = 0x20; 28 *buf++ = reg; 29 *buf++ = val; 30 return buf; 31 } 32 33 static char *udl_vidreg_lock(char *buf) 34 { 35 return udl_set_register(buf, 0xFF, 0x00); 36 } 37 38 static char *udl_vidreg_unlock(char *buf) 39 { 40 return udl_set_register(buf, 0xFF, 0xFF); 41 } 42 43 /* 44 * On/Off for driving the DisplayLink framebuffer to the display 45 * 0x00 H and V sync on 46 * 0x01 H and V sync off (screen blank but powered) 47 * 0x07 DPMS powerdown (requires modeset to come back) 48 */ 49 static char *udl_set_blank(char *buf, int dpms_mode) 50 { 51 u8 reg; 52 switch (dpms_mode) { 53 case DRM_MODE_DPMS_OFF: 54 reg = 0x07; 55 break; 56 case DRM_MODE_DPMS_STANDBY: 57 reg = 0x05; 58 break; 59 case DRM_MODE_DPMS_SUSPEND: 60 reg = 0x01; 61 break; 62 case DRM_MODE_DPMS_ON: 63 reg = 0x00; 64 break; 65 } 66 67 return udl_set_register(buf, 0x1f, reg); 68 } 69 70 static char *udl_set_color_depth(char *buf, u8 selection) 71 { 72 return udl_set_register(buf, 0x00, selection); 73 } 74 75 static char *udl_set_base16bpp(char *wrptr, u32 base) 76 { 77 /* the base pointer is 16 bits wide, 0x20 is hi byte. */ 78 wrptr = udl_set_register(wrptr, 0x20, base >> 16); 79 wrptr = udl_set_register(wrptr, 0x21, base >> 8); 80 return udl_set_register(wrptr, 0x22, base); 81 } 82 83 /* 84 * DisplayLink HW has separate 16bpp and 8bpp framebuffers. 85 * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer 86 */ 87 static char *udl_set_base8bpp(char *wrptr, u32 base) 88 { 89 wrptr = udl_set_register(wrptr, 0x26, base >> 16); 90 wrptr = udl_set_register(wrptr, 0x27, base >> 8); 91 return udl_set_register(wrptr, 0x28, base); 92 } 93 94 static char *udl_set_register_16(char *wrptr, u8 reg, u16 value) 95 { 96 wrptr = udl_set_register(wrptr, reg, value >> 8); 97 return udl_set_register(wrptr, reg+1, value); 98 } 99 100 /* 101 * This is kind of weird because the controller takes some 102 * register values in a different byte order than other registers. 103 */ 104 static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value) 105 { 106 wrptr = udl_set_register(wrptr, reg, value); 107 return udl_set_register(wrptr, reg+1, value >> 8); 108 } 109 110 /* 111 * LFSR is linear feedback shift register. The reason we have this is 112 * because the display controller needs to minimize the clock depth of 113 * various counters used in the display path. So this code reverses the 114 * provided value into the lfsr16 value by counting backwards to get 115 * the value that needs to be set in the hardware comparator to get the 116 * same actual count. This makes sense once you read above a couple of 117 * times and think about it from a hardware perspective. 118 */ 119 static u16 udl_lfsr16(u16 actual_count) 120 { 121 u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */ 122 123 while (actual_count--) { 124 lv = ((lv << 1) | 125 (((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1)) 126 & 0xFFFF; 127 } 128 129 return (u16) lv; 130 } 131 132 /* 133 * This does LFSR conversion on the value that is to be written. 134 * See LFSR explanation above for more detail. 135 */ 136 static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value) 137 { 138 return udl_set_register_16(wrptr, reg, udl_lfsr16(value)); 139 } 140 141 /* 142 * This takes a standard fbdev screeninfo struct and all of its monitor mode 143 * details and converts them into the DisplayLink equivalent register commands. 144 ERR(vreg(dev, 0x00, (color_depth == 16) ? 0 : 1)); 145 ERR(vreg_lfsr16(dev, 0x01, xDisplayStart)); 146 ERR(vreg_lfsr16(dev, 0x03, xDisplayEnd)); 147 ERR(vreg_lfsr16(dev, 0x05, yDisplayStart)); 148 ERR(vreg_lfsr16(dev, 0x07, yDisplayEnd)); 149 ERR(vreg_lfsr16(dev, 0x09, xEndCount)); 150 ERR(vreg_lfsr16(dev, 0x0B, hSyncStart)); 151 ERR(vreg_lfsr16(dev, 0x0D, hSyncEnd)); 152 ERR(vreg_big_endian(dev, 0x0F, hPixels)); 153 ERR(vreg_lfsr16(dev, 0x11, yEndCount)); 154 ERR(vreg_lfsr16(dev, 0x13, vSyncStart)); 155 ERR(vreg_lfsr16(dev, 0x15, vSyncEnd)); 156 ERR(vreg_big_endian(dev, 0x17, vPixels)); 157 ERR(vreg_little_endian(dev, 0x1B, pixelClock5KHz)); 158 159 ERR(vreg(dev, 0x1F, 0)); 160 161 ERR(vbuf(dev, WRITE_VIDREG_UNLOCK, DSIZEOF(WRITE_VIDREG_UNLOCK))); 162 */ 163 static char *udl_set_vid_cmds(char *wrptr, struct drm_display_mode *mode) 164 { 165 u16 xds, yds; 166 u16 xde, yde; 167 u16 yec; 168 169 /* x display start */ 170 xds = mode->crtc_htotal - mode->crtc_hsync_start; 171 wrptr = udl_set_register_lfsr16(wrptr, 0x01, xds); 172 /* x display end */ 173 xde = xds + mode->crtc_hdisplay; 174 wrptr = udl_set_register_lfsr16(wrptr, 0x03, xde); 175 176 /* y display start */ 177 yds = mode->crtc_vtotal - mode->crtc_vsync_start; 178 wrptr = udl_set_register_lfsr16(wrptr, 0x05, yds); 179 /* y display end */ 180 yde = yds + mode->crtc_vdisplay; 181 wrptr = udl_set_register_lfsr16(wrptr, 0x07, yde); 182 183 /* x end count is active + blanking - 1 */ 184 wrptr = udl_set_register_lfsr16(wrptr, 0x09, 185 mode->crtc_htotal - 1); 186 187 /* libdlo hardcodes hsync start to 1 */ 188 wrptr = udl_set_register_lfsr16(wrptr, 0x0B, 1); 189 190 /* hsync end is width of sync pulse + 1 */ 191 wrptr = udl_set_register_lfsr16(wrptr, 0x0D, 192 mode->crtc_hsync_end - mode->crtc_hsync_start + 1); 193 194 /* hpixels is active pixels */ 195 wrptr = udl_set_register_16(wrptr, 0x0F, mode->hdisplay); 196 197 /* yendcount is vertical active + vertical blanking */ 198 yec = mode->crtc_vtotal; 199 wrptr = udl_set_register_lfsr16(wrptr, 0x11, yec); 200 201 /* libdlo hardcodes vsync start to 0 */ 202 wrptr = udl_set_register_lfsr16(wrptr, 0x13, 0); 203 204 /* vsync end is width of vsync pulse */ 205 wrptr = udl_set_register_lfsr16(wrptr, 0x15, mode->crtc_vsync_end - mode->crtc_vsync_start); 206 207 /* vpixels is active pixels */ 208 wrptr = udl_set_register_16(wrptr, 0x17, mode->crtc_vdisplay); 209 210 wrptr = udl_set_register_16be(wrptr, 0x1B, 211 mode->clock / 5); 212 213 return wrptr; 214 } 215 216 static char *udl_dummy_render(char *wrptr) 217 { 218 *wrptr++ = 0xAF; 219 *wrptr++ = 0x6A; /* copy */ 220 *wrptr++ = 0x00; /* from addr */ 221 *wrptr++ = 0x00; 222 *wrptr++ = 0x00; 223 *wrptr++ = 0x01; /* one pixel */ 224 *wrptr++ = 0x00; /* to address */ 225 *wrptr++ = 0x00; 226 *wrptr++ = 0x00; 227 return wrptr; 228 } 229 230 static int udl_crtc_write_mode_to_hw(struct drm_crtc *crtc) 231 { 232 struct drm_device *dev = crtc->dev; 233 struct udl_device *udl = dev->dev_private; 234 struct urb *urb; 235 char *buf; 236 int retval; 237 238 urb = udl_get_urb(dev); 239 if (!urb) 240 return -ENOMEM; 241 242 buf = (char *)urb->transfer_buffer; 243 244 memcpy(buf, udl->mode_buf, udl->mode_buf_len); 245 retval = udl_submit_urb(dev, urb, udl->mode_buf_len); 246 DRM_INFO("write mode info %d\n", udl->mode_buf_len); 247 return retval; 248 } 249 250 251 static void udl_crtc_dpms(struct drm_crtc *crtc, int mode) 252 { 253 struct drm_device *dev = crtc->dev; 254 struct udl_device *udl = dev->dev_private; 255 int retval; 256 257 if (mode == DRM_MODE_DPMS_OFF) { 258 char *buf; 259 struct urb *urb; 260 urb = udl_get_urb(dev); 261 if (!urb) 262 return; 263 264 buf = (char *)urb->transfer_buffer; 265 buf = udl_vidreg_lock(buf); 266 buf = udl_set_blank(buf, mode); 267 buf = udl_vidreg_unlock(buf); 268 269 buf = udl_dummy_render(buf); 270 retval = udl_submit_urb(dev, urb, buf - (char *) 271 urb->transfer_buffer); 272 } else { 273 if (udl->mode_buf_len == 0) { 274 DRM_ERROR("Trying to enable DPMS with no mode\n"); 275 return; 276 } 277 udl_crtc_write_mode_to_hw(crtc); 278 } 279 280 } 281 282 #if 0 283 static int 284 udl_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, 285 int x, int y, enum mode_set_atomic state) 286 { 287 return 0; 288 } 289 290 static int 291 udl_pipe_set_base(struct drm_crtc *crtc, int x, int y, 292 struct drm_framebuffer *old_fb) 293 { 294 return 0; 295 } 296 #endif 297 298 static int udl_crtc_mode_set(struct drm_crtc *crtc, 299 struct drm_display_mode *mode, 300 struct drm_display_mode *adjusted_mode, 301 int x, int y, 302 struct drm_framebuffer *old_fb) 303 304 { 305 struct drm_device *dev = crtc->dev; 306 struct udl_framebuffer *ufb = to_udl_fb(crtc->primary->fb); 307 struct udl_device *udl = dev->dev_private; 308 char *buf; 309 char *wrptr; 310 int color_depth = 0; 311 312 udl->crtc = crtc; 313 314 buf = (char *)udl->mode_buf; 315 316 /* for now we just clip 24 -> 16 - if we fix that fix this */ 317 /*if (crtc->fb->bits_per_pixel != 16) 318 color_depth = 1; */ 319 320 /* This first section has to do with setting the base address on the 321 * controller * associated with the display. There are 2 base 322 * pointers, currently, we only * use the 16 bpp segment. 323 */ 324 wrptr = udl_vidreg_lock(buf); 325 wrptr = udl_set_color_depth(wrptr, color_depth); 326 /* set base for 16bpp segment to 0 */ 327 wrptr = udl_set_base16bpp(wrptr, 0); 328 /* set base for 8bpp segment to end of fb */ 329 wrptr = udl_set_base8bpp(wrptr, 2 * mode->vdisplay * mode->hdisplay); 330 331 wrptr = udl_set_vid_cmds(wrptr, adjusted_mode); 332 wrptr = udl_set_blank(wrptr, DRM_MODE_DPMS_ON); 333 wrptr = udl_vidreg_unlock(wrptr); 334 335 wrptr = udl_dummy_render(wrptr); 336 337 if (old_fb) { 338 struct udl_framebuffer *uold_fb = to_udl_fb(old_fb); 339 uold_fb->active_16 = false; 340 } 341 ufb->active_16 = true; 342 udl->mode_buf_len = wrptr - buf; 343 344 /* damage all of it */ 345 udl_handle_damage(ufb, 0, 0, ufb->base.width, ufb->base.height); 346 return 0; 347 } 348 349 350 static void udl_crtc_disable(struct drm_crtc *crtc) 351 { 352 udl_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 353 } 354 355 static void udl_crtc_destroy(struct drm_crtc *crtc) 356 { 357 drm_crtc_cleanup(crtc); 358 kfree(crtc); 359 } 360 361 static int udl_crtc_page_flip(struct drm_crtc *crtc, 362 struct drm_framebuffer *fb, 363 struct drm_pending_vblank_event *event, 364 uint32_t page_flip_flags, 365 struct drm_modeset_acquire_ctx *ctx) 366 { 367 struct udl_framebuffer *ufb = to_udl_fb(fb); 368 struct drm_device *dev = crtc->dev; 369 unsigned long flags; 370 371 struct drm_framebuffer *old_fb = crtc->primary->fb; 372 if (old_fb) { 373 struct udl_framebuffer *uold_fb = to_udl_fb(old_fb); 374 uold_fb->active_16 = false; 375 } 376 ufb->active_16 = true; 377 378 udl_handle_damage(ufb, 0, 0, fb->width, fb->height); 379 380 spin_lock_irqsave(&dev->event_lock, flags); 381 if (event) 382 drm_crtc_send_vblank_event(crtc, event); 383 spin_unlock_irqrestore(&dev->event_lock, flags); 384 crtc->primary->fb = fb; 385 386 return 0; 387 } 388 389 static void udl_crtc_prepare(struct drm_crtc *crtc) 390 { 391 } 392 393 static void udl_crtc_commit(struct drm_crtc *crtc) 394 { 395 udl_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 396 } 397 398 static const struct drm_crtc_helper_funcs udl_helper_funcs = { 399 .dpms = udl_crtc_dpms, 400 .mode_set = udl_crtc_mode_set, 401 .prepare = udl_crtc_prepare, 402 .commit = udl_crtc_commit, 403 .disable = udl_crtc_disable, 404 }; 405 406 static const struct drm_crtc_funcs udl_crtc_funcs = { 407 .set_config = drm_crtc_helper_set_config, 408 .destroy = udl_crtc_destroy, 409 .page_flip = udl_crtc_page_flip, 410 }; 411 412 static int udl_crtc_init(struct drm_device *dev) 413 { 414 struct drm_crtc *crtc; 415 416 crtc = kzalloc(sizeof(struct drm_crtc) + sizeof(struct drm_connector *), GFP_KERNEL); 417 if (crtc == NULL) 418 return -ENOMEM; 419 420 drm_crtc_init(dev, crtc, &udl_crtc_funcs); 421 drm_crtc_helper_add(crtc, &udl_helper_funcs); 422 423 return 0; 424 } 425 426 static const struct drm_mode_config_funcs udl_mode_funcs = { 427 .fb_create = udl_fb_user_fb_create, 428 .output_poll_changed = NULL, 429 }; 430 431 int udl_modeset_init(struct drm_device *dev) 432 { 433 struct drm_encoder *encoder; 434 drm_mode_config_init(dev); 435 436 dev->mode_config.min_width = 640; 437 dev->mode_config.min_height = 480; 438 439 dev->mode_config.max_width = 2048; 440 dev->mode_config.max_height = 2048; 441 442 dev->mode_config.prefer_shadow = 0; 443 dev->mode_config.preferred_depth = 24; 444 445 dev->mode_config.funcs = &udl_mode_funcs; 446 447 udl_crtc_init(dev); 448 449 encoder = udl_encoder_init(dev); 450 451 udl_connector_init(dev, encoder); 452 453 return 0; 454 } 455 456 void udl_modeset_restore(struct drm_device *dev) 457 { 458 struct udl_device *udl = dev->dev_private; 459 struct udl_framebuffer *ufb; 460 461 if (!udl->crtc || !udl->crtc->primary->fb) 462 return; 463 udl_crtc_commit(udl->crtc); 464 ufb = to_udl_fb(udl->crtc->primary->fb); 465 udl_handle_damage(ufb, 0, 0, ufb->base.width, ufb->base.height); 466 } 467 468 void udl_modeset_cleanup(struct drm_device *dev) 469 { 470 drm_mode_config_cleanup(dev); 471 } 472