1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Red Hat 4 * 5 * based in parts on udlfb.c: 6 * Copyright (C) 2009 Roberto De Ioris <roberto@unbit.it> 7 * Copyright (C) 2009 Jaya Kumar <jayakumar.lkml@gmail.com> 8 * Copyright (C) 2009 Bernie Thompson <bernie@plugable.com> 9 10 */ 11 12 #include <drm/drm_atomic_helper.h> 13 #include <drm/drm_crtc_helper.h> 14 #include <drm/drm_damage_helper.h> 15 #include <drm/drm_gem_framebuffer_helper.h> 16 #include <drm/drm_modeset_helper_vtables.h> 17 #include <drm/drm_vblank.h> 18 19 #include "udl_drv.h" 20 21 #define UDL_COLOR_DEPTH_16BPP 0 22 23 /* 24 * All DisplayLink bulk operations start with 0xAF, followed by specific code 25 * All operations are written to buffers which then later get sent to device 26 */ 27 static char *udl_set_register(char *buf, u8 reg, u8 val) 28 { 29 *buf++ = 0xAF; 30 *buf++ = 0x20; 31 *buf++ = reg; 32 *buf++ = val; 33 return buf; 34 } 35 36 static char *udl_vidreg_lock(char *buf) 37 { 38 return udl_set_register(buf, 0xFF, 0x00); 39 } 40 41 static char *udl_vidreg_unlock(char *buf) 42 { 43 return udl_set_register(buf, 0xFF, 0xFF); 44 } 45 46 static char *udl_set_blank_mode(char *buf, u8 mode) 47 { 48 return udl_set_register(buf, UDL_REG_BLANK_MODE, mode); 49 } 50 51 static char *udl_set_color_depth(char *buf, u8 selection) 52 { 53 return udl_set_register(buf, 0x00, selection); 54 } 55 56 static char *udl_set_base16bpp(char *wrptr, u32 base) 57 { 58 /* the base pointer is 16 bits wide, 0x20 is hi byte. */ 59 wrptr = udl_set_register(wrptr, 0x20, base >> 16); 60 wrptr = udl_set_register(wrptr, 0x21, base >> 8); 61 return udl_set_register(wrptr, 0x22, base); 62 } 63 64 /* 65 * DisplayLink HW has separate 16bpp and 8bpp framebuffers. 66 * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer 67 */ 68 static char *udl_set_base8bpp(char *wrptr, u32 base) 69 { 70 wrptr = udl_set_register(wrptr, 0x26, base >> 16); 71 wrptr = udl_set_register(wrptr, 0x27, base >> 8); 72 return udl_set_register(wrptr, 0x28, base); 73 } 74 75 static char *udl_set_register_16(char *wrptr, u8 reg, u16 value) 76 { 77 wrptr = udl_set_register(wrptr, reg, value >> 8); 78 return udl_set_register(wrptr, reg+1, value); 79 } 80 81 /* 82 * This is kind of weird because the controller takes some 83 * register values in a different byte order than other registers. 84 */ 85 static char *udl_set_register_16be(char *wrptr, u8 reg, u16 value) 86 { 87 wrptr = udl_set_register(wrptr, reg, value); 88 return udl_set_register(wrptr, reg+1, value >> 8); 89 } 90 91 /* 92 * LFSR is linear feedback shift register. The reason we have this is 93 * because the display controller needs to minimize the clock depth of 94 * various counters used in the display path. So this code reverses the 95 * provided value into the lfsr16 value by counting backwards to get 96 * the value that needs to be set in the hardware comparator to get the 97 * same actual count. This makes sense once you read above a couple of 98 * times and think about it from a hardware perspective. 99 */ 100 static u16 udl_lfsr16(u16 actual_count) 101 { 102 u32 lv = 0xFFFF; /* This is the lfsr value that the hw starts with */ 103 104 while (actual_count--) { 105 lv = ((lv << 1) | 106 (((lv >> 15) ^ (lv >> 4) ^ (lv >> 2) ^ (lv >> 1)) & 1)) 107 & 0xFFFF; 108 } 109 110 return (u16) lv; 111 } 112 113 /* 114 * This does LFSR conversion on the value that is to be written. 115 * See LFSR explanation above for more detail. 116 */ 117 static char *udl_set_register_lfsr16(char *wrptr, u8 reg, u16 value) 118 { 119 return udl_set_register_16(wrptr, reg, udl_lfsr16(value)); 120 } 121 122 /* 123 * This takes a standard fbdev screeninfo struct and all of its monitor mode 124 * details and converts them into the DisplayLink equivalent register commands. 125 ERR(vreg(dev, 0x00, (color_depth == 16) ? 0 : 1)); 126 ERR(vreg_lfsr16(dev, 0x01, xDisplayStart)); 127 ERR(vreg_lfsr16(dev, 0x03, xDisplayEnd)); 128 ERR(vreg_lfsr16(dev, 0x05, yDisplayStart)); 129 ERR(vreg_lfsr16(dev, 0x07, yDisplayEnd)); 130 ERR(vreg_lfsr16(dev, 0x09, xEndCount)); 131 ERR(vreg_lfsr16(dev, 0x0B, hSyncStart)); 132 ERR(vreg_lfsr16(dev, 0x0D, hSyncEnd)); 133 ERR(vreg_big_endian(dev, 0x0F, hPixels)); 134 ERR(vreg_lfsr16(dev, 0x11, yEndCount)); 135 ERR(vreg_lfsr16(dev, 0x13, vSyncStart)); 136 ERR(vreg_lfsr16(dev, 0x15, vSyncEnd)); 137 ERR(vreg_big_endian(dev, 0x17, vPixels)); 138 ERR(vreg_little_endian(dev, 0x1B, pixelClock5KHz)); 139 140 ERR(vreg(dev, 0x1F, 0)); 141 142 ERR(vbuf(dev, WRITE_VIDREG_UNLOCK, DSIZEOF(WRITE_VIDREG_UNLOCK))); 143 */ 144 static char *udl_set_vid_cmds(char *wrptr, struct drm_display_mode *mode) 145 { 146 u16 xds, yds; 147 u16 xde, yde; 148 u16 yec; 149 150 /* x display start */ 151 xds = mode->crtc_htotal - mode->crtc_hsync_start; 152 wrptr = udl_set_register_lfsr16(wrptr, 0x01, xds); 153 /* x display end */ 154 xde = xds + mode->crtc_hdisplay; 155 wrptr = udl_set_register_lfsr16(wrptr, 0x03, xde); 156 157 /* y display start */ 158 yds = mode->crtc_vtotal - mode->crtc_vsync_start; 159 wrptr = udl_set_register_lfsr16(wrptr, 0x05, yds); 160 /* y display end */ 161 yde = yds + mode->crtc_vdisplay; 162 wrptr = udl_set_register_lfsr16(wrptr, 0x07, yde); 163 164 /* x end count is active + blanking - 1 */ 165 wrptr = udl_set_register_lfsr16(wrptr, 0x09, 166 mode->crtc_htotal - 1); 167 168 /* libdlo hardcodes hsync start to 1 */ 169 wrptr = udl_set_register_lfsr16(wrptr, 0x0B, 1); 170 171 /* hsync end is width of sync pulse + 1 */ 172 wrptr = udl_set_register_lfsr16(wrptr, 0x0D, 173 mode->crtc_hsync_end - mode->crtc_hsync_start + 1); 174 175 /* hpixels is active pixels */ 176 wrptr = udl_set_register_16(wrptr, 0x0F, mode->hdisplay); 177 178 /* yendcount is vertical active + vertical blanking */ 179 yec = mode->crtc_vtotal; 180 wrptr = udl_set_register_lfsr16(wrptr, 0x11, yec); 181 182 /* libdlo hardcodes vsync start to 0 */ 183 wrptr = udl_set_register_lfsr16(wrptr, 0x13, 0); 184 185 /* vsync end is width of vsync pulse */ 186 wrptr = udl_set_register_lfsr16(wrptr, 0x15, mode->crtc_vsync_end - mode->crtc_vsync_start); 187 188 /* vpixels is active pixels */ 189 wrptr = udl_set_register_16(wrptr, 0x17, mode->crtc_vdisplay); 190 191 wrptr = udl_set_register_16be(wrptr, 0x1B, 192 mode->clock / 5); 193 194 return wrptr; 195 } 196 197 static char *udl_dummy_render(char *wrptr) 198 { 199 *wrptr++ = 0xAF; 200 *wrptr++ = 0x6A; /* copy */ 201 *wrptr++ = 0x00; /* from addr */ 202 *wrptr++ = 0x00; 203 *wrptr++ = 0x00; 204 *wrptr++ = 0x01; /* one pixel */ 205 *wrptr++ = 0x00; /* to address */ 206 *wrptr++ = 0x00; 207 *wrptr++ = 0x00; 208 return wrptr; 209 } 210 211 static int udl_crtc_write_mode_to_hw(struct drm_crtc *crtc) 212 { 213 struct drm_device *dev = crtc->dev; 214 struct udl_device *udl = dev->dev_private; 215 struct urb *urb; 216 char *buf; 217 int retval; 218 219 if (udl->mode_buf_len == 0) { 220 DRM_ERROR("No mode set\n"); 221 return -EINVAL; 222 } 223 224 urb = udl_get_urb(dev); 225 if (!urb) 226 return -ENOMEM; 227 228 buf = (char *)urb->transfer_buffer; 229 230 memcpy(buf, udl->mode_buf, udl->mode_buf_len); 231 retval = udl_submit_urb(dev, urb, udl->mode_buf_len); 232 DRM_DEBUG("write mode info %d\n", udl->mode_buf_len); 233 return retval; 234 } 235 236 /* 237 * Simple display pipeline 238 */ 239 240 static const uint32_t udl_simple_display_pipe_formats[] = { 241 DRM_FORMAT_RGB565, 242 DRM_FORMAT_XRGB8888, 243 }; 244 245 static enum drm_mode_status 246 udl_simple_display_pipe_mode_valid(struct drm_simple_display_pipe *pipe, 247 const struct drm_display_mode *mode) 248 { 249 return MODE_OK; 250 } 251 252 static void 253 udl_simple_display_pipe_enable(struct drm_simple_display_pipe *pipe, 254 struct drm_crtc_state *crtc_state, 255 struct drm_plane_state *plane_state) 256 { 257 struct drm_crtc *crtc = &pipe->crtc; 258 struct drm_device *dev = crtc->dev; 259 struct drm_framebuffer *fb = plane_state->fb; 260 struct udl_device *udl = dev->dev_private; 261 struct drm_display_mode *mode = &crtc_state->mode; 262 char *buf; 263 char *wrptr; 264 int color_depth = UDL_COLOR_DEPTH_16BPP; 265 266 crtc_state->no_vblank = true; 267 268 buf = (char *)udl->mode_buf; 269 270 /* This first section has to do with setting the base address on the 271 * controller associated with the display. There are 2 base 272 * pointers, currently, we only use the 16 bpp segment. 273 */ 274 wrptr = udl_vidreg_lock(buf); 275 wrptr = udl_set_color_depth(wrptr, color_depth); 276 /* set base for 16bpp segment to 0 */ 277 wrptr = udl_set_base16bpp(wrptr, 0); 278 /* set base for 8bpp segment to end of fb */ 279 wrptr = udl_set_base8bpp(wrptr, 2 * mode->vdisplay * mode->hdisplay); 280 281 wrptr = udl_set_vid_cmds(wrptr, mode); 282 wrptr = udl_set_blank_mode(wrptr, UDL_BLANK_MODE_ON); 283 wrptr = udl_vidreg_unlock(wrptr); 284 285 wrptr = udl_dummy_render(wrptr); 286 287 spin_lock(&udl->active_fb_16_lock); 288 udl->active_fb_16 = fb; 289 spin_unlock(&udl->active_fb_16_lock); 290 udl->mode_buf_len = wrptr - buf; 291 292 udl_handle_damage(fb, 0, 0, fb->width, fb->height); 293 294 if (!crtc_state->mode_changed) 295 return; 296 297 /* enable display */ 298 udl_crtc_write_mode_to_hw(crtc); 299 } 300 301 static void 302 udl_simple_display_pipe_disable(struct drm_simple_display_pipe *pipe) 303 { 304 struct drm_crtc *crtc = &pipe->crtc; 305 struct drm_device *dev = crtc->dev; 306 struct urb *urb; 307 char *buf; 308 309 urb = udl_get_urb(dev); 310 if (!urb) 311 return; 312 313 buf = (char *)urb->transfer_buffer; 314 buf = udl_vidreg_lock(buf); 315 buf = udl_set_blank_mode(buf, UDL_BLANK_MODE_POWERDOWN); 316 buf = udl_vidreg_unlock(buf); 317 buf = udl_dummy_render(buf); 318 319 udl_submit_urb(dev, urb, buf - (char *)urb->transfer_buffer); 320 } 321 322 static int 323 udl_simple_display_pipe_check(struct drm_simple_display_pipe *pipe, 324 struct drm_plane_state *plane_state, 325 struct drm_crtc_state *crtc_state) 326 { 327 return 0; 328 } 329 330 static void 331 udl_simple_display_pipe_update(struct drm_simple_display_pipe *pipe, 332 struct drm_plane_state *old_plane_state) 333 { 334 struct drm_device *dev = pipe->crtc.dev; 335 struct udl_device *udl = dev->dev_private; 336 struct drm_plane_state *state = pipe->plane.state; 337 struct drm_framebuffer *fb = state->fb; 338 struct drm_rect rect; 339 340 spin_lock(&udl->active_fb_16_lock); 341 udl->active_fb_16 = fb; 342 spin_unlock(&udl->active_fb_16_lock); 343 344 if (!fb) 345 return; 346 347 if (drm_atomic_helper_damage_merged(old_plane_state, state, &rect)) 348 udl_handle_damage(fb, rect.x1, rect.y1, rect.x2 - rect.x1, 349 rect.y2 - rect.y1); 350 } 351 352 static const 353 struct drm_simple_display_pipe_funcs udl_simple_display_pipe_funcs = { 354 .mode_valid = udl_simple_display_pipe_mode_valid, 355 .enable = udl_simple_display_pipe_enable, 356 .disable = udl_simple_display_pipe_disable, 357 .check = udl_simple_display_pipe_check, 358 .update = udl_simple_display_pipe_update, 359 .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb, 360 }; 361 362 /* 363 * Modesetting 364 */ 365 366 static const struct drm_mode_config_funcs udl_mode_funcs = { 367 .fb_create = drm_gem_fb_create_with_dirty, 368 .atomic_check = drm_atomic_helper_check, 369 .atomic_commit = drm_atomic_helper_commit, 370 }; 371 372 int udl_modeset_init(struct drm_device *dev) 373 { 374 size_t format_count = ARRAY_SIZE(udl_simple_display_pipe_formats); 375 struct udl_device *udl = dev->dev_private; 376 struct drm_connector *connector; 377 int ret; 378 379 drm_mode_config_init(dev); 380 381 dev->mode_config.min_width = 640; 382 dev->mode_config.min_height = 480; 383 384 dev->mode_config.max_width = 2048; 385 dev->mode_config.max_height = 2048; 386 387 dev->mode_config.prefer_shadow = 0; 388 dev->mode_config.preferred_depth = 16; 389 390 dev->mode_config.funcs = &udl_mode_funcs; 391 392 connector = udl_connector_init(dev); 393 if (IS_ERR(connector)) { 394 ret = PTR_ERR(connector); 395 goto err_drm_mode_config_cleanup; 396 } 397 398 format_count = ARRAY_SIZE(udl_simple_display_pipe_formats); 399 400 ret = drm_simple_display_pipe_init(dev, &udl->display_pipe, 401 &udl_simple_display_pipe_funcs, 402 udl_simple_display_pipe_formats, 403 format_count, NULL, connector); 404 if (ret) 405 goto err_drm_mode_config_cleanup; 406 407 drm_mode_config_reset(dev); 408 409 return 0; 410 411 err_drm_mode_config_cleanup: 412 drm_mode_config_cleanup(dev); 413 return ret; 414 } 415 416 void udl_modeset_cleanup(struct drm_device *dev) 417 { 418 drm_mode_config_cleanup(dev); 419 } 420