1 /* 2 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 3 * Parts of this file were based on sources as follows: 4 * 5 * Copyright (C) 2006-2008 Intel Corporation 6 * Copyright (C) 2007 Amos Lee <amos_lee@storlinksemi.com> 7 * Copyright (C) 2007 Dave Airlie <airlied@linux.ie> 8 * Copyright (C) 2011 Texas Instruments 9 * Copyright (C) 2017 Eric Anholt 10 * 11 * This program is free software and is provided to you under the terms of the 12 * GNU General Public License version 2 as published by the Free Software 13 * Foundation, and any use by you of this program is subject to the terms of 14 * such GNU licence. 15 */ 16 #include <linux/clk.h> 17 #include <linux/version.h> 18 #include <linux/dma-buf.h> 19 #include <linux/of_graph.h> 20 21 #include <drm/drmP.h> 22 #include <drm/drm_panel.h> 23 #include <drm/drm_gem_cma_helper.h> 24 #include <drm/drm_gem_framebuffer_helper.h> 25 #include <drm/drm_fb_cma_helper.h> 26 27 #include "tve200_drm.h" 28 29 irqreturn_t tve200_irq(int irq, void *data) 30 { 31 struct tve200_drm_dev_private *priv = data; 32 u32 stat; 33 u32 val; 34 35 stat = readl(priv->regs + TVE200_INT_STAT); 36 37 if (!stat) 38 return IRQ_NONE; 39 40 /* 41 * Vblank IRQ 42 * 43 * The hardware is a bit tilted: the line stays high after clearing 44 * the vblank IRQ, firing many more interrupts. We counter this 45 * by toggling the IRQ back and forth from firing at vblank and 46 * firing at start of active image, which works around the problem 47 * since those occur strictly in sequence, and we get two IRQs for each 48 * frame, one at start of Vblank (that we make call into the CRTC) and 49 * another one at the start of the image (that we discard). 50 */ 51 if (stat & TVE200_INT_V_STATUS) { 52 val = readl(priv->regs + TVE200_CTRL); 53 /* We have an actual start of vsync */ 54 if (!(val & TVE200_VSTSTYPE_BITS)) { 55 drm_crtc_handle_vblank(&priv->pipe.crtc); 56 /* Toggle trigger to start of active image */ 57 val |= TVE200_VSTSTYPE_VAI; 58 } else { 59 /* Toggle trigger back to start of vsync */ 60 val &= ~TVE200_VSTSTYPE_BITS; 61 } 62 writel(val, priv->regs + TVE200_CTRL); 63 } else 64 dev_err(priv->drm->dev, "stray IRQ %08x\n", stat); 65 66 /* Clear the interrupt once done */ 67 writel(stat, priv->regs + TVE200_INT_CLR); 68 69 return IRQ_HANDLED; 70 } 71 72 static int tve200_display_check(struct drm_simple_display_pipe *pipe, 73 struct drm_plane_state *pstate, 74 struct drm_crtc_state *cstate) 75 { 76 const struct drm_display_mode *mode = &cstate->mode; 77 struct drm_framebuffer *old_fb = pipe->plane.state->fb; 78 struct drm_framebuffer *fb = pstate->fb; 79 80 /* 81 * We support these specific resolutions and nothing else. 82 */ 83 if (!(mode->hdisplay == 352 && mode->vdisplay == 240) && /* SIF(525) */ 84 !(mode->hdisplay == 352 && mode->vdisplay == 288) && /* CIF(625) */ 85 !(mode->hdisplay == 640 && mode->vdisplay == 480) && /* VGA */ 86 !(mode->hdisplay == 720 && mode->vdisplay == 480) && /* D1 */ 87 !(mode->hdisplay == 720 && mode->vdisplay == 576)) { /* D1 */ 88 DRM_DEBUG_KMS("unsupported display mode (%u x %u)\n", 89 mode->hdisplay, mode->vdisplay); 90 return -EINVAL; 91 } 92 93 if (fb) { 94 u32 offset = drm_fb_cma_get_gem_addr(fb, pstate, 0); 95 96 /* FB base address must be dword aligned. */ 97 if (offset & 3) { 98 DRM_DEBUG_KMS("FB not 32-bit aligned\n"); 99 return -EINVAL; 100 } 101 102 /* 103 * There's no pitch register, the mode's hdisplay 104 * controls this. 105 */ 106 if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0]) { 107 DRM_DEBUG_KMS("can't handle pitches\n"); 108 return -EINVAL; 109 } 110 111 /* 112 * We can't change the FB format in a flicker-free 113 * manner (and only update it during CRTC enable). 114 */ 115 if (old_fb && old_fb->format != fb->format) 116 cstate->mode_changed = true; 117 } 118 119 return 0; 120 } 121 122 static void tve200_display_enable(struct drm_simple_display_pipe *pipe, 123 struct drm_crtc_state *cstate) 124 { 125 struct drm_crtc *crtc = &pipe->crtc; 126 struct drm_plane *plane = &pipe->plane; 127 struct drm_device *drm = crtc->dev; 128 struct tve200_drm_dev_private *priv = drm->dev_private; 129 const struct drm_display_mode *mode = &cstate->mode; 130 struct drm_framebuffer *fb = plane->state->fb; 131 struct drm_connector *connector = priv->connector; 132 u32 format = fb->format->format; 133 u32 ctrl1 = 0; 134 135 clk_prepare_enable(priv->clk); 136 137 /* Function 1 */ 138 ctrl1 |= TVE200_CTRL_CSMODE; 139 /* Interlace mode for CCIR656: parameterize? */ 140 ctrl1 |= TVE200_CTRL_NONINTERLACE; 141 /* 32 words per burst */ 142 ctrl1 |= TVE200_CTRL_BURST_32_WORDS; 143 /* 16 retries */ 144 ctrl1 |= TVE200_CTRL_RETRYCNT_16; 145 /* NTSC mode: parametrize? */ 146 ctrl1 |= TVE200_CTRL_NTSC; 147 148 /* Vsync IRQ at start of Vsync at first */ 149 ctrl1 |= TVE200_VSTSTYPE_VSYNC; 150 151 if (connector->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE) 152 ctrl1 |= TVE200_CTRL_TVCLKP; 153 154 if ((mode->hdisplay == 352 && mode->vdisplay == 240) || /* SIF(525) */ 155 (mode->hdisplay == 352 && mode->vdisplay == 288)) { /* CIF(625) */ 156 ctrl1 |= TVE200_CTRL_IPRESOL_CIF; 157 dev_info(drm->dev, "CIF mode\n"); 158 } else if (mode->hdisplay == 640 && mode->vdisplay == 480) { 159 ctrl1 |= TVE200_CTRL_IPRESOL_VGA; 160 dev_info(drm->dev, "VGA mode\n"); 161 } else if ((mode->hdisplay == 720 && mode->vdisplay == 480) || 162 (mode->hdisplay == 720 && mode->vdisplay == 576)) { 163 ctrl1 |= TVE200_CTRL_IPRESOL_D1; 164 dev_info(drm->dev, "D1 mode\n"); 165 } 166 167 if (format & DRM_FORMAT_BIG_ENDIAN) { 168 ctrl1 |= TVE200_CTRL_BBBP; 169 format &= ~DRM_FORMAT_BIG_ENDIAN; 170 } 171 172 switch (format) { 173 case DRM_FORMAT_XRGB8888: 174 ctrl1 |= TVE200_IPDMOD_RGB888; 175 break; 176 case DRM_FORMAT_RGB565: 177 ctrl1 |= TVE200_IPDMOD_RGB565; 178 break; 179 case DRM_FORMAT_XRGB1555: 180 ctrl1 |= TVE200_IPDMOD_RGB555; 181 break; 182 case DRM_FORMAT_XBGR8888: 183 ctrl1 |= TVE200_IPDMOD_RGB888 | TVE200_BGR; 184 break; 185 case DRM_FORMAT_BGR565: 186 ctrl1 |= TVE200_IPDMOD_RGB565 | TVE200_BGR; 187 break; 188 case DRM_FORMAT_XBGR1555: 189 ctrl1 |= TVE200_IPDMOD_RGB555 | TVE200_BGR; 190 break; 191 case DRM_FORMAT_YUYV: 192 ctrl1 |= TVE200_IPDMOD_YUV422; 193 ctrl1 |= TVE200_CTRL_YCBCRODR_CR0Y1CB0Y0; 194 break; 195 case DRM_FORMAT_YVYU: 196 ctrl1 |= TVE200_IPDMOD_YUV422; 197 ctrl1 |= TVE200_CTRL_YCBCRODR_CB0Y1CR0Y0; 198 break; 199 case DRM_FORMAT_UYVY: 200 ctrl1 |= TVE200_IPDMOD_YUV422; 201 ctrl1 |= TVE200_CTRL_YCBCRODR_Y1CR0Y0CB0; 202 break; 203 case DRM_FORMAT_VYUY: 204 ctrl1 |= TVE200_IPDMOD_YUV422; 205 ctrl1 |= TVE200_CTRL_YCBCRODR_Y1CB0Y0CR0; 206 break; 207 case DRM_FORMAT_YUV420: 208 ctrl1 |= TVE200_CTRL_YUV420; 209 ctrl1 |= TVE200_IPDMOD_YUV420; 210 break; 211 default: 212 dev_err(drm->dev, "Unknown FB format 0x%08x\n", 213 fb->format->format); 214 break; 215 } 216 217 ctrl1 |= TVE200_TVEEN; 218 219 /* Turn it on */ 220 writel(ctrl1, priv->regs + TVE200_CTRL); 221 222 drm_crtc_vblank_on(crtc); 223 } 224 225 static void tve200_display_disable(struct drm_simple_display_pipe *pipe) 226 { 227 struct drm_crtc *crtc = &pipe->crtc; 228 struct drm_device *drm = crtc->dev; 229 struct tve200_drm_dev_private *priv = drm->dev_private; 230 231 drm_crtc_vblank_off(crtc); 232 233 /* Disable and Power Down */ 234 writel(0, priv->regs + TVE200_CTRL); 235 236 clk_disable_unprepare(priv->clk); 237 } 238 239 static void tve200_display_update(struct drm_simple_display_pipe *pipe, 240 struct drm_plane_state *old_pstate) 241 { 242 struct drm_crtc *crtc = &pipe->crtc; 243 struct drm_device *drm = crtc->dev; 244 struct tve200_drm_dev_private *priv = drm->dev_private; 245 struct drm_pending_vblank_event *event = crtc->state->event; 246 struct drm_plane *plane = &pipe->plane; 247 struct drm_plane_state *pstate = plane->state; 248 struct drm_framebuffer *fb = pstate->fb; 249 250 if (fb) { 251 /* For RGB, the Y component is used as base address */ 252 writel(drm_fb_cma_get_gem_addr(fb, pstate, 0), 253 priv->regs + TVE200_Y_FRAME_BASE_ADDR); 254 255 /* For three plane YUV we need two more addresses */ 256 if (fb->format->format == DRM_FORMAT_YUV420) { 257 writel(drm_fb_cma_get_gem_addr(fb, pstate, 1), 258 priv->regs + TVE200_U_FRAME_BASE_ADDR); 259 writel(drm_fb_cma_get_gem_addr(fb, pstate, 2), 260 priv->regs + TVE200_V_FRAME_BASE_ADDR); 261 } 262 } 263 264 if (event) { 265 crtc->state->event = NULL; 266 267 spin_lock_irq(&crtc->dev->event_lock); 268 if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0) 269 drm_crtc_arm_vblank_event(crtc, event); 270 else 271 drm_crtc_send_vblank_event(crtc, event); 272 spin_unlock_irq(&crtc->dev->event_lock); 273 } 274 } 275 276 static int tve200_display_enable_vblank(struct drm_simple_display_pipe *pipe) 277 { 278 struct drm_crtc *crtc = &pipe->crtc; 279 struct drm_device *drm = crtc->dev; 280 struct tve200_drm_dev_private *priv = drm->dev_private; 281 282 writel(TVE200_INT_V_STATUS, priv->regs + TVE200_INT_EN); 283 return 0; 284 } 285 286 static void tve200_display_disable_vblank(struct drm_simple_display_pipe *pipe) 287 { 288 struct drm_crtc *crtc = &pipe->crtc; 289 struct drm_device *drm = crtc->dev; 290 struct tve200_drm_dev_private *priv = drm->dev_private; 291 292 writel(0, priv->regs + TVE200_INT_EN); 293 } 294 295 static int tve200_display_prepare_fb(struct drm_simple_display_pipe *pipe, 296 struct drm_plane_state *plane_state) 297 { 298 return drm_gem_fb_prepare_fb(&pipe->plane, plane_state); 299 } 300 301 static const struct drm_simple_display_pipe_funcs tve200_display_funcs = { 302 .check = tve200_display_check, 303 .enable = tve200_display_enable, 304 .disable = tve200_display_disable, 305 .update = tve200_display_update, 306 .prepare_fb = tve200_display_prepare_fb, 307 .enable_vblank = tve200_display_enable_vblank, 308 .disable_vblank = tve200_display_disable_vblank, 309 }; 310 311 int tve200_display_init(struct drm_device *drm) 312 { 313 struct tve200_drm_dev_private *priv = drm->dev_private; 314 int ret; 315 static const u32 formats[] = { 316 DRM_FORMAT_XRGB8888, 317 DRM_FORMAT_XBGR8888, 318 DRM_FORMAT_RGB565, 319 DRM_FORMAT_BGR565, 320 DRM_FORMAT_XRGB1555, 321 DRM_FORMAT_XBGR1555, 322 /* 323 * The controller actually supports any YCbCr ordering, 324 * for packed YCbCr. This just lists the orderings that 325 * DRM supports. 326 */ 327 DRM_FORMAT_YUYV, 328 DRM_FORMAT_YVYU, 329 DRM_FORMAT_UYVY, 330 DRM_FORMAT_VYUY, 331 /* This uses three planes */ 332 DRM_FORMAT_YUV420, 333 }; 334 335 ret = drm_simple_display_pipe_init(drm, &priv->pipe, 336 &tve200_display_funcs, 337 formats, ARRAY_SIZE(formats), 338 NULL, 339 priv->connector); 340 if (ret) 341 return ret; 342 343 return 0; 344 } 345