1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/of_address.h> 4 #include <linux/pci.h> 5 #include <linux/platform_device.h> 6 7 #include <drm/drm_aperture.h> 8 #include <drm/drm_atomic.h> 9 #include <drm/drm_atomic_state_helper.h> 10 #include <drm/drm_connector.h> 11 #include <drm/drm_damage_helper.h> 12 #include <drm/drm_device.h> 13 #include <drm/drm_drv.h> 14 #include <drm/drm_fb_helper.h> 15 #include <drm/drm_format_helper.h> 16 #include <drm/drm_framebuffer.h> 17 #include <drm/drm_gem_atomic_helper.h> 18 #include <drm/drm_gem_framebuffer_helper.h> 19 #include <drm/drm_gem_shmem_helper.h> 20 #include <drm/drm_managed.h> 21 #include <drm/drm_modeset_helper_vtables.h> 22 #include <drm/drm_plane_helper.h> 23 #include <drm/drm_probe_helper.h> 24 #include <drm/drm_simple_kms_helper.h> 25 26 #define DRIVER_NAME "ofdrm" 27 #define DRIVER_DESC "DRM driver for OF platform devices" 28 #define DRIVER_DATE "20220501" 29 #define DRIVER_MAJOR 1 30 #define DRIVER_MINOR 0 31 32 #define PCI_VENDOR_ID_ATI_R520 0x7100 33 #define PCI_VENDOR_ID_ATI_R600 0x9400 34 35 #define OFDRM_GAMMA_LUT_SIZE 256 36 37 /* Definitions used by the Avivo palette */ 38 #define AVIVO_DC_LUT_RW_SELECT 0x6480 39 #define AVIVO_DC_LUT_RW_MODE 0x6484 40 #define AVIVO_DC_LUT_RW_INDEX 0x6488 41 #define AVIVO_DC_LUT_SEQ_COLOR 0x648c 42 #define AVIVO_DC_LUT_PWL_DATA 0x6490 43 #define AVIVO_DC_LUT_30_COLOR 0x6494 44 #define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498 45 #define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c 46 #define AVIVO_DC_LUT_AUTOFILL 0x64a0 47 #define AVIVO_DC_LUTA_CONTROL 0x64c0 48 #define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4 49 #define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8 50 #define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc 51 #define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0 52 #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 53 #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 54 #define AVIVO_DC_LUTB_CONTROL 0x6cc0 55 #define AVIVO_DC_LUTB_BLACK_OFFSET_BLUE 0x6cc4 56 #define AVIVO_DC_LUTB_BLACK_OFFSET_GREEN 0x6cc8 57 #define AVIVO_DC_LUTB_BLACK_OFFSET_RED 0x6ccc 58 #define AVIVO_DC_LUTB_WHITE_OFFSET_BLUE 0x6cd0 59 #define AVIVO_DC_LUTB_WHITE_OFFSET_GREEN 0x6cd4 60 #define AVIVO_DC_LUTB_WHITE_OFFSET_RED 0x6cd8 61 62 enum ofdrm_model { 63 OFDRM_MODEL_UNKNOWN, 64 OFDRM_MODEL_MACH64, /* ATI Mach64 */ 65 OFDRM_MODEL_RAGE128, /* ATI Rage128 */ 66 OFDRM_MODEL_RAGE_M3A, /* ATI Rage Mobility M3 Head A */ 67 OFDRM_MODEL_RAGE_M3B, /* ATI Rage Mobility M3 Head B */ 68 OFDRM_MODEL_RADEON, /* ATI Radeon */ 69 OFDRM_MODEL_GXT2000, /* IBM GXT2000 */ 70 OFDRM_MODEL_AVIVO, /* ATI R5xx */ 71 OFDRM_MODEL_QEMU, /* QEMU VGA */ 72 }; 73 74 /* 75 * Helpers for display nodes 76 */ 77 78 static int display_get_validated_int(struct drm_device *dev, const char *name, uint32_t value) 79 { 80 if (value > INT_MAX) { 81 drm_err(dev, "invalid framebuffer %s of %u\n", name, value); 82 return -EINVAL; 83 } 84 return (int)value; 85 } 86 87 static int display_get_validated_int0(struct drm_device *dev, const char *name, uint32_t value) 88 { 89 if (!value) { 90 drm_err(dev, "invalid framebuffer %s of %u\n", name, value); 91 return -EINVAL; 92 } 93 return display_get_validated_int(dev, name, value); 94 } 95 96 static const struct drm_format_info *display_get_validated_format(struct drm_device *dev, 97 u32 depth, bool big_endian) 98 { 99 const struct drm_format_info *info; 100 u32 format; 101 102 switch (depth) { 103 case 8: 104 format = drm_mode_legacy_fb_format(8, 8); 105 break; 106 case 15: 107 case 16: 108 format = drm_mode_legacy_fb_format(16, depth); 109 break; 110 case 32: 111 format = drm_mode_legacy_fb_format(32, 24); 112 break; 113 default: 114 drm_err(dev, "unsupported framebuffer depth %u\n", depth); 115 return ERR_PTR(-EINVAL); 116 } 117 118 /* 119 * DRM formats assume little-endian byte order. Update the format 120 * if the scanout buffer uses big-endian ordering. 121 */ 122 if (big_endian) { 123 switch (format) { 124 case DRM_FORMAT_XRGB8888: 125 format = DRM_FORMAT_BGRX8888; 126 break; 127 case DRM_FORMAT_ARGB8888: 128 format = DRM_FORMAT_BGRA8888; 129 break; 130 case DRM_FORMAT_RGB565: 131 format = DRM_FORMAT_RGB565 | DRM_FORMAT_BIG_ENDIAN; 132 break; 133 case DRM_FORMAT_XRGB1555: 134 format = DRM_FORMAT_XRGB1555 | DRM_FORMAT_BIG_ENDIAN; 135 break; 136 default: 137 break; 138 } 139 } 140 141 info = drm_format_info(format); 142 if (!info) { 143 drm_err(dev, "cannot find framebuffer format for depth %u\n", depth); 144 return ERR_PTR(-EINVAL); 145 } 146 147 return info; 148 } 149 150 static int display_read_u32_of(struct drm_device *dev, struct device_node *of_node, 151 const char *name, u32 *value) 152 { 153 int ret = of_property_read_u32(of_node, name, value); 154 155 if (ret) 156 drm_err(dev, "cannot parse framebuffer %s: error %d\n", name, ret); 157 return ret; 158 } 159 160 static bool display_get_big_endian_of(struct drm_device *dev, struct device_node *of_node) 161 { 162 bool big_endian; 163 164 #ifdef __BIG_ENDIAN 165 big_endian = true; 166 if (of_get_property(of_node, "little-endian", NULL)) 167 big_endian = false; 168 #else 169 big_endian = false; 170 if (of_get_property(of_node, "big-endian", NULL)) 171 big_endian = true; 172 #endif 173 174 return big_endian; 175 } 176 177 static int display_get_width_of(struct drm_device *dev, struct device_node *of_node) 178 { 179 u32 width; 180 int ret = display_read_u32_of(dev, of_node, "width", &width); 181 182 if (ret) 183 return ret; 184 return display_get_validated_int0(dev, "width", width); 185 } 186 187 static int display_get_height_of(struct drm_device *dev, struct device_node *of_node) 188 { 189 u32 height; 190 int ret = display_read_u32_of(dev, of_node, "height", &height); 191 192 if (ret) 193 return ret; 194 return display_get_validated_int0(dev, "height", height); 195 } 196 197 static int display_get_depth_of(struct drm_device *dev, struct device_node *of_node) 198 { 199 u32 depth; 200 int ret = display_read_u32_of(dev, of_node, "depth", &depth); 201 202 if (ret) 203 return ret; 204 return display_get_validated_int0(dev, "depth", depth); 205 } 206 207 static int display_get_linebytes_of(struct drm_device *dev, struct device_node *of_node) 208 { 209 u32 linebytes; 210 int ret = display_read_u32_of(dev, of_node, "linebytes", &linebytes); 211 212 if (ret) 213 return ret; 214 return display_get_validated_int(dev, "linebytes", linebytes); 215 } 216 217 static u64 display_get_address_of(struct drm_device *dev, struct device_node *of_node) 218 { 219 u32 address; 220 int ret; 221 222 /* 223 * Not all devices provide an address property, it's not 224 * a bug if this fails. The driver will try to find the 225 * framebuffer base address from the device's memory regions. 226 */ 227 ret = of_property_read_u32(of_node, "address", &address); 228 if (ret) 229 return OF_BAD_ADDR; 230 231 return address; 232 } 233 234 static bool is_avivo(__be32 vendor, __be32 device) 235 { 236 /* This will match most R5xx */ 237 return (vendor == PCI_VENDOR_ID_ATI) && 238 ((device >= PCI_VENDOR_ID_ATI_R520 && device < 0x7800) || 239 (PCI_VENDOR_ID_ATI_R600 >= 0x9400)); 240 } 241 242 static enum ofdrm_model display_get_model_of(struct drm_device *dev, struct device_node *of_node) 243 { 244 enum ofdrm_model model = OFDRM_MODEL_UNKNOWN; 245 246 if (of_node_name_prefix(of_node, "ATY,Rage128")) { 247 model = OFDRM_MODEL_RAGE128; 248 } else if (of_node_name_prefix(of_node, "ATY,RageM3pA") || 249 of_node_name_prefix(of_node, "ATY,RageM3p12A")) { 250 model = OFDRM_MODEL_RAGE_M3A; 251 } else if (of_node_name_prefix(of_node, "ATY,RageM3pB")) { 252 model = OFDRM_MODEL_RAGE_M3B; 253 } else if (of_node_name_prefix(of_node, "ATY,Rage6")) { 254 model = OFDRM_MODEL_RADEON; 255 } else if (of_node_name_prefix(of_node, "ATY,")) { 256 return OFDRM_MODEL_MACH64; 257 } else if (of_device_is_compatible(of_node, "pci1014,b7") || 258 of_device_is_compatible(of_node, "pci1014,21c")) { 259 model = OFDRM_MODEL_GXT2000; 260 } else if (of_node_name_prefix(of_node, "vga,Display-")) { 261 struct device_node *of_parent; 262 const __be32 *vendor_p, *device_p; 263 264 /* Look for AVIVO initialized by SLOF */ 265 of_parent = of_get_parent(of_node); 266 vendor_p = of_get_property(of_parent, "vendor-id", NULL); 267 device_p = of_get_property(of_parent, "device-id", NULL); 268 if (vendor_p && device_p && is_avivo(*vendor_p, *device_p)) 269 model = OFDRM_MODEL_AVIVO; 270 of_node_put(of_parent); 271 } else if (of_device_is_compatible(of_node, "qemu,std-vga")) { 272 model = OFDRM_MODEL_QEMU; 273 } 274 275 return model; 276 } 277 278 /* 279 * Open Firmware display device 280 */ 281 282 struct ofdrm_device; 283 284 struct ofdrm_device_funcs { 285 void __iomem *(*cmap_ioremap)(struct ofdrm_device *odev, 286 struct device_node *of_node, 287 u64 fb_bas); 288 void (*cmap_write)(struct ofdrm_device *odev, unsigned char index, 289 unsigned char r, unsigned char g, unsigned char b); 290 }; 291 292 struct ofdrm_device { 293 struct drm_device dev; 294 struct platform_device *pdev; 295 296 const struct ofdrm_device_funcs *funcs; 297 298 /* firmware-buffer settings */ 299 struct iosys_map screen_base; 300 struct drm_display_mode mode; 301 const struct drm_format_info *format; 302 unsigned int pitch; 303 304 /* colormap */ 305 void __iomem *cmap_base; 306 307 /* modesetting */ 308 uint32_t formats[8]; 309 struct drm_plane primary_plane; 310 struct drm_crtc crtc; 311 struct drm_encoder encoder; 312 struct drm_connector connector; 313 }; 314 315 static struct ofdrm_device *ofdrm_device_of_dev(struct drm_device *dev) 316 { 317 return container_of(dev, struct ofdrm_device, dev); 318 } 319 320 /* 321 * Hardware 322 */ 323 324 #if defined(CONFIG_PCI) 325 static struct pci_dev *display_get_pci_dev_of(struct drm_device *dev, struct device_node *of_node) 326 { 327 const __be32 *vendor_p, *device_p; 328 u32 vendor, device; 329 struct pci_dev *pcidev; 330 331 vendor_p = of_get_property(of_node, "vendor-id", NULL); 332 if (!vendor_p) 333 return ERR_PTR(-ENODEV); 334 vendor = be32_to_cpup(vendor_p); 335 336 device_p = of_get_property(of_node, "device-id", NULL); 337 if (!device_p) 338 return ERR_PTR(-ENODEV); 339 device = be32_to_cpup(device_p); 340 341 pcidev = pci_get_device(vendor, device, NULL); 342 if (!pcidev) 343 return ERR_PTR(-ENODEV); 344 345 return pcidev; 346 } 347 348 static void ofdrm_pci_release(void *data) 349 { 350 struct pci_dev *pcidev = data; 351 352 pci_disable_device(pcidev); 353 } 354 355 static int ofdrm_device_init_pci(struct ofdrm_device *odev) 356 { 357 struct drm_device *dev = &odev->dev; 358 struct platform_device *pdev = to_platform_device(dev->dev); 359 struct device_node *of_node = pdev->dev.of_node; 360 struct pci_dev *pcidev; 361 int ret; 362 363 /* 364 * Never use pcim_ or other managed helpers on the returned PCI 365 * device. Otherwise, probing the native driver will fail for 366 * resource conflicts. PCI-device management has to be tied to 367 * the lifetime of the platform device until the native driver 368 * takes over. 369 */ 370 pcidev = display_get_pci_dev_of(dev, of_node); 371 if (IS_ERR(pcidev)) 372 return 0; /* no PCI device found; ignore the error */ 373 374 ret = pci_enable_device(pcidev); 375 if (ret) { 376 drm_err(dev, "pci_enable_device(%s) failed: %d\n", 377 dev_name(&pcidev->dev), ret); 378 return ret; 379 } 380 ret = devm_add_action_or_reset(&pdev->dev, ofdrm_pci_release, pcidev); 381 if (ret) 382 return ret; 383 384 return 0; 385 } 386 #else 387 static int ofdrm_device_init_pci(struct ofdrm_device *odev) 388 { 389 return 0; 390 } 391 #endif 392 393 /* 394 * OF display settings 395 */ 396 397 static struct resource *ofdrm_find_fb_resource(struct ofdrm_device *odev, 398 struct resource *fb_res) 399 { 400 struct platform_device *pdev = to_platform_device(odev->dev.dev); 401 struct resource *res, *max_res = NULL; 402 u32 i; 403 404 for (i = 0; pdev->num_resources; ++i) { 405 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 406 if (!res) 407 break; /* all resources processed */ 408 if (resource_size(res) < resource_size(fb_res)) 409 continue; /* resource too small */ 410 if (fb_res->start && resource_contains(res, fb_res)) 411 return res; /* resource contains framebuffer */ 412 if (!max_res || resource_size(res) > resource_size(max_res)) 413 max_res = res; /* store largest resource as fallback */ 414 } 415 416 return max_res; 417 } 418 419 /* 420 * Colormap / Palette 421 */ 422 423 static void __iomem *get_cmap_address_of(struct ofdrm_device *odev, struct device_node *of_node, 424 int bar_no, unsigned long offset, unsigned long size) 425 { 426 struct drm_device *dev = &odev->dev; 427 const __be32 *addr_p; 428 u64 max_size, address; 429 unsigned int flags; 430 void __iomem *mem; 431 432 addr_p = of_get_pci_address(of_node, bar_no, &max_size, &flags); 433 if (!addr_p) 434 addr_p = of_get_address(of_node, bar_no, &max_size, &flags); 435 if (!addr_p) 436 return ERR_PTR(-ENODEV); 437 438 if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0) 439 return ERR_PTR(-ENODEV); 440 441 if ((offset + size) >= max_size) 442 return ERR_PTR(-ENODEV); 443 444 address = of_translate_address(of_node, addr_p); 445 if (address == OF_BAD_ADDR) 446 return ERR_PTR(-ENODEV); 447 448 mem = devm_ioremap(dev->dev, address + offset, size); 449 if (!mem) 450 return ERR_PTR(-ENOMEM); 451 452 return mem; 453 } 454 455 static void __iomem *ofdrm_mach64_cmap_ioremap(struct ofdrm_device *odev, 456 struct device_node *of_node, 457 u64 fb_base) 458 { 459 struct drm_device *dev = &odev->dev; 460 u64 address; 461 void __iomem *cmap_base; 462 463 address = fb_base & 0xff000000ul; 464 address += 0x7ff000; 465 466 cmap_base = devm_ioremap(dev->dev, address, 0x1000); 467 if (!cmap_base) 468 return ERR_PTR(-ENOMEM); 469 470 return cmap_base; 471 } 472 473 static void ofdrm_mach64_cmap_write(struct ofdrm_device *odev, unsigned char index, 474 unsigned char r, unsigned char g, unsigned char b) 475 { 476 void __iomem *addr = odev->cmap_base + 0xcc0; 477 void __iomem *data = odev->cmap_base + 0xcc0 + 1; 478 479 writeb(index, addr); 480 writeb(r, data); 481 writeb(g, data); 482 writeb(b, data); 483 } 484 485 static void __iomem *ofdrm_rage128_cmap_ioremap(struct ofdrm_device *odev, 486 struct device_node *of_node, 487 u64 fb_base) 488 { 489 return get_cmap_address_of(odev, of_node, 2, 0, 0x1fff); 490 } 491 492 static void ofdrm_rage128_cmap_write(struct ofdrm_device *odev, unsigned char index, 493 unsigned char r, unsigned char g, unsigned char b) 494 { 495 void __iomem *addr = odev->cmap_base + 0xb0; 496 void __iomem *data = odev->cmap_base + 0xb4; 497 u32 color = (r << 16) | (g << 8) | b; 498 499 writeb(index, addr); 500 writel(color, data); 501 } 502 503 static void __iomem *ofdrm_rage_m3a_cmap_ioremap(struct ofdrm_device *odev, 504 struct device_node *of_node, 505 u64 fb_base) 506 { 507 return get_cmap_address_of(odev, of_node, 2, 0, 0x1fff); 508 } 509 510 static void ofdrm_rage_m3a_cmap_write(struct ofdrm_device *odev, unsigned char index, 511 unsigned char r, unsigned char g, unsigned char b) 512 { 513 void __iomem *dac_ctl = odev->cmap_base + 0x58; 514 void __iomem *addr = odev->cmap_base + 0xb0; 515 void __iomem *data = odev->cmap_base + 0xb4; 516 u32 color = (r << 16) | (g << 8) | b; 517 u32 val; 518 519 /* Clear PALETTE_ACCESS_CNTL in DAC_CNTL */ 520 val = readl(dac_ctl); 521 val &= ~0x20; 522 writel(val, dac_ctl); 523 524 /* Set color at palette index */ 525 writeb(index, addr); 526 writel(color, data); 527 } 528 529 static void __iomem *ofdrm_rage_m3b_cmap_ioremap(struct ofdrm_device *odev, 530 struct device_node *of_node, 531 u64 fb_base) 532 { 533 return get_cmap_address_of(odev, of_node, 2, 0, 0x1fff); 534 } 535 536 static void ofdrm_rage_m3b_cmap_write(struct ofdrm_device *odev, unsigned char index, 537 unsigned char r, unsigned char g, unsigned char b) 538 { 539 void __iomem *dac_ctl = odev->cmap_base + 0x58; 540 void __iomem *addr = odev->cmap_base + 0xb0; 541 void __iomem *data = odev->cmap_base + 0xb4; 542 u32 color = (r << 16) | (g << 8) | b; 543 u32 val; 544 545 /* Set PALETTE_ACCESS_CNTL in DAC_CNTL */ 546 val = readl(dac_ctl); 547 val |= 0x20; 548 writel(val, dac_ctl); 549 550 /* Set color at palette index */ 551 writeb(index, addr); 552 writel(color, data); 553 } 554 555 static void __iomem *ofdrm_radeon_cmap_ioremap(struct ofdrm_device *odev, 556 struct device_node *of_node, 557 u64 fb_base) 558 { 559 return get_cmap_address_of(odev, of_node, 1, 0, 0x1fff); 560 } 561 562 static void __iomem *ofdrm_gxt2000_cmap_ioremap(struct ofdrm_device *odev, 563 struct device_node *of_node, 564 u64 fb_base) 565 { 566 return get_cmap_address_of(odev, of_node, 0, 0x6000, 0x1000); 567 } 568 569 static void ofdrm_gxt2000_cmap_write(struct ofdrm_device *odev, unsigned char index, 570 unsigned char r, unsigned char g, unsigned char b) 571 { 572 void __iomem *data = ((unsigned int __iomem *)odev->cmap_base) + index; 573 u32 color = (r << 16) | (g << 8) | b; 574 575 writel(color, data); 576 } 577 578 static void __iomem *ofdrm_avivo_cmap_ioremap(struct ofdrm_device *odev, 579 struct device_node *of_node, 580 u64 fb_base) 581 { 582 struct device_node *of_parent; 583 void __iomem *cmap_base; 584 585 of_parent = of_get_parent(of_node); 586 cmap_base = get_cmap_address_of(odev, of_parent, 0, 0, 0x10000); 587 of_node_put(of_parent); 588 589 return cmap_base; 590 } 591 592 static void ofdrm_avivo_cmap_write(struct ofdrm_device *odev, unsigned char index, 593 unsigned char r, unsigned char g, unsigned char b) 594 { 595 void __iomem *lutsel = odev->cmap_base + AVIVO_DC_LUT_RW_SELECT; 596 void __iomem *addr = odev->cmap_base + AVIVO_DC_LUT_RW_INDEX; 597 void __iomem *data = odev->cmap_base + AVIVO_DC_LUT_30_COLOR; 598 u32 color = (r << 22) | (g << 12) | (b << 2); 599 600 /* Write to both LUTs for now */ 601 602 writel(1, lutsel); 603 writeb(index, addr); 604 writel(color, data); 605 606 writel(0, lutsel); 607 writeb(index, addr); 608 writel(color, data); 609 } 610 611 static void __iomem *ofdrm_qemu_cmap_ioremap(struct ofdrm_device *odev, 612 struct device_node *of_node, 613 u64 fb_base) 614 { 615 static const __be32 io_of_addr[3] = { 616 cpu_to_be32(0x01000000), 617 cpu_to_be32(0x00), 618 cpu_to_be32(0x00), 619 }; 620 621 struct drm_device *dev = &odev->dev; 622 u64 address; 623 void __iomem *cmap_base; 624 625 address = of_translate_address(of_node, io_of_addr); 626 if (address == OF_BAD_ADDR) 627 return ERR_PTR(-ENODEV); 628 629 cmap_base = devm_ioremap(dev->dev, address + 0x3c8, 2); 630 if (!cmap_base) 631 return ERR_PTR(-ENOMEM); 632 633 return cmap_base; 634 } 635 636 static void ofdrm_qemu_cmap_write(struct ofdrm_device *odev, unsigned char index, 637 unsigned char r, unsigned char g, unsigned char b) 638 { 639 void __iomem *addr = odev->cmap_base; 640 void __iomem *data = odev->cmap_base + 1; 641 642 writeb(index, addr); 643 writeb(r, data); 644 writeb(g, data); 645 writeb(b, data); 646 } 647 648 static void ofdrm_device_set_gamma_linear(struct ofdrm_device *odev, 649 const struct drm_format_info *format) 650 { 651 struct drm_device *dev = &odev->dev; 652 int i; 653 654 switch (format->format) { 655 case DRM_FORMAT_RGB565: 656 case DRM_FORMAT_RGB565 | DRM_FORMAT_BIG_ENDIAN: 657 /* Use better interpolation, to take 32 values from 0 to 255 */ 658 for (i = 0; i < OFDRM_GAMMA_LUT_SIZE / 8; i++) { 659 unsigned char r = i * 8 + i / 4; 660 unsigned char g = i * 4 + i / 16; 661 unsigned char b = i * 8 + i / 4; 662 663 odev->funcs->cmap_write(odev, i, r, g, b); 664 } 665 /* Green has one more bit, so add padding with 0 for red and blue. */ 666 for (i = OFDRM_GAMMA_LUT_SIZE / 8; i < OFDRM_GAMMA_LUT_SIZE / 4; i++) { 667 unsigned char r = 0; 668 unsigned char g = i * 4 + i / 16; 669 unsigned char b = 0; 670 671 odev->funcs->cmap_write(odev, i, r, g, b); 672 } 673 break; 674 case DRM_FORMAT_XRGB8888: 675 case DRM_FORMAT_BGRX8888: 676 for (i = 0; i < OFDRM_GAMMA_LUT_SIZE; i++) 677 odev->funcs->cmap_write(odev, i, i, i, i); 678 break; 679 default: 680 drm_warn_once(dev, "Unsupported format %p4cc for gamma correction\n", 681 &format->format); 682 break; 683 } 684 } 685 686 static void ofdrm_device_set_gamma(struct ofdrm_device *odev, 687 const struct drm_format_info *format, 688 struct drm_color_lut *lut) 689 { 690 struct drm_device *dev = &odev->dev; 691 int i; 692 693 switch (format->format) { 694 case DRM_FORMAT_RGB565: 695 case DRM_FORMAT_RGB565 | DRM_FORMAT_BIG_ENDIAN: 696 /* Use better interpolation, to take 32 values from lut[0] to lut[255] */ 697 for (i = 0; i < OFDRM_GAMMA_LUT_SIZE / 8; i++) { 698 unsigned char r = lut[i * 8 + i / 4].red >> 8; 699 unsigned char g = lut[i * 4 + i / 16].green >> 8; 700 unsigned char b = lut[i * 8 + i / 4].blue >> 8; 701 702 odev->funcs->cmap_write(odev, i, r, g, b); 703 } 704 /* Green has one more bit, so add padding with 0 for red and blue. */ 705 for (i = OFDRM_GAMMA_LUT_SIZE / 8; i < OFDRM_GAMMA_LUT_SIZE / 4; i++) { 706 unsigned char r = 0; 707 unsigned char g = lut[i * 4 + i / 16].green >> 8; 708 unsigned char b = 0; 709 710 odev->funcs->cmap_write(odev, i, r, g, b); 711 } 712 break; 713 case DRM_FORMAT_XRGB8888: 714 case DRM_FORMAT_BGRX8888: 715 for (i = 0; i < OFDRM_GAMMA_LUT_SIZE; i++) { 716 unsigned char r = lut[i].red >> 8; 717 unsigned char g = lut[i].green >> 8; 718 unsigned char b = lut[i].blue >> 8; 719 720 odev->funcs->cmap_write(odev, i, r, g, b); 721 } 722 break; 723 default: 724 drm_warn_once(dev, "Unsupported format %p4cc for gamma correction\n", 725 &format->format); 726 break; 727 } 728 } 729 730 /* 731 * Modesetting 732 */ 733 734 struct ofdrm_crtc_state { 735 struct drm_crtc_state base; 736 737 /* Primary-plane format; required for color mgmt. */ 738 const struct drm_format_info *format; 739 }; 740 741 static struct ofdrm_crtc_state *to_ofdrm_crtc_state(struct drm_crtc_state *base) 742 { 743 return container_of(base, struct ofdrm_crtc_state, base); 744 } 745 746 static void ofdrm_crtc_state_destroy(struct ofdrm_crtc_state *ofdrm_crtc_state) 747 { 748 __drm_atomic_helper_crtc_destroy_state(&ofdrm_crtc_state->base); 749 kfree(ofdrm_crtc_state); 750 } 751 752 /* 753 * Support all formats of OF display and maybe more; in order 754 * of preference. The display's update function will do any 755 * conversion necessary. 756 * 757 * TODO: Add blit helpers for remaining formats and uncomment 758 * constants. 759 */ 760 static const uint32_t ofdrm_primary_plane_formats[] = { 761 DRM_FORMAT_XRGB8888, 762 DRM_FORMAT_RGB565, 763 //DRM_FORMAT_XRGB1555, 764 //DRM_FORMAT_C8, 765 /* Big-endian formats below */ 766 DRM_FORMAT_BGRX8888, 767 DRM_FORMAT_RGB565 | DRM_FORMAT_BIG_ENDIAN, 768 }; 769 770 static const uint64_t ofdrm_primary_plane_format_modifiers[] = { 771 DRM_FORMAT_MOD_LINEAR, 772 DRM_FORMAT_MOD_INVALID 773 }; 774 775 static int ofdrm_primary_plane_helper_atomic_check(struct drm_plane *plane, 776 struct drm_atomic_state *new_state) 777 { 778 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(new_state, plane); 779 struct drm_framebuffer *new_fb = new_plane_state->fb; 780 struct drm_crtc *new_crtc = new_plane_state->crtc; 781 struct drm_crtc_state *new_crtc_state = NULL; 782 struct ofdrm_crtc_state *new_ofdrm_crtc_state; 783 int ret; 784 785 if (new_crtc) 786 new_crtc_state = drm_atomic_get_new_crtc_state(new_state, new_plane_state->crtc); 787 788 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, 789 DRM_PLANE_NO_SCALING, 790 DRM_PLANE_NO_SCALING, 791 false, false); 792 if (ret) 793 return ret; 794 else if (!new_plane_state->visible) 795 return 0; 796 797 new_crtc_state = drm_atomic_get_new_crtc_state(new_state, new_plane_state->crtc); 798 799 new_ofdrm_crtc_state = to_ofdrm_crtc_state(new_crtc_state); 800 new_ofdrm_crtc_state->format = new_fb->format; 801 802 return 0; 803 } 804 805 static void ofdrm_primary_plane_helper_atomic_update(struct drm_plane *plane, 806 struct drm_atomic_state *state) 807 { 808 struct drm_device *dev = plane->dev; 809 struct ofdrm_device *odev = ofdrm_device_of_dev(dev); 810 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 811 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 812 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 813 struct drm_framebuffer *fb = plane_state->fb; 814 unsigned int dst_pitch = odev->pitch; 815 const struct drm_format_info *dst_format = odev->format; 816 struct drm_atomic_helper_damage_iter iter; 817 struct drm_rect damage; 818 int ret, idx; 819 820 ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE); 821 if (ret) 822 return; 823 824 if (!drm_dev_enter(dev, &idx)) 825 goto out_drm_gem_fb_end_cpu_access; 826 827 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 828 drm_atomic_for_each_plane_damage(&iter, &damage) { 829 struct iosys_map dst = odev->screen_base; 830 struct drm_rect dst_clip = plane_state->dst; 831 832 if (!drm_rect_intersect(&dst_clip, &damage)) 833 continue; 834 835 iosys_map_incr(&dst, drm_fb_clip_offset(dst_pitch, dst_format, &dst_clip)); 836 drm_fb_blit(&dst, &dst_pitch, dst_format->format, shadow_plane_state->data, fb, 837 &damage); 838 } 839 840 drm_dev_exit(idx); 841 out_drm_gem_fb_end_cpu_access: 842 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 843 } 844 845 static void ofdrm_primary_plane_helper_atomic_disable(struct drm_plane *plane, 846 struct drm_atomic_state *state) 847 { 848 struct drm_device *dev = plane->dev; 849 struct ofdrm_device *odev = ofdrm_device_of_dev(dev); 850 struct iosys_map dst = odev->screen_base; 851 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 852 void __iomem *dst_vmap = dst.vaddr_iomem; /* TODO: Use mapping abstraction */ 853 unsigned int dst_pitch = odev->pitch; 854 const struct drm_format_info *dst_format = odev->format; 855 struct drm_rect dst_clip; 856 unsigned long lines, linepixels, i; 857 int idx; 858 859 drm_rect_init(&dst_clip, 860 plane_state->src_x >> 16, plane_state->src_y >> 16, 861 plane_state->src_w >> 16, plane_state->src_h >> 16); 862 863 lines = drm_rect_height(&dst_clip); 864 linepixels = drm_rect_width(&dst_clip); 865 866 if (!drm_dev_enter(dev, &idx)) 867 return; 868 869 /* Clear buffer to black if disabled */ 870 dst_vmap += drm_fb_clip_offset(dst_pitch, dst_format, &dst_clip); 871 for (i = 0; i < lines; ++i) { 872 memset_io(dst_vmap, 0, linepixels * dst_format->cpp[0]); 873 dst_vmap += dst_pitch; 874 } 875 876 drm_dev_exit(idx); 877 } 878 879 static const struct drm_plane_helper_funcs ofdrm_primary_plane_helper_funcs = { 880 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 881 .atomic_check = ofdrm_primary_plane_helper_atomic_check, 882 .atomic_update = ofdrm_primary_plane_helper_atomic_update, 883 .atomic_disable = ofdrm_primary_plane_helper_atomic_disable, 884 }; 885 886 static const struct drm_plane_funcs ofdrm_primary_plane_funcs = { 887 .update_plane = drm_atomic_helper_update_plane, 888 .disable_plane = drm_atomic_helper_disable_plane, 889 .destroy = drm_plane_cleanup, 890 DRM_GEM_SHADOW_PLANE_FUNCS, 891 }; 892 893 static enum drm_mode_status ofdrm_crtc_helper_mode_valid(struct drm_crtc *crtc, 894 const struct drm_display_mode *mode) 895 { 896 struct ofdrm_device *odev = ofdrm_device_of_dev(crtc->dev); 897 898 return drm_crtc_helper_mode_valid_fixed(crtc, mode, &odev->mode); 899 } 900 901 static int ofdrm_crtc_helper_atomic_check(struct drm_crtc *crtc, 902 struct drm_atomic_state *new_state) 903 { 904 static const size_t gamma_lut_length = OFDRM_GAMMA_LUT_SIZE * sizeof(struct drm_color_lut); 905 906 struct drm_device *dev = crtc->dev; 907 struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(new_state, crtc); 908 int ret; 909 910 if (!new_crtc_state->enable) 911 return 0; 912 913 ret = drm_atomic_helper_check_crtc_primary_plane(new_crtc_state); 914 if (ret) 915 return ret; 916 917 if (new_crtc_state->color_mgmt_changed) { 918 struct drm_property_blob *gamma_lut = new_crtc_state->gamma_lut; 919 920 if (gamma_lut && (gamma_lut->length != gamma_lut_length)) { 921 drm_dbg(dev, "Incorrect gamma_lut length %zu\n", gamma_lut->length); 922 return -EINVAL; 923 } 924 } 925 926 return 0; 927 } 928 929 static void ofdrm_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state) 930 { 931 struct ofdrm_device *odev = ofdrm_device_of_dev(crtc->dev); 932 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 933 struct ofdrm_crtc_state *ofdrm_crtc_state = to_ofdrm_crtc_state(crtc_state); 934 935 if (crtc_state->enable && crtc_state->color_mgmt_changed) { 936 const struct drm_format_info *format = ofdrm_crtc_state->format; 937 938 if (crtc_state->gamma_lut) 939 ofdrm_device_set_gamma(odev, format, crtc_state->gamma_lut->data); 940 else 941 ofdrm_device_set_gamma_linear(odev, format); 942 } 943 } 944 945 /* 946 * The CRTC is always enabled. Screen updates are performed by 947 * the primary plane's atomic_update function. Disabling clears 948 * the screen in the primary plane's atomic_disable function. 949 */ 950 static const struct drm_crtc_helper_funcs ofdrm_crtc_helper_funcs = { 951 .mode_valid = ofdrm_crtc_helper_mode_valid, 952 .atomic_check = ofdrm_crtc_helper_atomic_check, 953 .atomic_flush = ofdrm_crtc_helper_atomic_flush, 954 }; 955 956 static void ofdrm_crtc_reset(struct drm_crtc *crtc) 957 { 958 struct ofdrm_crtc_state *ofdrm_crtc_state = 959 kzalloc(sizeof(*ofdrm_crtc_state), GFP_KERNEL); 960 961 if (crtc->state) 962 ofdrm_crtc_state_destroy(to_ofdrm_crtc_state(crtc->state)); 963 964 if (ofdrm_crtc_state) 965 __drm_atomic_helper_crtc_reset(crtc, &ofdrm_crtc_state->base); 966 else 967 __drm_atomic_helper_crtc_reset(crtc, NULL); 968 } 969 970 static struct drm_crtc_state *ofdrm_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 971 { 972 struct drm_device *dev = crtc->dev; 973 struct drm_crtc_state *crtc_state = crtc->state; 974 struct ofdrm_crtc_state *new_ofdrm_crtc_state; 975 struct ofdrm_crtc_state *ofdrm_crtc_state; 976 977 if (drm_WARN_ON(dev, !crtc_state)) 978 return NULL; 979 980 new_ofdrm_crtc_state = kzalloc(sizeof(*new_ofdrm_crtc_state), GFP_KERNEL); 981 if (!new_ofdrm_crtc_state) 982 return NULL; 983 984 ofdrm_crtc_state = to_ofdrm_crtc_state(crtc_state); 985 986 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_ofdrm_crtc_state->base); 987 new_ofdrm_crtc_state->format = ofdrm_crtc_state->format; 988 989 return &new_ofdrm_crtc_state->base; 990 } 991 992 static void ofdrm_crtc_atomic_destroy_state(struct drm_crtc *crtc, 993 struct drm_crtc_state *crtc_state) 994 { 995 ofdrm_crtc_state_destroy(to_ofdrm_crtc_state(crtc_state)); 996 } 997 998 static const struct drm_crtc_funcs ofdrm_crtc_funcs = { 999 .reset = ofdrm_crtc_reset, 1000 .destroy = drm_crtc_cleanup, 1001 .set_config = drm_atomic_helper_set_config, 1002 .page_flip = drm_atomic_helper_page_flip, 1003 .atomic_duplicate_state = ofdrm_crtc_atomic_duplicate_state, 1004 .atomic_destroy_state = ofdrm_crtc_atomic_destroy_state, 1005 }; 1006 1007 static int ofdrm_connector_helper_get_modes(struct drm_connector *connector) 1008 { 1009 struct ofdrm_device *odev = ofdrm_device_of_dev(connector->dev); 1010 1011 return drm_connector_helper_get_modes_fixed(connector, &odev->mode); 1012 } 1013 1014 static const struct drm_connector_helper_funcs ofdrm_connector_helper_funcs = { 1015 .get_modes = ofdrm_connector_helper_get_modes, 1016 }; 1017 1018 static const struct drm_connector_funcs ofdrm_connector_funcs = { 1019 .reset = drm_atomic_helper_connector_reset, 1020 .fill_modes = drm_helper_probe_single_connector_modes, 1021 .destroy = drm_connector_cleanup, 1022 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1023 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1024 }; 1025 1026 static const struct drm_mode_config_funcs ofdrm_mode_config_funcs = { 1027 .fb_create = drm_gem_fb_create_with_dirty, 1028 .atomic_check = drm_atomic_helper_check, 1029 .atomic_commit = drm_atomic_helper_commit, 1030 }; 1031 1032 /* 1033 * Init / Cleanup 1034 */ 1035 1036 static const struct ofdrm_device_funcs ofdrm_unknown_device_funcs = { 1037 }; 1038 1039 static const struct ofdrm_device_funcs ofdrm_mach64_device_funcs = { 1040 .cmap_ioremap = ofdrm_mach64_cmap_ioremap, 1041 .cmap_write = ofdrm_mach64_cmap_write, 1042 }; 1043 1044 static const struct ofdrm_device_funcs ofdrm_rage128_device_funcs = { 1045 .cmap_ioremap = ofdrm_rage128_cmap_ioremap, 1046 .cmap_write = ofdrm_rage128_cmap_write, 1047 }; 1048 1049 static const struct ofdrm_device_funcs ofdrm_rage_m3a_device_funcs = { 1050 .cmap_ioremap = ofdrm_rage_m3a_cmap_ioremap, 1051 .cmap_write = ofdrm_rage_m3a_cmap_write, 1052 }; 1053 1054 static const struct ofdrm_device_funcs ofdrm_rage_m3b_device_funcs = { 1055 .cmap_ioremap = ofdrm_rage_m3b_cmap_ioremap, 1056 .cmap_write = ofdrm_rage_m3b_cmap_write, 1057 }; 1058 1059 static const struct ofdrm_device_funcs ofdrm_radeon_device_funcs = { 1060 .cmap_ioremap = ofdrm_radeon_cmap_ioremap, 1061 .cmap_write = ofdrm_rage128_cmap_write, /* same as Rage128 */ 1062 }; 1063 1064 static const struct ofdrm_device_funcs ofdrm_gxt2000_device_funcs = { 1065 .cmap_ioremap = ofdrm_gxt2000_cmap_ioremap, 1066 .cmap_write = ofdrm_gxt2000_cmap_write, 1067 }; 1068 1069 static const struct ofdrm_device_funcs ofdrm_avivo_device_funcs = { 1070 .cmap_ioremap = ofdrm_avivo_cmap_ioremap, 1071 .cmap_write = ofdrm_avivo_cmap_write, 1072 }; 1073 1074 static const struct ofdrm_device_funcs ofdrm_qemu_device_funcs = { 1075 .cmap_ioremap = ofdrm_qemu_cmap_ioremap, 1076 .cmap_write = ofdrm_qemu_cmap_write, 1077 }; 1078 1079 static struct drm_display_mode ofdrm_mode(unsigned int width, unsigned int height) 1080 { 1081 /* 1082 * Assume a monitor resolution of 96 dpi to 1083 * get a somewhat reasonable screen size. 1084 */ 1085 const struct drm_display_mode mode = { 1086 DRM_MODE_INIT(60, width, height, 1087 DRM_MODE_RES_MM(width, 96ul), 1088 DRM_MODE_RES_MM(height, 96ul)) 1089 }; 1090 1091 return mode; 1092 } 1093 1094 static struct ofdrm_device *ofdrm_device_create(struct drm_driver *drv, 1095 struct platform_device *pdev) 1096 { 1097 struct device_node *of_node = pdev->dev.of_node; 1098 struct ofdrm_device *odev; 1099 struct drm_device *dev; 1100 enum ofdrm_model model; 1101 bool big_endian; 1102 int width, height, depth, linebytes; 1103 const struct drm_format_info *format; 1104 u64 address; 1105 resource_size_t fb_size, fb_base, fb_pgbase, fb_pgsize; 1106 struct resource *res, *mem; 1107 void __iomem *screen_base; 1108 struct drm_plane *primary_plane; 1109 struct drm_crtc *crtc; 1110 struct drm_encoder *encoder; 1111 struct drm_connector *connector; 1112 unsigned long max_width, max_height; 1113 size_t nformats; 1114 int ret; 1115 1116 odev = devm_drm_dev_alloc(&pdev->dev, drv, struct ofdrm_device, dev); 1117 if (IS_ERR(odev)) 1118 return ERR_CAST(odev); 1119 dev = &odev->dev; 1120 platform_set_drvdata(pdev, dev); 1121 1122 ret = ofdrm_device_init_pci(odev); 1123 if (ret) 1124 return ERR_PTR(ret); 1125 1126 /* 1127 * OF display-node settings 1128 */ 1129 1130 model = display_get_model_of(dev, of_node); 1131 drm_dbg(dev, "detected model %d\n", model); 1132 1133 switch (model) { 1134 case OFDRM_MODEL_UNKNOWN: 1135 odev->funcs = &ofdrm_unknown_device_funcs; 1136 break; 1137 case OFDRM_MODEL_MACH64: 1138 odev->funcs = &ofdrm_mach64_device_funcs; 1139 break; 1140 case OFDRM_MODEL_RAGE128: 1141 odev->funcs = &ofdrm_rage128_device_funcs; 1142 break; 1143 case OFDRM_MODEL_RAGE_M3A: 1144 odev->funcs = &ofdrm_rage_m3a_device_funcs; 1145 break; 1146 case OFDRM_MODEL_RAGE_M3B: 1147 odev->funcs = &ofdrm_rage_m3b_device_funcs; 1148 break; 1149 case OFDRM_MODEL_RADEON: 1150 odev->funcs = &ofdrm_radeon_device_funcs; 1151 break; 1152 case OFDRM_MODEL_GXT2000: 1153 odev->funcs = &ofdrm_gxt2000_device_funcs; 1154 break; 1155 case OFDRM_MODEL_AVIVO: 1156 odev->funcs = &ofdrm_avivo_device_funcs; 1157 break; 1158 case OFDRM_MODEL_QEMU: 1159 odev->funcs = &ofdrm_qemu_device_funcs; 1160 break; 1161 } 1162 1163 big_endian = display_get_big_endian_of(dev, of_node); 1164 1165 width = display_get_width_of(dev, of_node); 1166 if (width < 0) 1167 return ERR_PTR(width); 1168 height = display_get_height_of(dev, of_node); 1169 if (height < 0) 1170 return ERR_PTR(height); 1171 depth = display_get_depth_of(dev, of_node); 1172 if (depth < 0) 1173 return ERR_PTR(depth); 1174 linebytes = display_get_linebytes_of(dev, of_node); 1175 if (linebytes < 0) 1176 return ERR_PTR(linebytes); 1177 1178 format = display_get_validated_format(dev, depth, big_endian); 1179 if (IS_ERR(format)) 1180 return ERR_CAST(format); 1181 if (!linebytes) { 1182 linebytes = drm_format_info_min_pitch(format, 0, width); 1183 if (drm_WARN_ON(dev, !linebytes)) 1184 return ERR_PTR(-EINVAL); 1185 } 1186 1187 fb_size = linebytes * height; 1188 1189 /* 1190 * Try to figure out the address of the framebuffer. Unfortunately, Open 1191 * Firmware doesn't provide a standard way to do so. All we can do is a 1192 * dodgy heuristic that happens to work in practice. 1193 * 1194 * On most machines, the "address" property contains what we need, though 1195 * not on Matrox cards found in IBM machines. What appears to give good 1196 * results is to go through the PCI ranges and pick one that encloses the 1197 * "address" property. If none match, we pick the largest. 1198 */ 1199 address = display_get_address_of(dev, of_node); 1200 if (address != OF_BAD_ADDR) { 1201 struct resource fb_res = DEFINE_RES_MEM(address, fb_size); 1202 1203 res = ofdrm_find_fb_resource(odev, &fb_res); 1204 if (!res) 1205 return ERR_PTR(-EINVAL); 1206 if (resource_contains(res, &fb_res)) 1207 fb_base = address; 1208 else 1209 fb_base = res->start; 1210 } else { 1211 struct resource fb_res = DEFINE_RES_MEM(0u, fb_size); 1212 1213 res = ofdrm_find_fb_resource(odev, &fb_res); 1214 if (!res) 1215 return ERR_PTR(-EINVAL); 1216 fb_base = res->start; 1217 } 1218 1219 /* 1220 * I/O resources 1221 */ 1222 1223 fb_pgbase = round_down(fb_base, PAGE_SIZE); 1224 fb_pgsize = fb_base - fb_pgbase + round_up(fb_size, PAGE_SIZE); 1225 1226 ret = devm_aperture_acquire_from_firmware(dev, fb_pgbase, fb_pgsize); 1227 if (ret) { 1228 drm_err(dev, "could not acquire memory range %pr: error %d\n", &res, ret); 1229 return ERR_PTR(ret); 1230 } 1231 1232 mem = devm_request_mem_region(&pdev->dev, fb_pgbase, fb_pgsize, drv->name); 1233 if (!mem) { 1234 drm_warn(dev, "could not acquire memory region %pr\n", &res); 1235 return ERR_PTR(-ENOMEM); 1236 } 1237 1238 screen_base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); 1239 if (!screen_base) 1240 return ERR_PTR(-ENOMEM); 1241 1242 if (odev->funcs->cmap_ioremap) { 1243 void __iomem *cmap_base = odev->funcs->cmap_ioremap(odev, of_node, fb_base); 1244 1245 if (IS_ERR(cmap_base)) { 1246 /* Don't fail; continue without colormap */ 1247 drm_warn(dev, "could not find colormap: error %ld\n", PTR_ERR(cmap_base)); 1248 } else { 1249 odev->cmap_base = cmap_base; 1250 } 1251 } 1252 1253 /* 1254 * Firmware framebuffer 1255 */ 1256 1257 iosys_map_set_vaddr_iomem(&odev->screen_base, screen_base); 1258 odev->mode = ofdrm_mode(width, height); 1259 odev->format = format; 1260 odev->pitch = linebytes; 1261 1262 drm_dbg(dev, "display mode={" DRM_MODE_FMT "}\n", DRM_MODE_ARG(&odev->mode)); 1263 drm_dbg(dev, "framebuffer format=%p4cc, size=%dx%d, linebytes=%d byte\n", 1264 &format->format, width, height, linebytes); 1265 1266 /* 1267 * Mode-setting pipeline 1268 */ 1269 1270 ret = drmm_mode_config_init(dev); 1271 if (ret) 1272 return ERR_PTR(ret); 1273 1274 max_width = max_t(unsigned long, width, DRM_SHADOW_PLANE_MAX_WIDTH); 1275 max_height = max_t(unsigned long, height, DRM_SHADOW_PLANE_MAX_HEIGHT); 1276 1277 dev->mode_config.min_width = width; 1278 dev->mode_config.max_width = max_width; 1279 dev->mode_config.min_height = height; 1280 dev->mode_config.max_height = max_height; 1281 dev->mode_config.funcs = &ofdrm_mode_config_funcs; 1282 switch (depth) { 1283 case 32: 1284 dev->mode_config.preferred_depth = 24; 1285 break; 1286 default: 1287 dev->mode_config.preferred_depth = depth; 1288 break; 1289 } 1290 dev->mode_config.quirk_addfb_prefer_host_byte_order = true; 1291 1292 /* Primary plane */ 1293 1294 nformats = drm_fb_build_fourcc_list(dev, &format->format, 1, 1295 ofdrm_primary_plane_formats, 1296 ARRAY_SIZE(ofdrm_primary_plane_formats), 1297 odev->formats, ARRAY_SIZE(odev->formats)); 1298 1299 primary_plane = &odev->primary_plane; 1300 ret = drm_universal_plane_init(dev, primary_plane, 0, &ofdrm_primary_plane_funcs, 1301 odev->formats, nformats, 1302 ofdrm_primary_plane_format_modifiers, 1303 DRM_PLANE_TYPE_PRIMARY, NULL); 1304 if (ret) 1305 return ERR_PTR(ret); 1306 drm_plane_helper_add(primary_plane, &ofdrm_primary_plane_helper_funcs); 1307 drm_plane_enable_fb_damage_clips(primary_plane); 1308 1309 /* CRTC */ 1310 1311 crtc = &odev->crtc; 1312 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL, 1313 &ofdrm_crtc_funcs, NULL); 1314 if (ret) 1315 return ERR_PTR(ret); 1316 drm_crtc_helper_add(crtc, &ofdrm_crtc_helper_funcs); 1317 1318 if (odev->cmap_base) { 1319 drm_mode_crtc_set_gamma_size(crtc, OFDRM_GAMMA_LUT_SIZE); 1320 drm_crtc_enable_color_mgmt(crtc, 0, false, OFDRM_GAMMA_LUT_SIZE); 1321 } 1322 1323 /* Encoder */ 1324 1325 encoder = &odev->encoder; 1326 ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_NONE); 1327 if (ret) 1328 return ERR_PTR(ret); 1329 encoder->possible_crtcs = drm_crtc_mask(crtc); 1330 1331 /* Connector */ 1332 1333 connector = &odev->connector; 1334 ret = drm_connector_init(dev, connector, &ofdrm_connector_funcs, 1335 DRM_MODE_CONNECTOR_Unknown); 1336 if (ret) 1337 return ERR_PTR(ret); 1338 drm_connector_helper_add(connector, &ofdrm_connector_helper_funcs); 1339 drm_connector_set_panel_orientation_with_quirk(connector, 1340 DRM_MODE_PANEL_ORIENTATION_UNKNOWN, 1341 width, height); 1342 1343 ret = drm_connector_attach_encoder(connector, encoder); 1344 if (ret) 1345 return ERR_PTR(ret); 1346 1347 drm_mode_config_reset(dev); 1348 1349 return odev; 1350 } 1351 1352 /* 1353 * DRM driver 1354 */ 1355 1356 DEFINE_DRM_GEM_FOPS(ofdrm_fops); 1357 1358 static struct drm_driver ofdrm_driver = { 1359 DRM_GEM_SHMEM_DRIVER_OPS, 1360 .name = DRIVER_NAME, 1361 .desc = DRIVER_DESC, 1362 .date = DRIVER_DATE, 1363 .major = DRIVER_MAJOR, 1364 .minor = DRIVER_MINOR, 1365 .driver_features = DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET, 1366 .fops = &ofdrm_fops, 1367 }; 1368 1369 /* 1370 * Platform driver 1371 */ 1372 1373 static int ofdrm_probe(struct platform_device *pdev) 1374 { 1375 struct ofdrm_device *odev; 1376 struct drm_device *dev; 1377 int ret; 1378 1379 odev = ofdrm_device_create(&ofdrm_driver, pdev); 1380 if (IS_ERR(odev)) 1381 return PTR_ERR(odev); 1382 dev = &odev->dev; 1383 1384 ret = drm_dev_register(dev, 0); 1385 if (ret) 1386 return ret; 1387 1388 /* 1389 * FIXME: 24-bit color depth does not work reliably with a 32-bpp 1390 * value. Force the bpp value of the scanout buffer's format. 1391 */ 1392 drm_fbdev_generic_setup(dev, drm_format_info_bpp(odev->format, 0)); 1393 1394 return 0; 1395 } 1396 1397 static int ofdrm_remove(struct platform_device *pdev) 1398 { 1399 struct drm_device *dev = platform_get_drvdata(pdev); 1400 1401 drm_dev_unplug(dev); 1402 1403 return 0; 1404 } 1405 1406 static const struct of_device_id ofdrm_of_match_display[] = { 1407 { .compatible = "display", }, 1408 { }, 1409 }; 1410 MODULE_DEVICE_TABLE(of, ofdrm_of_match_display); 1411 1412 static struct platform_driver ofdrm_platform_driver = { 1413 .driver = { 1414 .name = "of-display", 1415 .of_match_table = ofdrm_of_match_display, 1416 }, 1417 .probe = ofdrm_probe, 1418 .remove = ofdrm_remove, 1419 }; 1420 1421 module_platform_driver(ofdrm_platform_driver); 1422 1423 MODULE_DESCRIPTION(DRIVER_DESC); 1424 MODULE_LICENSE("GPL"); 1425