1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/of_address.h> 4 #include <linux/pci.h> 5 #include <linux/platform_device.h> 6 7 #include <drm/drm_aperture.h> 8 #include <drm/drm_atomic.h> 9 #include <drm/drm_atomic_state_helper.h> 10 #include <drm/drm_connector.h> 11 #include <drm/drm_damage_helper.h> 12 #include <drm/drm_device.h> 13 #include <drm/drm_drv.h> 14 #include <drm/drm_fbdev_generic.h> 15 #include <drm/drm_format_helper.h> 16 #include <drm/drm_framebuffer.h> 17 #include <drm/drm_gem_atomic_helper.h> 18 #include <drm/drm_gem_framebuffer_helper.h> 19 #include <drm/drm_gem_shmem_helper.h> 20 #include <drm/drm_managed.h> 21 #include <drm/drm_modeset_helper_vtables.h> 22 #include <drm/drm_plane_helper.h> 23 #include <drm/drm_probe_helper.h> 24 #include <drm/drm_simple_kms_helper.h> 25 26 #define DRIVER_NAME "ofdrm" 27 #define DRIVER_DESC "DRM driver for OF platform devices" 28 #define DRIVER_DATE "20220501" 29 #define DRIVER_MAJOR 1 30 #define DRIVER_MINOR 0 31 32 #define PCI_VENDOR_ID_ATI_R520 0x7100 33 #define PCI_VENDOR_ID_ATI_R600 0x9400 34 35 #define OFDRM_GAMMA_LUT_SIZE 256 36 37 /* Definitions used by the Avivo palette */ 38 #define AVIVO_DC_LUT_RW_SELECT 0x6480 39 #define AVIVO_DC_LUT_RW_MODE 0x6484 40 #define AVIVO_DC_LUT_RW_INDEX 0x6488 41 #define AVIVO_DC_LUT_SEQ_COLOR 0x648c 42 #define AVIVO_DC_LUT_PWL_DATA 0x6490 43 #define AVIVO_DC_LUT_30_COLOR 0x6494 44 #define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498 45 #define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c 46 #define AVIVO_DC_LUT_AUTOFILL 0x64a0 47 #define AVIVO_DC_LUTA_CONTROL 0x64c0 48 #define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4 49 #define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8 50 #define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc 51 #define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0 52 #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 53 #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 54 #define AVIVO_DC_LUTB_CONTROL 0x6cc0 55 #define AVIVO_DC_LUTB_BLACK_OFFSET_BLUE 0x6cc4 56 #define AVIVO_DC_LUTB_BLACK_OFFSET_GREEN 0x6cc8 57 #define AVIVO_DC_LUTB_BLACK_OFFSET_RED 0x6ccc 58 #define AVIVO_DC_LUTB_WHITE_OFFSET_BLUE 0x6cd0 59 #define AVIVO_DC_LUTB_WHITE_OFFSET_GREEN 0x6cd4 60 #define AVIVO_DC_LUTB_WHITE_OFFSET_RED 0x6cd8 61 62 enum ofdrm_model { 63 OFDRM_MODEL_UNKNOWN, 64 OFDRM_MODEL_MACH64, /* ATI Mach64 */ 65 OFDRM_MODEL_RAGE128, /* ATI Rage128 */ 66 OFDRM_MODEL_RAGE_M3A, /* ATI Rage Mobility M3 Head A */ 67 OFDRM_MODEL_RAGE_M3B, /* ATI Rage Mobility M3 Head B */ 68 OFDRM_MODEL_RADEON, /* ATI Radeon */ 69 OFDRM_MODEL_GXT2000, /* IBM GXT2000 */ 70 OFDRM_MODEL_AVIVO, /* ATI R5xx */ 71 OFDRM_MODEL_QEMU, /* QEMU VGA */ 72 }; 73 74 /* 75 * Helpers for display nodes 76 */ 77 78 static int display_get_validated_int(struct drm_device *dev, const char *name, uint32_t value) 79 { 80 if (value > INT_MAX) { 81 drm_err(dev, "invalid framebuffer %s of %u\n", name, value); 82 return -EINVAL; 83 } 84 return (int)value; 85 } 86 87 static int display_get_validated_int0(struct drm_device *dev, const char *name, uint32_t value) 88 { 89 if (!value) { 90 drm_err(dev, "invalid framebuffer %s of %u\n", name, value); 91 return -EINVAL; 92 } 93 return display_get_validated_int(dev, name, value); 94 } 95 96 static const struct drm_format_info *display_get_validated_format(struct drm_device *dev, 97 u32 depth, bool big_endian) 98 { 99 const struct drm_format_info *info; 100 u32 format; 101 102 switch (depth) { 103 case 8: 104 format = drm_mode_legacy_fb_format(8, 8); 105 break; 106 case 15: 107 case 16: 108 format = drm_mode_legacy_fb_format(16, depth); 109 break; 110 case 32: 111 format = drm_mode_legacy_fb_format(32, 24); 112 break; 113 default: 114 drm_err(dev, "unsupported framebuffer depth %u\n", depth); 115 return ERR_PTR(-EINVAL); 116 } 117 118 /* 119 * DRM formats assume little-endian byte order. Update the format 120 * if the scanout buffer uses big-endian ordering. 121 */ 122 if (big_endian) { 123 switch (format) { 124 case DRM_FORMAT_XRGB8888: 125 format = DRM_FORMAT_BGRX8888; 126 break; 127 case DRM_FORMAT_ARGB8888: 128 format = DRM_FORMAT_BGRA8888; 129 break; 130 case DRM_FORMAT_RGB565: 131 format = DRM_FORMAT_RGB565 | DRM_FORMAT_BIG_ENDIAN; 132 break; 133 case DRM_FORMAT_XRGB1555: 134 format = DRM_FORMAT_XRGB1555 | DRM_FORMAT_BIG_ENDIAN; 135 break; 136 default: 137 break; 138 } 139 } 140 141 info = drm_format_info(format); 142 if (!info) { 143 drm_err(dev, "cannot find framebuffer format for depth %u\n", depth); 144 return ERR_PTR(-EINVAL); 145 } 146 147 return info; 148 } 149 150 static int display_read_u32_of(struct drm_device *dev, struct device_node *of_node, 151 const char *name, u32 *value) 152 { 153 int ret = of_property_read_u32(of_node, name, value); 154 155 if (ret) 156 drm_err(dev, "cannot parse framebuffer %s: error %d\n", name, ret); 157 return ret; 158 } 159 160 static bool display_get_big_endian_of(struct drm_device *dev, struct device_node *of_node) 161 { 162 bool big_endian; 163 164 #ifdef __BIG_ENDIAN 165 big_endian = true; 166 if (of_get_property(of_node, "little-endian", NULL)) 167 big_endian = false; 168 #else 169 big_endian = false; 170 if (of_get_property(of_node, "big-endian", NULL)) 171 big_endian = true; 172 #endif 173 174 return big_endian; 175 } 176 177 static int display_get_width_of(struct drm_device *dev, struct device_node *of_node) 178 { 179 u32 width; 180 int ret = display_read_u32_of(dev, of_node, "width", &width); 181 182 if (ret) 183 return ret; 184 return display_get_validated_int0(dev, "width", width); 185 } 186 187 static int display_get_height_of(struct drm_device *dev, struct device_node *of_node) 188 { 189 u32 height; 190 int ret = display_read_u32_of(dev, of_node, "height", &height); 191 192 if (ret) 193 return ret; 194 return display_get_validated_int0(dev, "height", height); 195 } 196 197 static int display_get_depth_of(struct drm_device *dev, struct device_node *of_node) 198 { 199 u32 depth; 200 int ret = display_read_u32_of(dev, of_node, "depth", &depth); 201 202 if (ret) 203 return ret; 204 return display_get_validated_int0(dev, "depth", depth); 205 } 206 207 static int display_get_linebytes_of(struct drm_device *dev, struct device_node *of_node) 208 { 209 u32 linebytes; 210 int ret = display_read_u32_of(dev, of_node, "linebytes", &linebytes); 211 212 if (ret) 213 return ret; 214 return display_get_validated_int(dev, "linebytes", linebytes); 215 } 216 217 static u64 display_get_address_of(struct drm_device *dev, struct device_node *of_node) 218 { 219 u32 address; 220 int ret; 221 222 /* 223 * Not all devices provide an address property, it's not 224 * a bug if this fails. The driver will try to find the 225 * framebuffer base address from the device's memory regions. 226 */ 227 ret = of_property_read_u32(of_node, "address", &address); 228 if (ret) 229 return OF_BAD_ADDR; 230 231 return address; 232 } 233 234 static bool is_avivo(u32 vendor, u32 device) 235 { 236 /* This will match most R5xx */ 237 return (vendor == PCI_VENDOR_ID_ATI) && 238 ((device >= PCI_VENDOR_ID_ATI_R520 && device < 0x7800) || 239 (PCI_VENDOR_ID_ATI_R600 >= 0x9400)); 240 } 241 242 static enum ofdrm_model display_get_model_of(struct drm_device *dev, struct device_node *of_node) 243 { 244 enum ofdrm_model model = OFDRM_MODEL_UNKNOWN; 245 246 if (of_node_name_prefix(of_node, "ATY,Rage128")) { 247 model = OFDRM_MODEL_RAGE128; 248 } else if (of_node_name_prefix(of_node, "ATY,RageM3pA") || 249 of_node_name_prefix(of_node, "ATY,RageM3p12A")) { 250 model = OFDRM_MODEL_RAGE_M3A; 251 } else if (of_node_name_prefix(of_node, "ATY,RageM3pB")) { 252 model = OFDRM_MODEL_RAGE_M3B; 253 } else if (of_node_name_prefix(of_node, "ATY,Rage6")) { 254 model = OFDRM_MODEL_RADEON; 255 } else if (of_node_name_prefix(of_node, "ATY,")) { 256 return OFDRM_MODEL_MACH64; 257 } else if (of_device_is_compatible(of_node, "pci1014,b7") || 258 of_device_is_compatible(of_node, "pci1014,21c")) { 259 model = OFDRM_MODEL_GXT2000; 260 } else if (of_node_name_prefix(of_node, "vga,Display-")) { 261 struct device_node *of_parent; 262 const __be32 *vendor_p, *device_p; 263 264 /* Look for AVIVO initialized by SLOF */ 265 of_parent = of_get_parent(of_node); 266 vendor_p = of_get_property(of_parent, "vendor-id", NULL); 267 device_p = of_get_property(of_parent, "device-id", NULL); 268 if (vendor_p && device_p) { 269 u32 vendor = be32_to_cpup(vendor_p); 270 u32 device = be32_to_cpup(device_p); 271 272 if (is_avivo(vendor, device)) 273 model = OFDRM_MODEL_AVIVO; 274 } 275 of_node_put(of_parent); 276 } else if (of_device_is_compatible(of_node, "qemu,std-vga")) { 277 model = OFDRM_MODEL_QEMU; 278 } 279 280 return model; 281 } 282 283 /* 284 * Open Firmware display device 285 */ 286 287 struct ofdrm_device; 288 289 struct ofdrm_device_funcs { 290 void __iomem *(*cmap_ioremap)(struct ofdrm_device *odev, 291 struct device_node *of_node, 292 u64 fb_bas); 293 void (*cmap_write)(struct ofdrm_device *odev, unsigned char index, 294 unsigned char r, unsigned char g, unsigned char b); 295 }; 296 297 struct ofdrm_device { 298 struct drm_device dev; 299 struct platform_device *pdev; 300 301 const struct ofdrm_device_funcs *funcs; 302 303 /* firmware-buffer settings */ 304 struct iosys_map screen_base; 305 struct drm_display_mode mode; 306 const struct drm_format_info *format; 307 unsigned int pitch; 308 309 /* colormap */ 310 void __iomem *cmap_base; 311 312 /* modesetting */ 313 uint32_t formats[8]; 314 struct drm_plane primary_plane; 315 struct drm_crtc crtc; 316 struct drm_encoder encoder; 317 struct drm_connector connector; 318 }; 319 320 static struct ofdrm_device *ofdrm_device_of_dev(struct drm_device *dev) 321 { 322 return container_of(dev, struct ofdrm_device, dev); 323 } 324 325 /* 326 * Hardware 327 */ 328 329 #if defined(CONFIG_PCI) 330 static struct pci_dev *display_get_pci_dev_of(struct drm_device *dev, struct device_node *of_node) 331 { 332 const __be32 *vendor_p, *device_p; 333 u32 vendor, device; 334 struct pci_dev *pcidev; 335 336 vendor_p = of_get_property(of_node, "vendor-id", NULL); 337 if (!vendor_p) 338 return ERR_PTR(-ENODEV); 339 vendor = be32_to_cpup(vendor_p); 340 341 device_p = of_get_property(of_node, "device-id", NULL); 342 if (!device_p) 343 return ERR_PTR(-ENODEV); 344 device = be32_to_cpup(device_p); 345 346 pcidev = pci_get_device(vendor, device, NULL); 347 if (!pcidev) 348 return ERR_PTR(-ENODEV); 349 350 return pcidev; 351 } 352 353 static void ofdrm_pci_release(void *data) 354 { 355 struct pci_dev *pcidev = data; 356 357 pci_disable_device(pcidev); 358 } 359 360 static int ofdrm_device_init_pci(struct ofdrm_device *odev) 361 { 362 struct drm_device *dev = &odev->dev; 363 struct platform_device *pdev = to_platform_device(dev->dev); 364 struct device_node *of_node = pdev->dev.of_node; 365 struct pci_dev *pcidev; 366 int ret; 367 368 /* 369 * Never use pcim_ or other managed helpers on the returned PCI 370 * device. Otherwise, probing the native driver will fail for 371 * resource conflicts. PCI-device management has to be tied to 372 * the lifetime of the platform device until the native driver 373 * takes over. 374 */ 375 pcidev = display_get_pci_dev_of(dev, of_node); 376 if (IS_ERR(pcidev)) 377 return 0; /* no PCI device found; ignore the error */ 378 379 ret = pci_enable_device(pcidev); 380 if (ret) { 381 drm_err(dev, "pci_enable_device(%s) failed: %d\n", 382 dev_name(&pcidev->dev), ret); 383 return ret; 384 } 385 ret = devm_add_action_or_reset(&pdev->dev, ofdrm_pci_release, pcidev); 386 if (ret) 387 return ret; 388 389 return 0; 390 } 391 #else 392 static int ofdrm_device_init_pci(struct ofdrm_device *odev) 393 { 394 return 0; 395 } 396 #endif 397 398 /* 399 * OF display settings 400 */ 401 402 static struct resource *ofdrm_find_fb_resource(struct ofdrm_device *odev, 403 struct resource *fb_res) 404 { 405 struct platform_device *pdev = to_platform_device(odev->dev.dev); 406 struct resource *res, *max_res = NULL; 407 u32 i; 408 409 for (i = 0; pdev->num_resources; ++i) { 410 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 411 if (!res) 412 break; /* all resources processed */ 413 if (resource_size(res) < resource_size(fb_res)) 414 continue; /* resource too small */ 415 if (fb_res->start && resource_contains(res, fb_res)) 416 return res; /* resource contains framebuffer */ 417 if (!max_res || resource_size(res) > resource_size(max_res)) 418 max_res = res; /* store largest resource as fallback */ 419 } 420 421 return max_res; 422 } 423 424 /* 425 * Colormap / Palette 426 */ 427 428 static void __iomem *get_cmap_address_of(struct ofdrm_device *odev, struct device_node *of_node, 429 int bar_no, unsigned long offset, unsigned long size) 430 { 431 struct drm_device *dev = &odev->dev; 432 const __be32 *addr_p; 433 u64 max_size, address; 434 unsigned int flags; 435 void __iomem *mem; 436 437 addr_p = of_get_pci_address(of_node, bar_no, &max_size, &flags); 438 if (!addr_p) 439 addr_p = of_get_address(of_node, bar_no, &max_size, &flags); 440 if (!addr_p) 441 return IOMEM_ERR_PTR(-ENODEV); 442 443 if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0) 444 return IOMEM_ERR_PTR(-ENODEV); 445 446 if ((offset + size) >= max_size) 447 return IOMEM_ERR_PTR(-ENODEV); 448 449 address = of_translate_address(of_node, addr_p); 450 if (address == OF_BAD_ADDR) 451 return IOMEM_ERR_PTR(-ENODEV); 452 453 mem = devm_ioremap(dev->dev, address + offset, size); 454 if (!mem) 455 return IOMEM_ERR_PTR(-ENOMEM); 456 457 return mem; 458 } 459 460 static void __iomem *ofdrm_mach64_cmap_ioremap(struct ofdrm_device *odev, 461 struct device_node *of_node, 462 u64 fb_base) 463 { 464 struct drm_device *dev = &odev->dev; 465 u64 address; 466 void __iomem *cmap_base; 467 468 address = fb_base & 0xff000000ul; 469 address += 0x7ff000; 470 471 cmap_base = devm_ioremap(dev->dev, address, 0x1000); 472 if (!cmap_base) 473 return IOMEM_ERR_PTR(-ENOMEM); 474 475 return cmap_base; 476 } 477 478 static void ofdrm_mach64_cmap_write(struct ofdrm_device *odev, unsigned char index, 479 unsigned char r, unsigned char g, unsigned char b) 480 { 481 void __iomem *addr = odev->cmap_base + 0xcc0; 482 void __iomem *data = odev->cmap_base + 0xcc0 + 1; 483 484 writeb(index, addr); 485 writeb(r, data); 486 writeb(g, data); 487 writeb(b, data); 488 } 489 490 static void __iomem *ofdrm_rage128_cmap_ioremap(struct ofdrm_device *odev, 491 struct device_node *of_node, 492 u64 fb_base) 493 { 494 return get_cmap_address_of(odev, of_node, 2, 0, 0x1fff); 495 } 496 497 static void ofdrm_rage128_cmap_write(struct ofdrm_device *odev, unsigned char index, 498 unsigned char r, unsigned char g, unsigned char b) 499 { 500 void __iomem *addr = odev->cmap_base + 0xb0; 501 void __iomem *data = odev->cmap_base + 0xb4; 502 u32 color = (r << 16) | (g << 8) | b; 503 504 writeb(index, addr); 505 writel(color, data); 506 } 507 508 static void __iomem *ofdrm_rage_m3a_cmap_ioremap(struct ofdrm_device *odev, 509 struct device_node *of_node, 510 u64 fb_base) 511 { 512 return get_cmap_address_of(odev, of_node, 2, 0, 0x1fff); 513 } 514 515 static void ofdrm_rage_m3a_cmap_write(struct ofdrm_device *odev, unsigned char index, 516 unsigned char r, unsigned char g, unsigned char b) 517 { 518 void __iomem *dac_ctl = odev->cmap_base + 0x58; 519 void __iomem *addr = odev->cmap_base + 0xb0; 520 void __iomem *data = odev->cmap_base + 0xb4; 521 u32 color = (r << 16) | (g << 8) | b; 522 u32 val; 523 524 /* Clear PALETTE_ACCESS_CNTL in DAC_CNTL */ 525 val = readl(dac_ctl); 526 val &= ~0x20; 527 writel(val, dac_ctl); 528 529 /* Set color at palette index */ 530 writeb(index, addr); 531 writel(color, data); 532 } 533 534 static void __iomem *ofdrm_rage_m3b_cmap_ioremap(struct ofdrm_device *odev, 535 struct device_node *of_node, 536 u64 fb_base) 537 { 538 return get_cmap_address_of(odev, of_node, 2, 0, 0x1fff); 539 } 540 541 static void ofdrm_rage_m3b_cmap_write(struct ofdrm_device *odev, unsigned char index, 542 unsigned char r, unsigned char g, unsigned char b) 543 { 544 void __iomem *dac_ctl = odev->cmap_base + 0x58; 545 void __iomem *addr = odev->cmap_base + 0xb0; 546 void __iomem *data = odev->cmap_base + 0xb4; 547 u32 color = (r << 16) | (g << 8) | b; 548 u32 val; 549 550 /* Set PALETTE_ACCESS_CNTL in DAC_CNTL */ 551 val = readl(dac_ctl); 552 val |= 0x20; 553 writel(val, dac_ctl); 554 555 /* Set color at palette index */ 556 writeb(index, addr); 557 writel(color, data); 558 } 559 560 static void __iomem *ofdrm_radeon_cmap_ioremap(struct ofdrm_device *odev, 561 struct device_node *of_node, 562 u64 fb_base) 563 { 564 return get_cmap_address_of(odev, of_node, 1, 0, 0x1fff); 565 } 566 567 static void __iomem *ofdrm_gxt2000_cmap_ioremap(struct ofdrm_device *odev, 568 struct device_node *of_node, 569 u64 fb_base) 570 { 571 return get_cmap_address_of(odev, of_node, 0, 0x6000, 0x1000); 572 } 573 574 static void ofdrm_gxt2000_cmap_write(struct ofdrm_device *odev, unsigned char index, 575 unsigned char r, unsigned char g, unsigned char b) 576 { 577 void __iomem *data = ((unsigned int __iomem *)odev->cmap_base) + index; 578 u32 color = (r << 16) | (g << 8) | b; 579 580 writel(color, data); 581 } 582 583 static void __iomem *ofdrm_avivo_cmap_ioremap(struct ofdrm_device *odev, 584 struct device_node *of_node, 585 u64 fb_base) 586 { 587 struct device_node *of_parent; 588 void __iomem *cmap_base; 589 590 of_parent = of_get_parent(of_node); 591 cmap_base = get_cmap_address_of(odev, of_parent, 0, 0, 0x10000); 592 of_node_put(of_parent); 593 594 return cmap_base; 595 } 596 597 static void ofdrm_avivo_cmap_write(struct ofdrm_device *odev, unsigned char index, 598 unsigned char r, unsigned char g, unsigned char b) 599 { 600 void __iomem *lutsel = odev->cmap_base + AVIVO_DC_LUT_RW_SELECT; 601 void __iomem *addr = odev->cmap_base + AVIVO_DC_LUT_RW_INDEX; 602 void __iomem *data = odev->cmap_base + AVIVO_DC_LUT_30_COLOR; 603 u32 color = (r << 22) | (g << 12) | (b << 2); 604 605 /* Write to both LUTs for now */ 606 607 writel(1, lutsel); 608 writeb(index, addr); 609 writel(color, data); 610 611 writel(0, lutsel); 612 writeb(index, addr); 613 writel(color, data); 614 } 615 616 static void __iomem *ofdrm_qemu_cmap_ioremap(struct ofdrm_device *odev, 617 struct device_node *of_node, 618 u64 fb_base) 619 { 620 static const __be32 io_of_addr[3] = { 621 cpu_to_be32(0x01000000), 622 cpu_to_be32(0x00), 623 cpu_to_be32(0x00), 624 }; 625 626 struct drm_device *dev = &odev->dev; 627 u64 address; 628 void __iomem *cmap_base; 629 630 address = of_translate_address(of_node, io_of_addr); 631 if (address == OF_BAD_ADDR) 632 return IOMEM_ERR_PTR(-ENODEV); 633 634 cmap_base = devm_ioremap(dev->dev, address + 0x3c8, 2); 635 if (!cmap_base) 636 return IOMEM_ERR_PTR(-ENOMEM); 637 638 return cmap_base; 639 } 640 641 static void ofdrm_qemu_cmap_write(struct ofdrm_device *odev, unsigned char index, 642 unsigned char r, unsigned char g, unsigned char b) 643 { 644 void __iomem *addr = odev->cmap_base; 645 void __iomem *data = odev->cmap_base + 1; 646 647 writeb(index, addr); 648 writeb(r, data); 649 writeb(g, data); 650 writeb(b, data); 651 } 652 653 static void ofdrm_device_set_gamma_linear(struct ofdrm_device *odev, 654 const struct drm_format_info *format) 655 { 656 struct drm_device *dev = &odev->dev; 657 int i; 658 659 switch (format->format) { 660 case DRM_FORMAT_RGB565: 661 case DRM_FORMAT_RGB565 | DRM_FORMAT_BIG_ENDIAN: 662 /* Use better interpolation, to take 32 values from 0 to 255 */ 663 for (i = 0; i < OFDRM_GAMMA_LUT_SIZE / 8; i++) { 664 unsigned char r = i * 8 + i / 4; 665 unsigned char g = i * 4 + i / 16; 666 unsigned char b = i * 8 + i / 4; 667 668 odev->funcs->cmap_write(odev, i, r, g, b); 669 } 670 /* Green has one more bit, so add padding with 0 for red and blue. */ 671 for (i = OFDRM_GAMMA_LUT_SIZE / 8; i < OFDRM_GAMMA_LUT_SIZE / 4; i++) { 672 unsigned char r = 0; 673 unsigned char g = i * 4 + i / 16; 674 unsigned char b = 0; 675 676 odev->funcs->cmap_write(odev, i, r, g, b); 677 } 678 break; 679 case DRM_FORMAT_XRGB8888: 680 case DRM_FORMAT_BGRX8888: 681 for (i = 0; i < OFDRM_GAMMA_LUT_SIZE; i++) 682 odev->funcs->cmap_write(odev, i, i, i, i); 683 break; 684 default: 685 drm_warn_once(dev, "Unsupported format %p4cc for gamma correction\n", 686 &format->format); 687 break; 688 } 689 } 690 691 static void ofdrm_device_set_gamma(struct ofdrm_device *odev, 692 const struct drm_format_info *format, 693 struct drm_color_lut *lut) 694 { 695 struct drm_device *dev = &odev->dev; 696 int i; 697 698 switch (format->format) { 699 case DRM_FORMAT_RGB565: 700 case DRM_FORMAT_RGB565 | DRM_FORMAT_BIG_ENDIAN: 701 /* Use better interpolation, to take 32 values from lut[0] to lut[255] */ 702 for (i = 0; i < OFDRM_GAMMA_LUT_SIZE / 8; i++) { 703 unsigned char r = lut[i * 8 + i / 4].red >> 8; 704 unsigned char g = lut[i * 4 + i / 16].green >> 8; 705 unsigned char b = lut[i * 8 + i / 4].blue >> 8; 706 707 odev->funcs->cmap_write(odev, i, r, g, b); 708 } 709 /* Green has one more bit, so add padding with 0 for red and blue. */ 710 for (i = OFDRM_GAMMA_LUT_SIZE / 8; i < OFDRM_GAMMA_LUT_SIZE / 4; i++) { 711 unsigned char r = 0; 712 unsigned char g = lut[i * 4 + i / 16].green >> 8; 713 unsigned char b = 0; 714 715 odev->funcs->cmap_write(odev, i, r, g, b); 716 } 717 break; 718 case DRM_FORMAT_XRGB8888: 719 case DRM_FORMAT_BGRX8888: 720 for (i = 0; i < OFDRM_GAMMA_LUT_SIZE; i++) { 721 unsigned char r = lut[i].red >> 8; 722 unsigned char g = lut[i].green >> 8; 723 unsigned char b = lut[i].blue >> 8; 724 725 odev->funcs->cmap_write(odev, i, r, g, b); 726 } 727 break; 728 default: 729 drm_warn_once(dev, "Unsupported format %p4cc for gamma correction\n", 730 &format->format); 731 break; 732 } 733 } 734 735 /* 736 * Modesetting 737 */ 738 739 struct ofdrm_crtc_state { 740 struct drm_crtc_state base; 741 742 /* Primary-plane format; required for color mgmt. */ 743 const struct drm_format_info *format; 744 }; 745 746 static struct ofdrm_crtc_state *to_ofdrm_crtc_state(struct drm_crtc_state *base) 747 { 748 return container_of(base, struct ofdrm_crtc_state, base); 749 } 750 751 static void ofdrm_crtc_state_destroy(struct ofdrm_crtc_state *ofdrm_crtc_state) 752 { 753 __drm_atomic_helper_crtc_destroy_state(&ofdrm_crtc_state->base); 754 kfree(ofdrm_crtc_state); 755 } 756 757 /* 758 * Support all formats of OF display and maybe more; in order 759 * of preference. The display's update function will do any 760 * conversion necessary. 761 * 762 * TODO: Add blit helpers for remaining formats and uncomment 763 * constants. 764 */ 765 static const uint32_t ofdrm_primary_plane_formats[] = { 766 DRM_FORMAT_XRGB8888, 767 DRM_FORMAT_RGB565, 768 //DRM_FORMAT_XRGB1555, 769 //DRM_FORMAT_C8, 770 /* Big-endian formats below */ 771 DRM_FORMAT_BGRX8888, 772 DRM_FORMAT_RGB565 | DRM_FORMAT_BIG_ENDIAN, 773 }; 774 775 static const uint64_t ofdrm_primary_plane_format_modifiers[] = { 776 DRM_FORMAT_MOD_LINEAR, 777 DRM_FORMAT_MOD_INVALID 778 }; 779 780 static int ofdrm_primary_plane_helper_atomic_check(struct drm_plane *plane, 781 struct drm_atomic_state *new_state) 782 { 783 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(new_state, plane); 784 struct drm_framebuffer *new_fb = new_plane_state->fb; 785 struct drm_crtc *new_crtc = new_plane_state->crtc; 786 struct drm_crtc_state *new_crtc_state = NULL; 787 struct ofdrm_crtc_state *new_ofdrm_crtc_state; 788 int ret; 789 790 if (new_crtc) 791 new_crtc_state = drm_atomic_get_new_crtc_state(new_state, new_plane_state->crtc); 792 793 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state, 794 DRM_PLANE_NO_SCALING, 795 DRM_PLANE_NO_SCALING, 796 false, false); 797 if (ret) 798 return ret; 799 else if (!new_plane_state->visible) 800 return 0; 801 802 new_crtc_state = drm_atomic_get_new_crtc_state(new_state, new_plane_state->crtc); 803 804 new_ofdrm_crtc_state = to_ofdrm_crtc_state(new_crtc_state); 805 new_ofdrm_crtc_state->format = new_fb->format; 806 807 return 0; 808 } 809 810 static void ofdrm_primary_plane_helper_atomic_update(struct drm_plane *plane, 811 struct drm_atomic_state *state) 812 { 813 struct drm_device *dev = plane->dev; 814 struct ofdrm_device *odev = ofdrm_device_of_dev(dev); 815 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 816 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane); 817 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state); 818 struct drm_framebuffer *fb = plane_state->fb; 819 unsigned int dst_pitch = odev->pitch; 820 const struct drm_format_info *dst_format = odev->format; 821 struct drm_atomic_helper_damage_iter iter; 822 struct drm_rect damage; 823 int ret, idx; 824 825 ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE); 826 if (ret) 827 return; 828 829 if (!drm_dev_enter(dev, &idx)) 830 goto out_drm_gem_fb_end_cpu_access; 831 832 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state); 833 drm_atomic_for_each_plane_damage(&iter, &damage) { 834 struct iosys_map dst = odev->screen_base; 835 struct drm_rect dst_clip = plane_state->dst; 836 837 if (!drm_rect_intersect(&dst_clip, &damage)) 838 continue; 839 840 iosys_map_incr(&dst, drm_fb_clip_offset(dst_pitch, dst_format, &dst_clip)); 841 drm_fb_blit(&dst, &dst_pitch, dst_format->format, shadow_plane_state->data, fb, 842 &damage); 843 } 844 845 drm_dev_exit(idx); 846 out_drm_gem_fb_end_cpu_access: 847 drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE); 848 } 849 850 static void ofdrm_primary_plane_helper_atomic_disable(struct drm_plane *plane, 851 struct drm_atomic_state *state) 852 { 853 struct drm_device *dev = plane->dev; 854 struct ofdrm_device *odev = ofdrm_device_of_dev(dev); 855 struct iosys_map dst = odev->screen_base; 856 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane); 857 void __iomem *dst_vmap = dst.vaddr_iomem; /* TODO: Use mapping abstraction */ 858 unsigned int dst_pitch = odev->pitch; 859 const struct drm_format_info *dst_format = odev->format; 860 struct drm_rect dst_clip; 861 unsigned long lines, linepixels, i; 862 int idx; 863 864 drm_rect_init(&dst_clip, 865 plane_state->src_x >> 16, plane_state->src_y >> 16, 866 plane_state->src_w >> 16, plane_state->src_h >> 16); 867 868 lines = drm_rect_height(&dst_clip); 869 linepixels = drm_rect_width(&dst_clip); 870 871 if (!drm_dev_enter(dev, &idx)) 872 return; 873 874 /* Clear buffer to black if disabled */ 875 dst_vmap += drm_fb_clip_offset(dst_pitch, dst_format, &dst_clip); 876 for (i = 0; i < lines; ++i) { 877 memset_io(dst_vmap, 0, linepixels * dst_format->cpp[0]); 878 dst_vmap += dst_pitch; 879 } 880 881 drm_dev_exit(idx); 882 } 883 884 static const struct drm_plane_helper_funcs ofdrm_primary_plane_helper_funcs = { 885 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, 886 .atomic_check = ofdrm_primary_plane_helper_atomic_check, 887 .atomic_update = ofdrm_primary_plane_helper_atomic_update, 888 .atomic_disable = ofdrm_primary_plane_helper_atomic_disable, 889 }; 890 891 static const struct drm_plane_funcs ofdrm_primary_plane_funcs = { 892 .update_plane = drm_atomic_helper_update_plane, 893 .disable_plane = drm_atomic_helper_disable_plane, 894 .destroy = drm_plane_cleanup, 895 DRM_GEM_SHADOW_PLANE_FUNCS, 896 }; 897 898 static enum drm_mode_status ofdrm_crtc_helper_mode_valid(struct drm_crtc *crtc, 899 const struct drm_display_mode *mode) 900 { 901 struct ofdrm_device *odev = ofdrm_device_of_dev(crtc->dev); 902 903 return drm_crtc_helper_mode_valid_fixed(crtc, mode, &odev->mode); 904 } 905 906 static int ofdrm_crtc_helper_atomic_check(struct drm_crtc *crtc, 907 struct drm_atomic_state *new_state) 908 { 909 static const size_t gamma_lut_length = OFDRM_GAMMA_LUT_SIZE * sizeof(struct drm_color_lut); 910 911 struct drm_device *dev = crtc->dev; 912 struct drm_crtc_state *new_crtc_state = drm_atomic_get_new_crtc_state(new_state, crtc); 913 int ret; 914 915 if (!new_crtc_state->enable) 916 return 0; 917 918 ret = drm_atomic_helper_check_crtc_primary_plane(new_crtc_state); 919 if (ret) 920 return ret; 921 922 if (new_crtc_state->color_mgmt_changed) { 923 struct drm_property_blob *gamma_lut = new_crtc_state->gamma_lut; 924 925 if (gamma_lut && (gamma_lut->length != gamma_lut_length)) { 926 drm_dbg(dev, "Incorrect gamma_lut length %zu\n", gamma_lut->length); 927 return -EINVAL; 928 } 929 } 930 931 return 0; 932 } 933 934 static void ofdrm_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state) 935 { 936 struct ofdrm_device *odev = ofdrm_device_of_dev(crtc->dev); 937 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 938 struct ofdrm_crtc_state *ofdrm_crtc_state = to_ofdrm_crtc_state(crtc_state); 939 940 if (crtc_state->enable && crtc_state->color_mgmt_changed) { 941 const struct drm_format_info *format = ofdrm_crtc_state->format; 942 943 if (crtc_state->gamma_lut) 944 ofdrm_device_set_gamma(odev, format, crtc_state->gamma_lut->data); 945 else 946 ofdrm_device_set_gamma_linear(odev, format); 947 } 948 } 949 950 /* 951 * The CRTC is always enabled. Screen updates are performed by 952 * the primary plane's atomic_update function. Disabling clears 953 * the screen in the primary plane's atomic_disable function. 954 */ 955 static const struct drm_crtc_helper_funcs ofdrm_crtc_helper_funcs = { 956 .mode_valid = ofdrm_crtc_helper_mode_valid, 957 .atomic_check = ofdrm_crtc_helper_atomic_check, 958 .atomic_flush = ofdrm_crtc_helper_atomic_flush, 959 }; 960 961 static void ofdrm_crtc_reset(struct drm_crtc *crtc) 962 { 963 struct ofdrm_crtc_state *ofdrm_crtc_state = 964 kzalloc(sizeof(*ofdrm_crtc_state), GFP_KERNEL); 965 966 if (crtc->state) 967 ofdrm_crtc_state_destroy(to_ofdrm_crtc_state(crtc->state)); 968 969 if (ofdrm_crtc_state) 970 __drm_atomic_helper_crtc_reset(crtc, &ofdrm_crtc_state->base); 971 else 972 __drm_atomic_helper_crtc_reset(crtc, NULL); 973 } 974 975 static struct drm_crtc_state *ofdrm_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 976 { 977 struct drm_device *dev = crtc->dev; 978 struct drm_crtc_state *crtc_state = crtc->state; 979 struct ofdrm_crtc_state *new_ofdrm_crtc_state; 980 struct ofdrm_crtc_state *ofdrm_crtc_state; 981 982 if (drm_WARN_ON(dev, !crtc_state)) 983 return NULL; 984 985 new_ofdrm_crtc_state = kzalloc(sizeof(*new_ofdrm_crtc_state), GFP_KERNEL); 986 if (!new_ofdrm_crtc_state) 987 return NULL; 988 989 ofdrm_crtc_state = to_ofdrm_crtc_state(crtc_state); 990 991 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_ofdrm_crtc_state->base); 992 new_ofdrm_crtc_state->format = ofdrm_crtc_state->format; 993 994 return &new_ofdrm_crtc_state->base; 995 } 996 997 static void ofdrm_crtc_atomic_destroy_state(struct drm_crtc *crtc, 998 struct drm_crtc_state *crtc_state) 999 { 1000 ofdrm_crtc_state_destroy(to_ofdrm_crtc_state(crtc_state)); 1001 } 1002 1003 static const struct drm_crtc_funcs ofdrm_crtc_funcs = { 1004 .reset = ofdrm_crtc_reset, 1005 .destroy = drm_crtc_cleanup, 1006 .set_config = drm_atomic_helper_set_config, 1007 .page_flip = drm_atomic_helper_page_flip, 1008 .atomic_duplicate_state = ofdrm_crtc_atomic_duplicate_state, 1009 .atomic_destroy_state = ofdrm_crtc_atomic_destroy_state, 1010 }; 1011 1012 static int ofdrm_connector_helper_get_modes(struct drm_connector *connector) 1013 { 1014 struct ofdrm_device *odev = ofdrm_device_of_dev(connector->dev); 1015 1016 return drm_connector_helper_get_modes_fixed(connector, &odev->mode); 1017 } 1018 1019 static const struct drm_connector_helper_funcs ofdrm_connector_helper_funcs = { 1020 .get_modes = ofdrm_connector_helper_get_modes, 1021 }; 1022 1023 static const struct drm_connector_funcs ofdrm_connector_funcs = { 1024 .reset = drm_atomic_helper_connector_reset, 1025 .fill_modes = drm_helper_probe_single_connector_modes, 1026 .destroy = drm_connector_cleanup, 1027 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1028 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1029 }; 1030 1031 static const struct drm_mode_config_funcs ofdrm_mode_config_funcs = { 1032 .fb_create = drm_gem_fb_create_with_dirty, 1033 .atomic_check = drm_atomic_helper_check, 1034 .atomic_commit = drm_atomic_helper_commit, 1035 }; 1036 1037 /* 1038 * Init / Cleanup 1039 */ 1040 1041 static const struct ofdrm_device_funcs ofdrm_unknown_device_funcs = { 1042 }; 1043 1044 static const struct ofdrm_device_funcs ofdrm_mach64_device_funcs = { 1045 .cmap_ioremap = ofdrm_mach64_cmap_ioremap, 1046 .cmap_write = ofdrm_mach64_cmap_write, 1047 }; 1048 1049 static const struct ofdrm_device_funcs ofdrm_rage128_device_funcs = { 1050 .cmap_ioremap = ofdrm_rage128_cmap_ioremap, 1051 .cmap_write = ofdrm_rage128_cmap_write, 1052 }; 1053 1054 static const struct ofdrm_device_funcs ofdrm_rage_m3a_device_funcs = { 1055 .cmap_ioremap = ofdrm_rage_m3a_cmap_ioremap, 1056 .cmap_write = ofdrm_rage_m3a_cmap_write, 1057 }; 1058 1059 static const struct ofdrm_device_funcs ofdrm_rage_m3b_device_funcs = { 1060 .cmap_ioremap = ofdrm_rage_m3b_cmap_ioremap, 1061 .cmap_write = ofdrm_rage_m3b_cmap_write, 1062 }; 1063 1064 static const struct ofdrm_device_funcs ofdrm_radeon_device_funcs = { 1065 .cmap_ioremap = ofdrm_radeon_cmap_ioremap, 1066 .cmap_write = ofdrm_rage128_cmap_write, /* same as Rage128 */ 1067 }; 1068 1069 static const struct ofdrm_device_funcs ofdrm_gxt2000_device_funcs = { 1070 .cmap_ioremap = ofdrm_gxt2000_cmap_ioremap, 1071 .cmap_write = ofdrm_gxt2000_cmap_write, 1072 }; 1073 1074 static const struct ofdrm_device_funcs ofdrm_avivo_device_funcs = { 1075 .cmap_ioremap = ofdrm_avivo_cmap_ioremap, 1076 .cmap_write = ofdrm_avivo_cmap_write, 1077 }; 1078 1079 static const struct ofdrm_device_funcs ofdrm_qemu_device_funcs = { 1080 .cmap_ioremap = ofdrm_qemu_cmap_ioremap, 1081 .cmap_write = ofdrm_qemu_cmap_write, 1082 }; 1083 1084 static struct drm_display_mode ofdrm_mode(unsigned int width, unsigned int height) 1085 { 1086 /* 1087 * Assume a monitor resolution of 96 dpi to 1088 * get a somewhat reasonable screen size. 1089 */ 1090 const struct drm_display_mode mode = { 1091 DRM_MODE_INIT(60, width, height, 1092 DRM_MODE_RES_MM(width, 96ul), 1093 DRM_MODE_RES_MM(height, 96ul)) 1094 }; 1095 1096 return mode; 1097 } 1098 1099 static struct ofdrm_device *ofdrm_device_create(struct drm_driver *drv, 1100 struct platform_device *pdev) 1101 { 1102 struct device_node *of_node = pdev->dev.of_node; 1103 struct ofdrm_device *odev; 1104 struct drm_device *dev; 1105 enum ofdrm_model model; 1106 bool big_endian; 1107 int width, height, depth, linebytes; 1108 const struct drm_format_info *format; 1109 u64 address; 1110 resource_size_t fb_size, fb_base, fb_pgbase, fb_pgsize; 1111 struct resource *res, *mem; 1112 void __iomem *screen_base; 1113 struct drm_plane *primary_plane; 1114 struct drm_crtc *crtc; 1115 struct drm_encoder *encoder; 1116 struct drm_connector *connector; 1117 unsigned long max_width, max_height; 1118 size_t nformats; 1119 int ret; 1120 1121 odev = devm_drm_dev_alloc(&pdev->dev, drv, struct ofdrm_device, dev); 1122 if (IS_ERR(odev)) 1123 return ERR_CAST(odev); 1124 dev = &odev->dev; 1125 platform_set_drvdata(pdev, dev); 1126 1127 ret = ofdrm_device_init_pci(odev); 1128 if (ret) 1129 return ERR_PTR(ret); 1130 1131 /* 1132 * OF display-node settings 1133 */ 1134 1135 model = display_get_model_of(dev, of_node); 1136 drm_dbg(dev, "detected model %d\n", model); 1137 1138 switch (model) { 1139 case OFDRM_MODEL_UNKNOWN: 1140 odev->funcs = &ofdrm_unknown_device_funcs; 1141 break; 1142 case OFDRM_MODEL_MACH64: 1143 odev->funcs = &ofdrm_mach64_device_funcs; 1144 break; 1145 case OFDRM_MODEL_RAGE128: 1146 odev->funcs = &ofdrm_rage128_device_funcs; 1147 break; 1148 case OFDRM_MODEL_RAGE_M3A: 1149 odev->funcs = &ofdrm_rage_m3a_device_funcs; 1150 break; 1151 case OFDRM_MODEL_RAGE_M3B: 1152 odev->funcs = &ofdrm_rage_m3b_device_funcs; 1153 break; 1154 case OFDRM_MODEL_RADEON: 1155 odev->funcs = &ofdrm_radeon_device_funcs; 1156 break; 1157 case OFDRM_MODEL_GXT2000: 1158 odev->funcs = &ofdrm_gxt2000_device_funcs; 1159 break; 1160 case OFDRM_MODEL_AVIVO: 1161 odev->funcs = &ofdrm_avivo_device_funcs; 1162 break; 1163 case OFDRM_MODEL_QEMU: 1164 odev->funcs = &ofdrm_qemu_device_funcs; 1165 break; 1166 } 1167 1168 big_endian = display_get_big_endian_of(dev, of_node); 1169 1170 width = display_get_width_of(dev, of_node); 1171 if (width < 0) 1172 return ERR_PTR(width); 1173 height = display_get_height_of(dev, of_node); 1174 if (height < 0) 1175 return ERR_PTR(height); 1176 depth = display_get_depth_of(dev, of_node); 1177 if (depth < 0) 1178 return ERR_PTR(depth); 1179 linebytes = display_get_linebytes_of(dev, of_node); 1180 if (linebytes < 0) 1181 return ERR_PTR(linebytes); 1182 1183 format = display_get_validated_format(dev, depth, big_endian); 1184 if (IS_ERR(format)) 1185 return ERR_CAST(format); 1186 if (!linebytes) { 1187 linebytes = drm_format_info_min_pitch(format, 0, width); 1188 if (drm_WARN_ON(dev, !linebytes)) 1189 return ERR_PTR(-EINVAL); 1190 } 1191 1192 fb_size = linebytes * height; 1193 1194 /* 1195 * Try to figure out the address of the framebuffer. Unfortunately, Open 1196 * Firmware doesn't provide a standard way to do so. All we can do is a 1197 * dodgy heuristic that happens to work in practice. 1198 * 1199 * On most machines, the "address" property contains what we need, though 1200 * not on Matrox cards found in IBM machines. What appears to give good 1201 * results is to go through the PCI ranges and pick one that encloses the 1202 * "address" property. If none match, we pick the largest. 1203 */ 1204 address = display_get_address_of(dev, of_node); 1205 if (address != OF_BAD_ADDR) { 1206 struct resource fb_res = DEFINE_RES_MEM(address, fb_size); 1207 1208 res = ofdrm_find_fb_resource(odev, &fb_res); 1209 if (!res) 1210 return ERR_PTR(-EINVAL); 1211 if (resource_contains(res, &fb_res)) 1212 fb_base = address; 1213 else 1214 fb_base = res->start; 1215 } else { 1216 struct resource fb_res = DEFINE_RES_MEM(0u, fb_size); 1217 1218 res = ofdrm_find_fb_resource(odev, &fb_res); 1219 if (!res) 1220 return ERR_PTR(-EINVAL); 1221 fb_base = res->start; 1222 } 1223 1224 /* 1225 * I/O resources 1226 */ 1227 1228 fb_pgbase = round_down(fb_base, PAGE_SIZE); 1229 fb_pgsize = fb_base - fb_pgbase + round_up(fb_size, PAGE_SIZE); 1230 1231 ret = devm_aperture_acquire_from_firmware(dev, fb_pgbase, fb_pgsize); 1232 if (ret) { 1233 drm_err(dev, "could not acquire memory range %pr: error %d\n", &res, ret); 1234 return ERR_PTR(ret); 1235 } 1236 1237 mem = devm_request_mem_region(&pdev->dev, fb_pgbase, fb_pgsize, drv->name); 1238 if (!mem) { 1239 drm_warn(dev, "could not acquire memory region %pr\n", &res); 1240 return ERR_PTR(-ENOMEM); 1241 } 1242 1243 screen_base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); 1244 if (!screen_base) 1245 return ERR_PTR(-ENOMEM); 1246 1247 if (odev->funcs->cmap_ioremap) { 1248 void __iomem *cmap_base = odev->funcs->cmap_ioremap(odev, of_node, fb_base); 1249 1250 if (IS_ERR(cmap_base)) { 1251 /* Don't fail; continue without colormap */ 1252 drm_warn(dev, "could not find colormap: error %ld\n", PTR_ERR(cmap_base)); 1253 } else { 1254 odev->cmap_base = cmap_base; 1255 } 1256 } 1257 1258 /* 1259 * Firmware framebuffer 1260 */ 1261 1262 iosys_map_set_vaddr_iomem(&odev->screen_base, screen_base); 1263 odev->mode = ofdrm_mode(width, height); 1264 odev->format = format; 1265 odev->pitch = linebytes; 1266 1267 drm_dbg(dev, "display mode={" DRM_MODE_FMT "}\n", DRM_MODE_ARG(&odev->mode)); 1268 drm_dbg(dev, "framebuffer format=%p4cc, size=%dx%d, linebytes=%d byte\n", 1269 &format->format, width, height, linebytes); 1270 1271 /* 1272 * Mode-setting pipeline 1273 */ 1274 1275 ret = drmm_mode_config_init(dev); 1276 if (ret) 1277 return ERR_PTR(ret); 1278 1279 max_width = max_t(unsigned long, width, DRM_SHADOW_PLANE_MAX_WIDTH); 1280 max_height = max_t(unsigned long, height, DRM_SHADOW_PLANE_MAX_HEIGHT); 1281 1282 dev->mode_config.min_width = width; 1283 dev->mode_config.max_width = max_width; 1284 dev->mode_config.min_height = height; 1285 dev->mode_config.max_height = max_height; 1286 dev->mode_config.funcs = &ofdrm_mode_config_funcs; 1287 switch (depth) { 1288 case 32: 1289 dev->mode_config.preferred_depth = 24; 1290 break; 1291 default: 1292 dev->mode_config.preferred_depth = depth; 1293 break; 1294 } 1295 dev->mode_config.quirk_addfb_prefer_host_byte_order = true; 1296 1297 /* Primary plane */ 1298 1299 nformats = drm_fb_build_fourcc_list(dev, &format->format, 1, 1300 ofdrm_primary_plane_formats, 1301 ARRAY_SIZE(ofdrm_primary_plane_formats), 1302 odev->formats, ARRAY_SIZE(odev->formats)); 1303 1304 primary_plane = &odev->primary_plane; 1305 ret = drm_universal_plane_init(dev, primary_plane, 0, &ofdrm_primary_plane_funcs, 1306 odev->formats, nformats, 1307 ofdrm_primary_plane_format_modifiers, 1308 DRM_PLANE_TYPE_PRIMARY, NULL); 1309 if (ret) 1310 return ERR_PTR(ret); 1311 drm_plane_helper_add(primary_plane, &ofdrm_primary_plane_helper_funcs); 1312 drm_plane_enable_fb_damage_clips(primary_plane); 1313 1314 /* CRTC */ 1315 1316 crtc = &odev->crtc; 1317 ret = drm_crtc_init_with_planes(dev, crtc, primary_plane, NULL, 1318 &ofdrm_crtc_funcs, NULL); 1319 if (ret) 1320 return ERR_PTR(ret); 1321 drm_crtc_helper_add(crtc, &ofdrm_crtc_helper_funcs); 1322 1323 if (odev->cmap_base) { 1324 drm_mode_crtc_set_gamma_size(crtc, OFDRM_GAMMA_LUT_SIZE); 1325 drm_crtc_enable_color_mgmt(crtc, 0, false, OFDRM_GAMMA_LUT_SIZE); 1326 } 1327 1328 /* Encoder */ 1329 1330 encoder = &odev->encoder; 1331 ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_NONE); 1332 if (ret) 1333 return ERR_PTR(ret); 1334 encoder->possible_crtcs = drm_crtc_mask(crtc); 1335 1336 /* Connector */ 1337 1338 connector = &odev->connector; 1339 ret = drm_connector_init(dev, connector, &ofdrm_connector_funcs, 1340 DRM_MODE_CONNECTOR_Unknown); 1341 if (ret) 1342 return ERR_PTR(ret); 1343 drm_connector_helper_add(connector, &ofdrm_connector_helper_funcs); 1344 drm_connector_set_panel_orientation_with_quirk(connector, 1345 DRM_MODE_PANEL_ORIENTATION_UNKNOWN, 1346 width, height); 1347 1348 ret = drm_connector_attach_encoder(connector, encoder); 1349 if (ret) 1350 return ERR_PTR(ret); 1351 1352 drm_mode_config_reset(dev); 1353 1354 return odev; 1355 } 1356 1357 /* 1358 * DRM driver 1359 */ 1360 1361 DEFINE_DRM_GEM_FOPS(ofdrm_fops); 1362 1363 static struct drm_driver ofdrm_driver = { 1364 DRM_GEM_SHMEM_DRIVER_OPS, 1365 .name = DRIVER_NAME, 1366 .desc = DRIVER_DESC, 1367 .date = DRIVER_DATE, 1368 .major = DRIVER_MAJOR, 1369 .minor = DRIVER_MINOR, 1370 .driver_features = DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET, 1371 .fops = &ofdrm_fops, 1372 }; 1373 1374 /* 1375 * Platform driver 1376 */ 1377 1378 static int ofdrm_probe(struct platform_device *pdev) 1379 { 1380 struct ofdrm_device *odev; 1381 struct drm_device *dev; 1382 int ret; 1383 1384 odev = ofdrm_device_create(&ofdrm_driver, pdev); 1385 if (IS_ERR(odev)) 1386 return PTR_ERR(odev); 1387 dev = &odev->dev; 1388 1389 ret = drm_dev_register(dev, 0); 1390 if (ret) 1391 return ret; 1392 1393 /* 1394 * FIXME: 24-bit color depth does not work reliably with a 32-bpp 1395 * value. Force the bpp value of the scanout buffer's format. 1396 */ 1397 drm_fbdev_generic_setup(dev, drm_format_info_bpp(odev->format, 0)); 1398 1399 return 0; 1400 } 1401 1402 static int ofdrm_remove(struct platform_device *pdev) 1403 { 1404 struct drm_device *dev = platform_get_drvdata(pdev); 1405 1406 drm_dev_unplug(dev); 1407 1408 return 0; 1409 } 1410 1411 static const struct of_device_id ofdrm_of_match_display[] = { 1412 { .compatible = "display", }, 1413 { }, 1414 }; 1415 MODULE_DEVICE_TABLE(of, ofdrm_of_match_display); 1416 1417 static struct platform_driver ofdrm_platform_driver = { 1418 .driver = { 1419 .name = "of-display", 1420 .of_match_table = ofdrm_of_match_display, 1421 }, 1422 .probe = ofdrm_probe, 1423 .remove = ofdrm_remove, 1424 }; 1425 1426 module_platform_driver(ofdrm_platform_driver); 1427 1428 MODULE_DESCRIPTION(DRIVER_DESC); 1429 MODULE_LICENSE("GPL"); 1430