1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2012 Texas Instruments
4  * Author: Rob Clark <robdclark@gmail.com>
5  */
6 
7 #ifndef __TILCDC_DRV_H__
8 #define __TILCDC_DRV_H__
9 
10 #include <linux/cpufreq.h>
11 #include <linux/irqreturn.h>
12 
13 #include <drm/drm_print.h>
14 
15 struct clk;
16 struct workqueue_struct;
17 
18 struct drm_connector;
19 struct drm_connector_helper_funcs;
20 struct drm_crtc;
21 struct drm_device;
22 struct drm_display_mode;
23 struct drm_encoder;
24 struct drm_framebuffer;
25 struct drm_minor;
26 struct drm_pending_vblank_event;
27 struct drm_plane;
28 
29 /* Defaulting to pixel clock defined on AM335x */
30 #define TILCDC_DEFAULT_MAX_PIXELCLOCK  126000
31 /* Defaulting to max width as defined on AM335x */
32 #define TILCDC_DEFAULT_MAX_WIDTH  2048
33 /*
34  * This may need some tweaking, but want to allow at least 1280x1024@60
35  * with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to
36  * be supportable
37  */
38 #define TILCDC_DEFAULT_MAX_BANDWIDTH  (1280*1024*60)
39 
40 
41 struct tilcdc_drm_private {
42 	void __iomem *mmio;
43 
44 	struct clk *clk;         /* functional clock */
45 	int rev;                 /* IP revision */
46 
47 	/* don't attempt resolutions w/ higher W * H * Hz: */
48 	uint32_t max_bandwidth;
49 	/*
50 	 * Pixel Clock will be restricted to some value as
51 	 * defined in the device datasheet measured in KHz
52 	 */
53 	uint32_t max_pixelclock;
54 	/*
55 	 * Max allowable width is limited on a per device basis
56 	 * measured in pixels
57 	 */
58 	uint32_t max_width;
59 
60 	/* Supported pixel formats */
61 	const uint32_t *pixelformats;
62 	uint32_t num_pixelformats;
63 
64 #ifdef CONFIG_CPU_FREQ
65 	struct notifier_block freq_transition;
66 #endif
67 
68 	struct workqueue_struct *wq;
69 
70 	struct drm_crtc *crtc;
71 
72 	unsigned int num_encoders;
73 	struct drm_encoder *encoders[8];
74 
75 	unsigned int num_connectors;
76 	struct drm_connector *connectors[8];
77 
78 	struct drm_encoder *external_encoder;
79 	struct drm_connector *external_connector;
80 
81 	bool is_registered;
82 	bool is_componentized;
83 };
84 
85 /* Sub-module for display.  Since we don't know at compile time what panels
86  * or display adapter(s) might be present (for ex, off chip dvi/tfp410,
87  * hdmi encoder, various lcd panels), the connector/encoder(s) are split into
88  * separate drivers.  If they are probed and found to be present, they
89  * register themselves with tilcdc_register_module().
90  */
91 struct tilcdc_module;
92 
93 struct tilcdc_module_ops {
94 	/* create appropriate encoders/connectors: */
95 	int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev);
96 #ifdef CONFIG_DEBUG_FS
97 	/* create debugfs nodes (can be NULL): */
98 	int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor);
99 #endif
100 };
101 
102 struct tilcdc_module {
103 	const char *name;
104 	struct list_head list;
105 	const struct tilcdc_module_ops *funcs;
106 };
107 
108 void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
109 		const struct tilcdc_module_ops *funcs);
110 void tilcdc_module_cleanup(struct tilcdc_module *mod);
111 
112 /* Panel config that needs to be set in the crtc, but is not coming from
113  * the mode timings.  The display module is expected to call
114  * tilcdc_crtc_set_panel_info() to set this during modeset.
115  */
116 struct tilcdc_panel_info {
117 
118 	/* AC Bias Pin Frequency */
119 	uint32_t ac_bias;
120 
121 	/* AC Bias Pin Transitions per Interrupt */
122 	uint32_t ac_bias_intrpt;
123 
124 	/* DMA burst size */
125 	uint32_t dma_burst_sz;
126 
127 	/* Bits per pixel */
128 	uint32_t bpp;
129 
130 	/* FIFO DMA Request Delay */
131 	uint32_t fdd;
132 
133 	/* TFT Alternative Signal Mapping (Only for active) */
134 	bool tft_alt_mode;
135 
136 	/* Invert pixel clock */
137 	bool invert_pxl_clk;
138 
139 	/* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
140 	uint32_t sync_edge;
141 
142 	/* Horizontal and Vertical Sync: Control: 0=ignore */
143 	uint32_t sync_ctrl;
144 
145 	/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
146 	uint32_t raster_order;
147 
148 	/* DMA FIFO threshold */
149 	uint32_t fifo_th;
150 };
151 
152 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
153 
154 int tilcdc_crtc_create(struct drm_device *dev);
155 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc);
156 void tilcdc_crtc_update_clk(struct drm_crtc *crtc);
157 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
158 		const struct tilcdc_panel_info *info);
159 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
160 					bool simulate_vesa_sync);
161 int tilcdc_crtc_max_width(struct drm_crtc *crtc);
162 void tilcdc_crtc_shutdown(struct drm_crtc *crtc);
163 int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
164 		struct drm_framebuffer *fb,
165 		struct drm_pending_vblank_event *event);
166 
167 int tilcdc_plane_init(struct drm_device *dev, struct drm_plane *plane);
168 
169 #endif /* __TILCDC_DRV_H__ */
170