1 /* 2 * Copyright (C) 2012 Texas Instruments 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __TILCDC_DRV_H__ 19 #define __TILCDC_DRV_H__ 20 21 #include <linux/clk.h> 22 #include <linux/cpufreq.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/slab.h> 28 #include <linux/of.h> 29 #include <linux/of_device.h> 30 #include <linux/list.h> 31 32 #include <drm/drmP.h> 33 #include <drm/drm_crtc_helper.h> 34 #include <drm/drm_gem_cma_helper.h> 35 #include <drm/drm_fb_cma_helper.h> 36 37 /* Defaulting to pixel clock defined on AM335x */ 38 #define TILCDC_DEFAULT_MAX_PIXELCLOCK 126000 39 /* Defaulting to max width as defined on AM335x */ 40 #define TILCDC_DEFAULT_MAX_WIDTH 2048 41 /* 42 * This may need some tweaking, but want to allow at least 1280x1024@60 43 * with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to 44 * be supportable 45 */ 46 #define TILCDC_DEFAULT_MAX_BANDWIDTH (1280*1024*60) 47 48 49 struct tilcdc_drm_private { 50 void __iomem *mmio; 51 52 struct clk *clk; /* functional clock */ 53 int rev; /* IP revision */ 54 55 /* don't attempt resolutions w/ higher W * H * Hz: */ 56 uint32_t max_bandwidth; 57 /* 58 * Pixel Clock will be restricted to some value as 59 * defined in the device datasheet measured in KHz 60 */ 61 uint32_t max_pixelclock; 62 /* 63 * Max allowable width is limited on a per device basis 64 * measured in pixels 65 */ 66 uint32_t max_width; 67 68 /* Supported pixel formats */ 69 const uint32_t *pixelformats; 70 uint32_t num_pixelformats; 71 72 /* The context for pm susped/resume cycle is stored here */ 73 struct drm_atomic_state *saved_state; 74 75 #ifdef CONFIG_CPU_FREQ 76 struct notifier_block freq_transition; 77 #endif 78 79 struct workqueue_struct *wq; 80 81 struct drm_fbdev_cma *fbdev; 82 83 struct drm_crtc *crtc; 84 85 unsigned int num_encoders; 86 struct drm_encoder *encoders[8]; 87 88 unsigned int num_connectors; 89 struct drm_connector *connectors[8]; 90 const struct drm_connector_helper_funcs *connector_funcs[8]; 91 92 bool is_componentized; 93 }; 94 95 /* Sub-module for display. Since we don't know at compile time what panels 96 * or display adapter(s) might be present (for ex, off chip dvi/tfp410, 97 * hdmi encoder, various lcd panels), the connector/encoder(s) are split into 98 * separate drivers. If they are probed and found to be present, they 99 * register themselves with tilcdc_register_module(). 100 */ 101 struct tilcdc_module; 102 103 struct tilcdc_module_ops { 104 /* create appropriate encoders/connectors: */ 105 int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev); 106 #ifdef CONFIG_DEBUG_FS 107 /* create debugfs nodes (can be NULL): */ 108 int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor); 109 /* cleanup debugfs nodes (can be NULL): */ 110 void (*debugfs_cleanup)(struct tilcdc_module *mod, struct drm_minor *minor); 111 #endif 112 }; 113 114 struct tilcdc_module { 115 const char *name; 116 struct list_head list; 117 const struct tilcdc_module_ops *funcs; 118 }; 119 120 void tilcdc_module_init(struct tilcdc_module *mod, const char *name, 121 const struct tilcdc_module_ops *funcs); 122 void tilcdc_module_cleanup(struct tilcdc_module *mod); 123 124 /* Panel config that needs to be set in the crtc, but is not coming from 125 * the mode timings. The display module is expected to call 126 * tilcdc_crtc_set_panel_info() to set this during modeset. 127 */ 128 struct tilcdc_panel_info { 129 130 /* AC Bias Pin Frequency */ 131 uint32_t ac_bias; 132 133 /* AC Bias Pin Transitions per Interrupt */ 134 uint32_t ac_bias_intrpt; 135 136 /* DMA burst size */ 137 uint32_t dma_burst_sz; 138 139 /* Bits per pixel */ 140 uint32_t bpp; 141 142 /* FIFO DMA Request Delay */ 143 uint32_t fdd; 144 145 /* TFT Alternative Signal Mapping (Only for active) */ 146 bool tft_alt_mode; 147 148 /* Invert pixel clock */ 149 bool invert_pxl_clk; 150 151 /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ 152 uint32_t sync_edge; 153 154 /* Horizontal and Vertical Sync: Control: 0=ignore */ 155 uint32_t sync_ctrl; 156 157 /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ 158 uint32_t raster_order; 159 160 /* DMA FIFO threshold */ 161 uint32_t fifo_th; 162 }; 163 164 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 165 166 struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev); 167 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc); 168 void tilcdc_crtc_update_clk(struct drm_crtc *crtc); 169 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, 170 const struct tilcdc_panel_info *info); 171 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc, 172 bool simulate_vesa_sync); 173 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode); 174 int tilcdc_crtc_max_width(struct drm_crtc *crtc); 175 void tilcdc_crtc_disable(struct drm_crtc *crtc); 176 int tilcdc_crtc_update_fb(struct drm_crtc *crtc, 177 struct drm_framebuffer *fb, 178 struct drm_pending_vblank_event *event); 179 180 int tilcdc_plane_init(struct drm_device *dev, struct drm_plane *plane); 181 182 #endif /* __TILCDC_DRV_H__ */ 183