1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Texas Instruments 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #ifndef __TILCDC_DRV_H__ 8 #define __TILCDC_DRV_H__ 9 10 #include <linux/cpufreq.h> 11 #include <linux/irqreturn.h> 12 13 #include <drm/drm_print.h> 14 15 struct clk; 16 struct workqueue_struct; 17 18 struct drm_connector; 19 struct drm_connector_helper_funcs; 20 struct drm_crtc; 21 struct drm_device; 22 struct drm_display_mode; 23 struct drm_encoder; 24 struct drm_framebuffer; 25 struct drm_minor; 26 struct drm_pending_vblank_event; 27 struct drm_plane; 28 29 /* Defaulting to pixel clock defined on AM335x */ 30 #define TILCDC_DEFAULT_MAX_PIXELCLOCK 126000 31 /* Maximum display width for LCDC V1 */ 32 #define TILCDC_DEFAULT_MAX_WIDTH_V1 1024 33 /* ... and for LCDC V2 found on AM335x: */ 34 #define TILCDC_DEFAULT_MAX_WIDTH_V2 2048 35 /* 36 * This may need some tweaking, but want to allow at least 1280x1024@60 37 * with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to 38 * be supportable 39 */ 40 #define TILCDC_DEFAULT_MAX_BANDWIDTH (1280*1024*60) 41 42 43 struct tilcdc_drm_private { 44 void __iomem *mmio; 45 46 struct clk *clk; /* functional clock */ 47 int rev; /* IP revision */ 48 49 /* don't attempt resolutions w/ higher W * H * Hz: */ 50 uint32_t max_bandwidth; 51 /* 52 * Pixel Clock will be restricted to some value as 53 * defined in the device datasheet measured in KHz 54 */ 55 uint32_t max_pixelclock; 56 /* 57 * Max allowable width is limited on a per device basis 58 * measured in pixels 59 */ 60 uint32_t max_width; 61 62 /* Supported pixel formats */ 63 const uint32_t *pixelformats; 64 uint32_t num_pixelformats; 65 66 #ifdef CONFIG_CPU_FREQ 67 struct notifier_block freq_transition; 68 #endif 69 70 struct workqueue_struct *wq; 71 72 struct drm_crtc *crtc; 73 74 unsigned int num_encoders; 75 struct drm_encoder *encoders[8]; 76 77 unsigned int num_connectors; 78 struct drm_connector *connectors[8]; 79 80 struct drm_encoder *external_encoder; 81 struct drm_connector *external_connector; 82 83 bool is_registered; 84 bool is_componentized; 85 }; 86 87 /* Sub-module for display. Since we don't know at compile time what panels 88 * or display adapter(s) might be present (for ex, off chip dvi/tfp410, 89 * hdmi encoder, various lcd panels), the connector/encoder(s) are split into 90 * separate drivers. If they are probed and found to be present, they 91 * register themselves with tilcdc_register_module(). 92 */ 93 struct tilcdc_module; 94 95 struct tilcdc_module_ops { 96 /* create appropriate encoders/connectors: */ 97 int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev); 98 #ifdef CONFIG_DEBUG_FS 99 /* create debugfs nodes (can be NULL): */ 100 int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor); 101 #endif 102 }; 103 104 struct tilcdc_module { 105 const char *name; 106 struct list_head list; 107 const struct tilcdc_module_ops *funcs; 108 }; 109 110 void tilcdc_module_init(struct tilcdc_module *mod, const char *name, 111 const struct tilcdc_module_ops *funcs); 112 void tilcdc_module_cleanup(struct tilcdc_module *mod); 113 114 /* Panel config that needs to be set in the crtc, but is not coming from 115 * the mode timings. The display module is expected to call 116 * tilcdc_crtc_set_panel_info() to set this during modeset. 117 */ 118 struct tilcdc_panel_info { 119 120 /* AC Bias Pin Frequency */ 121 uint32_t ac_bias; 122 123 /* AC Bias Pin Transitions per Interrupt */ 124 uint32_t ac_bias_intrpt; 125 126 /* DMA burst size */ 127 uint32_t dma_burst_sz; 128 129 /* Bits per pixel */ 130 uint32_t bpp; 131 132 /* FIFO DMA Request Delay */ 133 uint32_t fdd; 134 135 /* TFT Alternative Signal Mapping (Only for active) */ 136 bool tft_alt_mode; 137 138 /* Invert pixel clock */ 139 bool invert_pxl_clk; 140 141 /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ 142 uint32_t sync_edge; 143 144 /* Horizontal and Vertical Sync: Control: 0=ignore */ 145 uint32_t sync_ctrl; 146 147 /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ 148 uint32_t raster_order; 149 150 /* DMA FIFO threshold */ 151 uint32_t fifo_th; 152 }; 153 154 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 155 156 int tilcdc_crtc_create(struct drm_device *dev); 157 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc); 158 void tilcdc_crtc_update_clk(struct drm_crtc *crtc); 159 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, 160 const struct tilcdc_panel_info *info); 161 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc, 162 bool simulate_vesa_sync); 163 void tilcdc_crtc_shutdown(struct drm_crtc *crtc); 164 int tilcdc_crtc_update_fb(struct drm_crtc *crtc, 165 struct drm_framebuffer *fb, 166 struct drm_pending_vblank_event *event); 167 168 int tilcdc_plane_init(struct drm_device *dev, struct drm_plane *plane); 169 170 #endif /* __TILCDC_DRV_H__ */ 171