1 /* 2 * Copyright (C) 2012 Texas Instruments 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 /* LCDC DRM driver, based on da8xx-fb */ 19 20 #include <linux/component.h> 21 #include <linux/pinctrl/consumer.h> 22 #include <linux/suspend.h> 23 24 #include "tilcdc_drv.h" 25 #include "tilcdc_regs.h" 26 #include "tilcdc_tfp410.h" 27 #include "tilcdc_panel.h" 28 #include "tilcdc_external.h" 29 30 #include "drm_fb_helper.h" 31 32 static LIST_HEAD(module_list); 33 34 void tilcdc_module_init(struct tilcdc_module *mod, const char *name, 35 const struct tilcdc_module_ops *funcs) 36 { 37 mod->name = name; 38 mod->funcs = funcs; 39 INIT_LIST_HEAD(&mod->list); 40 list_add(&mod->list, &module_list); 41 } 42 43 void tilcdc_module_cleanup(struct tilcdc_module *mod) 44 { 45 list_del(&mod->list); 46 } 47 48 static struct of_device_id tilcdc_of_match[]; 49 50 static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev, 51 struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd) 52 { 53 return drm_fb_cma_create(dev, file_priv, mode_cmd); 54 } 55 56 static void tilcdc_fb_output_poll_changed(struct drm_device *dev) 57 { 58 struct tilcdc_drm_private *priv = dev->dev_private; 59 drm_fbdev_cma_hotplug_event(priv->fbdev); 60 } 61 62 static const struct drm_mode_config_funcs mode_config_funcs = { 63 .fb_create = tilcdc_fb_create, 64 .output_poll_changed = tilcdc_fb_output_poll_changed, 65 }; 66 67 static int modeset_init(struct drm_device *dev) 68 { 69 struct tilcdc_drm_private *priv = dev->dev_private; 70 struct tilcdc_module *mod; 71 72 drm_mode_config_init(dev); 73 74 priv->crtc = tilcdc_crtc_create(dev); 75 76 list_for_each_entry(mod, &module_list, list) { 77 DBG("loading module: %s", mod->name); 78 mod->funcs->modeset_init(mod, dev); 79 } 80 81 dev->mode_config.min_width = 0; 82 dev->mode_config.min_height = 0; 83 dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc); 84 dev->mode_config.max_height = 2048; 85 dev->mode_config.funcs = &mode_config_funcs; 86 87 return 0; 88 } 89 90 #ifdef CONFIG_CPU_FREQ 91 static int cpufreq_transition(struct notifier_block *nb, 92 unsigned long val, void *data) 93 { 94 struct tilcdc_drm_private *priv = container_of(nb, 95 struct tilcdc_drm_private, freq_transition); 96 if (val == CPUFREQ_POSTCHANGE) { 97 if (priv->lcd_fck_rate != clk_get_rate(priv->clk)) { 98 priv->lcd_fck_rate = clk_get_rate(priv->clk); 99 tilcdc_crtc_update_clk(priv->crtc); 100 } 101 } 102 103 return 0; 104 } 105 #endif 106 107 /* 108 * DRM operations: 109 */ 110 111 static int tilcdc_unload(struct drm_device *dev) 112 { 113 struct tilcdc_drm_private *priv = dev->dev_private; 114 115 tilcdc_crtc_dpms(priv->crtc, DRM_MODE_DPMS_OFF); 116 117 tilcdc_remove_external_encoders(dev); 118 119 drm_fbdev_cma_fini(priv->fbdev); 120 drm_kms_helper_poll_fini(dev); 121 drm_mode_config_cleanup(dev); 122 drm_vblank_cleanup(dev); 123 124 pm_runtime_get_sync(dev->dev); 125 drm_irq_uninstall(dev); 126 pm_runtime_put_sync(dev->dev); 127 128 #ifdef CONFIG_CPU_FREQ 129 cpufreq_unregister_notifier(&priv->freq_transition, 130 CPUFREQ_TRANSITION_NOTIFIER); 131 #endif 132 133 if (priv->clk) 134 clk_put(priv->clk); 135 136 if (priv->mmio) 137 iounmap(priv->mmio); 138 139 flush_workqueue(priv->wq); 140 destroy_workqueue(priv->wq); 141 142 dev->dev_private = NULL; 143 144 pm_runtime_disable(dev->dev); 145 146 return 0; 147 } 148 149 static size_t tilcdc_num_regs(void); 150 151 static int tilcdc_load(struct drm_device *dev, unsigned long flags) 152 { 153 struct platform_device *pdev = dev->platformdev; 154 struct device_node *node = pdev->dev.of_node; 155 struct tilcdc_drm_private *priv; 156 struct tilcdc_module *mod; 157 struct resource *res; 158 u32 bpp = 0; 159 int ret; 160 161 priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL); 162 if (priv) 163 priv->saved_register = 164 devm_kcalloc(dev->dev, tilcdc_num_regs(), 165 sizeof(*priv->saved_register), GFP_KERNEL); 166 if (!priv || !priv->saved_register) { 167 dev_err(dev->dev, "failed to allocate private data\n"); 168 return -ENOMEM; 169 } 170 171 dev->dev_private = priv; 172 173 priv->is_componentized = 174 tilcdc_get_external_components(dev->dev, NULL) > 0; 175 176 priv->wq = alloc_ordered_workqueue("tilcdc", 0); 177 if (!priv->wq) { 178 ret = -ENOMEM; 179 goto fail_unset_priv; 180 } 181 182 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 183 if (!res) { 184 dev_err(dev->dev, "failed to get memory resource\n"); 185 ret = -EINVAL; 186 goto fail_free_wq; 187 } 188 189 priv->mmio = ioremap_nocache(res->start, resource_size(res)); 190 if (!priv->mmio) { 191 dev_err(dev->dev, "failed to ioremap\n"); 192 ret = -ENOMEM; 193 goto fail_free_wq; 194 } 195 196 priv->clk = clk_get(dev->dev, "fck"); 197 if (IS_ERR(priv->clk)) { 198 dev_err(dev->dev, "failed to get functional clock\n"); 199 ret = -ENODEV; 200 goto fail_iounmap; 201 } 202 203 #ifdef CONFIG_CPU_FREQ 204 priv->lcd_fck_rate = clk_get_rate(priv->clk); 205 priv->freq_transition.notifier_call = cpufreq_transition; 206 ret = cpufreq_register_notifier(&priv->freq_transition, 207 CPUFREQ_TRANSITION_NOTIFIER); 208 if (ret) { 209 dev_err(dev->dev, "failed to register cpufreq notifier\n"); 210 goto fail_put_clk; 211 } 212 #endif 213 214 if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth)) 215 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH; 216 217 DBG("Maximum Bandwidth Value %d", priv->max_bandwidth); 218 219 if (of_property_read_u32(node, "ti,max-width", &priv->max_width)) 220 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH; 221 222 DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width); 223 224 if (of_property_read_u32(node, "ti,max-pixelclock", 225 &priv->max_pixelclock)) 226 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK; 227 228 DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock); 229 230 pm_runtime_enable(dev->dev); 231 232 /* Determine LCD IP Version */ 233 pm_runtime_get_sync(dev->dev); 234 switch (tilcdc_read(dev, LCDC_PID_REG)) { 235 case 0x4c100102: 236 priv->rev = 1; 237 break; 238 case 0x4f200800: 239 case 0x4f201000: 240 priv->rev = 2; 241 break; 242 default: 243 dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, " 244 "defaulting to LCD revision 1\n", 245 tilcdc_read(dev, LCDC_PID_REG)); 246 priv->rev = 1; 247 break; 248 } 249 250 pm_runtime_put_sync(dev->dev); 251 252 ret = modeset_init(dev); 253 if (ret < 0) { 254 dev_err(dev->dev, "failed to initialize mode setting\n"); 255 goto fail_cpufreq_unregister; 256 } 257 258 platform_set_drvdata(pdev, dev); 259 260 if (priv->is_componentized) { 261 ret = component_bind_all(dev->dev, dev); 262 if (ret < 0) 263 goto fail_mode_config_cleanup; 264 265 ret = tilcdc_add_external_encoders(dev, &bpp); 266 if (ret < 0) 267 goto fail_component_cleanup; 268 } 269 270 if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) { 271 dev_err(dev->dev, "no encoders/connectors found\n"); 272 ret = -ENXIO; 273 goto fail_external_cleanup; 274 } 275 276 ret = drm_vblank_init(dev, 1); 277 if (ret < 0) { 278 dev_err(dev->dev, "failed to initialize vblank\n"); 279 goto fail_external_cleanup; 280 } 281 282 pm_runtime_get_sync(dev->dev); 283 ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0)); 284 pm_runtime_put_sync(dev->dev); 285 if (ret < 0) { 286 dev_err(dev->dev, "failed to install IRQ handler\n"); 287 goto fail_vblank_cleanup; 288 } 289 290 list_for_each_entry(mod, &module_list, list) { 291 DBG("%s: preferred_bpp: %d", mod->name, mod->preferred_bpp); 292 bpp = mod->preferred_bpp; 293 if (bpp > 0) 294 break; 295 } 296 297 drm_helper_disable_unused_functions(dev); 298 priv->fbdev = drm_fbdev_cma_init(dev, bpp, 299 dev->mode_config.num_crtc, 300 dev->mode_config.num_connector); 301 if (IS_ERR(priv->fbdev)) { 302 ret = PTR_ERR(priv->fbdev); 303 goto fail_irq_uninstall; 304 } 305 306 drm_kms_helper_poll_init(dev); 307 308 return 0; 309 310 fail_irq_uninstall: 311 pm_runtime_get_sync(dev->dev); 312 drm_irq_uninstall(dev); 313 pm_runtime_put_sync(dev->dev); 314 315 fail_vblank_cleanup: 316 drm_vblank_cleanup(dev); 317 318 fail_mode_config_cleanup: 319 drm_mode_config_cleanup(dev); 320 321 fail_component_cleanup: 322 if (priv->is_componentized) 323 component_unbind_all(dev->dev, dev); 324 325 fail_external_cleanup: 326 tilcdc_remove_external_encoders(dev); 327 328 fail_cpufreq_unregister: 329 pm_runtime_disable(dev->dev); 330 #ifdef CONFIG_CPU_FREQ 331 cpufreq_unregister_notifier(&priv->freq_transition, 332 CPUFREQ_TRANSITION_NOTIFIER); 333 334 fail_put_clk: 335 #endif 336 clk_put(priv->clk); 337 338 fail_iounmap: 339 iounmap(priv->mmio); 340 341 fail_free_wq: 342 flush_workqueue(priv->wq); 343 destroy_workqueue(priv->wq); 344 345 fail_unset_priv: 346 dev->dev_private = NULL; 347 348 return ret; 349 } 350 351 static void tilcdc_lastclose(struct drm_device *dev) 352 { 353 struct tilcdc_drm_private *priv = dev->dev_private; 354 drm_fbdev_cma_restore_mode(priv->fbdev); 355 } 356 357 static irqreturn_t tilcdc_irq(int irq, void *arg) 358 { 359 struct drm_device *dev = arg; 360 struct tilcdc_drm_private *priv = dev->dev_private; 361 return tilcdc_crtc_irq(priv->crtc); 362 } 363 364 static void tilcdc_irq_preinstall(struct drm_device *dev) 365 { 366 tilcdc_clear_irqstatus(dev, 0xffffffff); 367 } 368 369 static int tilcdc_irq_postinstall(struct drm_device *dev) 370 { 371 struct tilcdc_drm_private *priv = dev->dev_private; 372 373 /* enable FIFO underflow irq: */ 374 if (priv->rev == 1) { 375 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_UNDERFLOW_INT_ENA); 376 } else { 377 tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, 378 LCDC_V2_UNDERFLOW_INT_ENA | 379 LCDC_V2_END_OF_FRAME0_INT_ENA | 380 LCDC_FRAME_DONE | LCDC_SYNC_LOST); 381 } 382 383 return 0; 384 } 385 386 static void tilcdc_irq_uninstall(struct drm_device *dev) 387 { 388 struct tilcdc_drm_private *priv = dev->dev_private; 389 390 /* disable irqs that we might have enabled: */ 391 if (priv->rev == 1) { 392 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, 393 LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA); 394 tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_V1_END_OF_FRAME_INT_ENA); 395 } else { 396 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, 397 LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA | 398 LCDC_V2_END_OF_FRAME0_INT_ENA | 399 LCDC_FRAME_DONE | LCDC_SYNC_LOST); 400 } 401 } 402 403 static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe) 404 { 405 return 0; 406 } 407 408 static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe) 409 { 410 return; 411 } 412 413 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_PM_SLEEP) 414 static const struct { 415 const char *name; 416 uint8_t rev; 417 uint8_t save; 418 uint32_t reg; 419 } registers[] = { 420 #define REG(rev, save, reg) { #reg, rev, save, reg } 421 /* exists in revision 1: */ 422 REG(1, false, LCDC_PID_REG), 423 REG(1, true, LCDC_CTRL_REG), 424 REG(1, false, LCDC_STAT_REG), 425 REG(1, true, LCDC_RASTER_CTRL_REG), 426 REG(1, true, LCDC_RASTER_TIMING_0_REG), 427 REG(1, true, LCDC_RASTER_TIMING_1_REG), 428 REG(1, true, LCDC_RASTER_TIMING_2_REG), 429 REG(1, true, LCDC_DMA_CTRL_REG), 430 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG), 431 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG), 432 REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG), 433 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG), 434 /* new in revision 2: */ 435 REG(2, false, LCDC_RAW_STAT_REG), 436 REG(2, false, LCDC_MASKED_STAT_REG), 437 REG(2, true, LCDC_INT_ENABLE_SET_REG), 438 REG(2, false, LCDC_INT_ENABLE_CLR_REG), 439 REG(2, false, LCDC_END_OF_INT_IND_REG), 440 REG(2, true, LCDC_CLK_ENABLE_REG), 441 #undef REG 442 }; 443 444 static size_t tilcdc_num_regs(void) 445 { 446 return ARRAY_SIZE(registers); 447 } 448 #else 449 static size_t tilcdc_num_regs(void) 450 { 451 return 0; 452 } 453 #endif 454 455 #ifdef CONFIG_DEBUG_FS 456 static int tilcdc_regs_show(struct seq_file *m, void *arg) 457 { 458 struct drm_info_node *node = (struct drm_info_node *) m->private; 459 struct drm_device *dev = node->minor->dev; 460 struct tilcdc_drm_private *priv = dev->dev_private; 461 unsigned i; 462 463 pm_runtime_get_sync(dev->dev); 464 465 seq_printf(m, "revision: %d\n", priv->rev); 466 467 for (i = 0; i < ARRAY_SIZE(registers); i++) 468 if (priv->rev >= registers[i].rev) 469 seq_printf(m, "%s:\t %08x\n", registers[i].name, 470 tilcdc_read(dev, registers[i].reg)); 471 472 pm_runtime_put_sync(dev->dev); 473 474 return 0; 475 } 476 477 static int tilcdc_mm_show(struct seq_file *m, void *arg) 478 { 479 struct drm_info_node *node = (struct drm_info_node *) m->private; 480 struct drm_device *dev = node->minor->dev; 481 return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm); 482 } 483 484 static struct drm_info_list tilcdc_debugfs_list[] = { 485 { "regs", tilcdc_regs_show, 0 }, 486 { "mm", tilcdc_mm_show, 0 }, 487 { "fb", drm_fb_cma_debugfs_show, 0 }, 488 }; 489 490 static int tilcdc_debugfs_init(struct drm_minor *minor) 491 { 492 struct drm_device *dev = minor->dev; 493 struct tilcdc_module *mod; 494 int ret; 495 496 ret = drm_debugfs_create_files(tilcdc_debugfs_list, 497 ARRAY_SIZE(tilcdc_debugfs_list), 498 minor->debugfs_root, minor); 499 500 list_for_each_entry(mod, &module_list, list) 501 if (mod->funcs->debugfs_init) 502 mod->funcs->debugfs_init(mod, minor); 503 504 if (ret) { 505 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n"); 506 return ret; 507 } 508 509 return ret; 510 } 511 512 static void tilcdc_debugfs_cleanup(struct drm_minor *minor) 513 { 514 struct tilcdc_module *mod; 515 drm_debugfs_remove_files(tilcdc_debugfs_list, 516 ARRAY_SIZE(tilcdc_debugfs_list), minor); 517 518 list_for_each_entry(mod, &module_list, list) 519 if (mod->funcs->debugfs_cleanup) 520 mod->funcs->debugfs_cleanup(mod, minor); 521 } 522 #endif 523 524 static const struct file_operations fops = { 525 .owner = THIS_MODULE, 526 .open = drm_open, 527 .release = drm_release, 528 .unlocked_ioctl = drm_ioctl, 529 #ifdef CONFIG_COMPAT 530 .compat_ioctl = drm_compat_ioctl, 531 #endif 532 .poll = drm_poll, 533 .read = drm_read, 534 .llseek = no_llseek, 535 .mmap = drm_gem_cma_mmap, 536 }; 537 538 static struct drm_driver tilcdc_driver = { 539 .driver_features = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET | 540 DRIVER_PRIME), 541 .load = tilcdc_load, 542 .unload = tilcdc_unload, 543 .lastclose = tilcdc_lastclose, 544 .irq_handler = tilcdc_irq, 545 .irq_preinstall = tilcdc_irq_preinstall, 546 .irq_postinstall = tilcdc_irq_postinstall, 547 .irq_uninstall = tilcdc_irq_uninstall, 548 .get_vblank_counter = drm_vblank_no_hw_counter, 549 .enable_vblank = tilcdc_enable_vblank, 550 .disable_vblank = tilcdc_disable_vblank, 551 .gem_free_object_unlocked = drm_gem_cma_free_object, 552 .gem_vm_ops = &drm_gem_cma_vm_ops, 553 .dumb_create = drm_gem_cma_dumb_create, 554 .dumb_map_offset = drm_gem_cma_dumb_map_offset, 555 .dumb_destroy = drm_gem_dumb_destroy, 556 557 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 558 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 559 .gem_prime_import = drm_gem_prime_import, 560 .gem_prime_export = drm_gem_prime_export, 561 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, 562 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, 563 .gem_prime_vmap = drm_gem_cma_prime_vmap, 564 .gem_prime_vunmap = drm_gem_cma_prime_vunmap, 565 .gem_prime_mmap = drm_gem_cma_prime_mmap, 566 #ifdef CONFIG_DEBUG_FS 567 .debugfs_init = tilcdc_debugfs_init, 568 .debugfs_cleanup = tilcdc_debugfs_cleanup, 569 #endif 570 .fops = &fops, 571 .name = "tilcdc", 572 .desc = "TI LCD Controller DRM", 573 .date = "20121205", 574 .major = 1, 575 .minor = 0, 576 }; 577 578 /* 579 * Power management: 580 */ 581 582 #ifdef CONFIG_PM_SLEEP 583 static int tilcdc_pm_suspend(struct device *dev) 584 { 585 struct drm_device *ddev = dev_get_drvdata(dev); 586 struct tilcdc_drm_private *priv = ddev->dev_private; 587 unsigned i, n = 0; 588 589 drm_kms_helper_poll_disable(ddev); 590 591 /* Select sleep pin state */ 592 pinctrl_pm_select_sleep_state(dev); 593 594 if (pm_runtime_suspended(dev)) { 595 priv->ctx_valid = false; 596 return 0; 597 } 598 599 /* Disable the LCDC controller, to avoid locking up the PRCM */ 600 tilcdc_crtc_dpms(priv->crtc, DRM_MODE_DPMS_OFF); 601 602 /* Save register state: */ 603 for (i = 0; i < ARRAY_SIZE(registers); i++) 604 if (registers[i].save && (priv->rev >= registers[i].rev)) 605 priv->saved_register[n++] = tilcdc_read(ddev, registers[i].reg); 606 607 priv->ctx_valid = true; 608 609 return 0; 610 } 611 612 static int tilcdc_pm_resume(struct device *dev) 613 { 614 struct drm_device *ddev = dev_get_drvdata(dev); 615 struct tilcdc_drm_private *priv = ddev->dev_private; 616 unsigned i, n = 0; 617 618 /* Select default pin state */ 619 pinctrl_pm_select_default_state(dev); 620 621 if (priv->ctx_valid == true) { 622 /* Restore register state: */ 623 for (i = 0; i < ARRAY_SIZE(registers); i++) 624 if (registers[i].save && 625 (priv->rev >= registers[i].rev)) 626 tilcdc_write(ddev, registers[i].reg, 627 priv->saved_register[n++]); 628 } 629 630 drm_kms_helper_poll_enable(ddev); 631 632 return 0; 633 } 634 #endif 635 636 static const struct dev_pm_ops tilcdc_pm_ops = { 637 SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume) 638 }; 639 640 /* 641 * Platform driver: 642 */ 643 644 static int tilcdc_bind(struct device *dev) 645 { 646 return drm_platform_init(&tilcdc_driver, to_platform_device(dev)); 647 } 648 649 static void tilcdc_unbind(struct device *dev) 650 { 651 drm_put_dev(dev_get_drvdata(dev)); 652 } 653 654 static const struct component_master_ops tilcdc_comp_ops = { 655 .bind = tilcdc_bind, 656 .unbind = tilcdc_unbind, 657 }; 658 659 static int tilcdc_pdev_probe(struct platform_device *pdev) 660 { 661 struct component_match *match = NULL; 662 int ret; 663 664 /* bail out early if no DT data: */ 665 if (!pdev->dev.of_node) { 666 dev_err(&pdev->dev, "device-tree data is missing\n"); 667 return -ENXIO; 668 } 669 670 ret = tilcdc_get_external_components(&pdev->dev, &match); 671 if (ret < 0) 672 return ret; 673 else if (ret == 0) 674 return drm_platform_init(&tilcdc_driver, pdev); 675 else 676 return component_master_add_with_match(&pdev->dev, 677 &tilcdc_comp_ops, 678 match); 679 } 680 681 static int tilcdc_pdev_remove(struct platform_device *pdev) 682 { 683 struct drm_device *ddev = dev_get_drvdata(&pdev->dev); 684 struct tilcdc_drm_private *priv = ddev->dev_private; 685 686 /* Check if a subcomponent has already triggered the unloading. */ 687 if (!priv) 688 return 0; 689 690 if (priv->is_componentized) 691 component_master_del(&pdev->dev, &tilcdc_comp_ops); 692 else 693 drm_put_dev(platform_get_drvdata(pdev)); 694 695 return 0; 696 } 697 698 static struct of_device_id tilcdc_of_match[] = { 699 { .compatible = "ti,am33xx-tilcdc", }, 700 { }, 701 }; 702 MODULE_DEVICE_TABLE(of, tilcdc_of_match); 703 704 static struct platform_driver tilcdc_platform_driver = { 705 .probe = tilcdc_pdev_probe, 706 .remove = tilcdc_pdev_remove, 707 .driver = { 708 .name = "tilcdc", 709 .pm = &tilcdc_pm_ops, 710 .of_match_table = tilcdc_of_match, 711 }, 712 }; 713 714 static int __init tilcdc_drm_init(void) 715 { 716 DBG("init"); 717 tilcdc_tfp410_init(); 718 tilcdc_panel_init(); 719 return platform_driver_register(&tilcdc_platform_driver); 720 } 721 722 static void __exit tilcdc_drm_fini(void) 723 { 724 DBG("fini"); 725 platform_driver_unregister(&tilcdc_platform_driver); 726 tilcdc_panel_fini(); 727 tilcdc_tfp410_fini(); 728 } 729 730 module_init(tilcdc_drm_init); 731 module_exit(tilcdc_drm_fini); 732 733 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 734 MODULE_DESCRIPTION("TI LCD Controller DRM Driver"); 735 MODULE_LICENSE("GPL"); 736