1 /* 2 * Copyright (C) 2012 Texas Instruments 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "drm_flip_work.h" 19 #include <drm/drm_plane_helper.h> 20 21 #include "tilcdc_drv.h" 22 #include "tilcdc_regs.h" 23 24 struct tilcdc_crtc { 25 struct drm_crtc base; 26 27 const struct tilcdc_panel_info *info; 28 uint32_t dirty; 29 dma_addr_t start, end; 30 struct drm_pending_vblank_event *event; 31 int dpms; 32 wait_queue_head_t frame_done_wq; 33 bool frame_done; 34 35 /* fb currently set to scanout 0/1: */ 36 struct drm_framebuffer *scanout[2]; 37 38 /* for deferred fb unref's: */ 39 struct drm_flip_work unref_work; 40 }; 41 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base) 42 43 static void unref_worker(struct drm_flip_work *work, void *val) 44 { 45 struct tilcdc_crtc *tilcdc_crtc = 46 container_of(work, struct tilcdc_crtc, unref_work); 47 struct drm_device *dev = tilcdc_crtc->base.dev; 48 49 mutex_lock(&dev->mode_config.mutex); 50 drm_framebuffer_unreference(val); 51 mutex_unlock(&dev->mode_config.mutex); 52 } 53 54 static void set_scanout(struct drm_crtc *crtc, int n) 55 { 56 static const uint32_t base_reg[] = { 57 LCDC_DMA_FB_BASE_ADDR_0_REG, 58 LCDC_DMA_FB_BASE_ADDR_1_REG, 59 }; 60 static const uint32_t ceil_reg[] = { 61 LCDC_DMA_FB_CEILING_ADDR_0_REG, 62 LCDC_DMA_FB_CEILING_ADDR_1_REG, 63 }; 64 static const uint32_t stat[] = { 65 LCDC_END_OF_FRAME0, LCDC_END_OF_FRAME1, 66 }; 67 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 68 struct drm_device *dev = crtc->dev; 69 struct tilcdc_drm_private *priv = dev->dev_private; 70 71 pm_runtime_get_sync(dev->dev); 72 tilcdc_write(dev, base_reg[n], tilcdc_crtc->start); 73 tilcdc_write(dev, ceil_reg[n], tilcdc_crtc->end); 74 if (tilcdc_crtc->scanout[n]) { 75 drm_flip_work_queue(&tilcdc_crtc->unref_work, tilcdc_crtc->scanout[n]); 76 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq); 77 } 78 tilcdc_crtc->scanout[n] = crtc->primary->fb; 79 drm_framebuffer_reference(tilcdc_crtc->scanout[n]); 80 tilcdc_crtc->dirty &= ~stat[n]; 81 pm_runtime_put_sync(dev->dev); 82 } 83 84 static void update_scanout(struct drm_crtc *crtc) 85 { 86 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 87 struct drm_device *dev = crtc->dev; 88 struct drm_framebuffer *fb = crtc->primary->fb; 89 struct drm_gem_cma_object *gem; 90 unsigned int depth, bpp; 91 92 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp); 93 gem = drm_fb_cma_get_gem_obj(fb, 0); 94 95 tilcdc_crtc->start = gem->paddr + fb->offsets[0] + 96 (crtc->y * fb->pitches[0]) + (crtc->x * bpp/8); 97 98 tilcdc_crtc->end = tilcdc_crtc->start + 99 (crtc->mode.vdisplay * fb->pitches[0]); 100 101 if (tilcdc_crtc->dpms == DRM_MODE_DPMS_ON) { 102 /* already enabled, so just mark the frames that need 103 * updating and they will be updated on vblank: 104 */ 105 tilcdc_crtc->dirty |= LCDC_END_OF_FRAME0 | LCDC_END_OF_FRAME1; 106 drm_vblank_get(dev, 0); 107 } else { 108 /* not enabled yet, so update registers immediately: */ 109 set_scanout(crtc, 0); 110 set_scanout(crtc, 1); 111 } 112 } 113 114 static void start(struct drm_crtc *crtc) 115 { 116 struct drm_device *dev = crtc->dev; 117 struct tilcdc_drm_private *priv = dev->dev_private; 118 119 if (priv->rev == 2) { 120 tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); 121 msleep(1); 122 tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET); 123 msleep(1); 124 } 125 126 tilcdc_set(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE); 127 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY)); 128 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 129 } 130 131 static void stop(struct drm_crtc *crtc) 132 { 133 struct drm_device *dev = crtc->dev; 134 135 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE); 136 } 137 138 static void tilcdc_crtc_destroy(struct drm_crtc *crtc) 139 { 140 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 141 142 WARN_ON(tilcdc_crtc->dpms == DRM_MODE_DPMS_ON); 143 144 drm_crtc_cleanup(crtc); 145 drm_flip_work_cleanup(&tilcdc_crtc->unref_work); 146 147 kfree(tilcdc_crtc); 148 } 149 150 static int tilcdc_crtc_page_flip(struct drm_crtc *crtc, 151 struct drm_framebuffer *fb, 152 struct drm_pending_vblank_event *event, 153 uint32_t page_flip_flags) 154 { 155 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 156 struct drm_device *dev = crtc->dev; 157 158 if (tilcdc_crtc->event) { 159 dev_err(dev->dev, "already pending page flip!\n"); 160 return -EBUSY; 161 } 162 163 crtc->primary->fb = fb; 164 tilcdc_crtc->event = event; 165 update_scanout(crtc); 166 167 return 0; 168 } 169 170 static void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode) 171 { 172 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 173 struct drm_device *dev = crtc->dev; 174 struct tilcdc_drm_private *priv = dev->dev_private; 175 176 /* we really only care about on or off: */ 177 if (mode != DRM_MODE_DPMS_ON) 178 mode = DRM_MODE_DPMS_OFF; 179 180 if (tilcdc_crtc->dpms == mode) 181 return; 182 183 tilcdc_crtc->dpms = mode; 184 185 pm_runtime_get_sync(dev->dev); 186 187 if (mode == DRM_MODE_DPMS_ON) { 188 pm_runtime_forbid(dev->dev); 189 start(crtc); 190 } else { 191 tilcdc_crtc->frame_done = false; 192 stop(crtc); 193 194 /* 195 * if necessary wait for framedone irq which will still come 196 * before putting things to sleep.. 197 */ 198 if (priv->rev == 2) { 199 int ret = wait_event_timeout( 200 tilcdc_crtc->frame_done_wq, 201 tilcdc_crtc->frame_done, 202 msecs_to_jiffies(50)); 203 if (ret == 0) 204 dev_err(dev->dev, "timeout waiting for framedone\n"); 205 } 206 pm_runtime_allow(dev->dev); 207 } 208 209 pm_runtime_put_sync(dev->dev); 210 } 211 212 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc, 213 const struct drm_display_mode *mode, 214 struct drm_display_mode *adjusted_mode) 215 { 216 return true; 217 } 218 219 static void tilcdc_crtc_prepare(struct drm_crtc *crtc) 220 { 221 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 222 } 223 224 static void tilcdc_crtc_commit(struct drm_crtc *crtc) 225 { 226 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 227 } 228 229 static int tilcdc_crtc_mode_set(struct drm_crtc *crtc, 230 struct drm_display_mode *mode, 231 struct drm_display_mode *adjusted_mode, 232 int x, int y, 233 struct drm_framebuffer *old_fb) 234 { 235 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 236 struct drm_device *dev = crtc->dev; 237 struct tilcdc_drm_private *priv = dev->dev_private; 238 const struct tilcdc_panel_info *info = tilcdc_crtc->info; 239 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; 240 int ret; 241 242 ret = tilcdc_crtc_mode_valid(crtc, mode); 243 if (WARN_ON(ret)) 244 return ret; 245 246 if (WARN_ON(!info)) 247 return -EINVAL; 248 249 pm_runtime_get_sync(dev->dev); 250 251 /* Configure the Burst Size and fifo threshold of DMA: */ 252 reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770; 253 switch (info->dma_burst_sz) { 254 case 1: 255 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1); 256 break; 257 case 2: 258 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2); 259 break; 260 case 4: 261 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4); 262 break; 263 case 8: 264 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8); 265 break; 266 case 16: 267 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16); 268 break; 269 default: 270 return -EINVAL; 271 } 272 reg |= (info->fifo_th << 8); 273 tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg); 274 275 /* Configure timings: */ 276 hbp = mode->htotal - mode->hsync_end; 277 hfp = mode->hsync_start - mode->hdisplay; 278 hsw = mode->hsync_end - mode->hsync_start; 279 vbp = mode->vtotal - mode->vsync_end; 280 vfp = mode->vsync_start - mode->vdisplay; 281 vsw = mode->vsync_end - mode->vsync_start; 282 283 DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u", 284 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); 285 286 /* Configure the AC Bias Period and Number of Transitions per Interrupt: */ 287 reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00; 288 reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) | 289 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt); 290 291 /* 292 * subtract one from hfp, hbp, hsw because the hardware uses 293 * a value of 0 as 1 294 */ 295 if (priv->rev == 2) { 296 /* clear bits we're going to set */ 297 reg &= ~0x78000033; 298 reg |= ((hfp-1) & 0x300) >> 8; 299 reg |= ((hbp-1) & 0x300) >> 4; 300 reg |= ((hsw-1) & 0x3c0) << 21; 301 } 302 tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg); 303 304 reg = (((mode->hdisplay >> 4) - 1) << 4) | 305 (((hbp-1) & 0xff) << 24) | 306 (((hfp-1) & 0xff) << 16) | 307 (((hsw-1) & 0x3f) << 10); 308 if (priv->rev == 2) 309 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3; 310 tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg); 311 312 reg = ((mode->vdisplay - 1) & 0x3ff) | 313 ((vbp & 0xff) << 24) | 314 ((vfp & 0xff) << 16) | 315 (((vsw-1) & 0x3f) << 10); 316 tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg); 317 318 /* 319 * be sure to set Bit 10 for the V2 LCDC controller, 320 * otherwise limited to 1024 pixels width, stopping 321 * 1920x1080 being suppoted. 322 */ 323 if (priv->rev == 2) { 324 if ((mode->vdisplay - 1) & 0x400) { 325 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, 326 LCDC_LPP_B10); 327 } else { 328 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, 329 LCDC_LPP_B10); 330 } 331 } 332 333 /* Configure display type: */ 334 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & 335 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE | 336 LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 0x000ff000); 337 reg |= LCDC_TFT_MODE; /* no monochrome/passive support */ 338 if (info->tft_alt_mode) 339 reg |= LCDC_TFT_ALT_ENABLE; 340 if (priv->rev == 2) { 341 unsigned int depth, bpp; 342 343 drm_fb_get_bpp_depth(crtc->primary->fb->pixel_format, &depth, &bpp); 344 switch (bpp) { 345 case 16: 346 break; 347 case 32: 348 reg |= LCDC_V2_TFT_24BPP_UNPACK; 349 /* fallthrough */ 350 case 24: 351 reg |= LCDC_V2_TFT_24BPP_MODE; 352 break; 353 default: 354 dev_err(dev->dev, "invalid pixel format\n"); 355 return -EINVAL; 356 } 357 } 358 reg |= info->fdd < 12; 359 tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg); 360 361 if (info->invert_pxl_clk) 362 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); 363 else 364 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK); 365 366 if (info->sync_ctrl) 367 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); 368 else 369 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL); 370 371 if (info->sync_edge) 372 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); 373 else 374 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE); 375 376 /* 377 * use value from adjusted_mode here as this might have been 378 * changed as part of the fixup for slave encoders to solve the 379 * issue where tilcdc timings are not VESA compliant 380 */ 381 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 382 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); 383 else 384 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC); 385 386 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 387 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); 388 else 389 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC); 390 391 if (info->raster_order) 392 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); 393 else 394 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER); 395 396 397 update_scanout(crtc); 398 tilcdc_crtc_update_clk(crtc); 399 400 pm_runtime_put_sync(dev->dev); 401 402 return 0; 403 } 404 405 static int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 406 struct drm_framebuffer *old_fb) 407 { 408 update_scanout(crtc); 409 return 0; 410 } 411 412 static const struct drm_crtc_funcs tilcdc_crtc_funcs = { 413 .destroy = tilcdc_crtc_destroy, 414 .set_config = drm_crtc_helper_set_config, 415 .page_flip = tilcdc_crtc_page_flip, 416 }; 417 418 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = { 419 .dpms = tilcdc_crtc_dpms, 420 .mode_fixup = tilcdc_crtc_mode_fixup, 421 .prepare = tilcdc_crtc_prepare, 422 .commit = tilcdc_crtc_commit, 423 .mode_set = tilcdc_crtc_mode_set, 424 .mode_set_base = tilcdc_crtc_mode_set_base, 425 }; 426 427 int tilcdc_crtc_max_width(struct drm_crtc *crtc) 428 { 429 struct drm_device *dev = crtc->dev; 430 struct tilcdc_drm_private *priv = dev->dev_private; 431 int max_width = 0; 432 433 if (priv->rev == 1) 434 max_width = 1024; 435 else if (priv->rev == 2) 436 max_width = 2048; 437 438 return max_width; 439 } 440 441 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode) 442 { 443 struct tilcdc_drm_private *priv = crtc->dev->dev_private; 444 unsigned int bandwidth; 445 uint32_t hbp, hfp, hsw, vbp, vfp, vsw; 446 447 /* 448 * check to see if the width is within the range that 449 * the LCD Controller physically supports 450 */ 451 if (mode->hdisplay > tilcdc_crtc_max_width(crtc)) 452 return MODE_VIRTUAL_X; 453 454 /* width must be multiple of 16 */ 455 if (mode->hdisplay & 0xf) 456 return MODE_VIRTUAL_X; 457 458 if (mode->vdisplay > 2048) 459 return MODE_VIRTUAL_Y; 460 461 DBG("Processing mode %dx%d@%d with pixel clock %d", 462 mode->hdisplay, mode->vdisplay, 463 drm_mode_vrefresh(mode), mode->clock); 464 465 hbp = mode->htotal - mode->hsync_end; 466 hfp = mode->hsync_start - mode->hdisplay; 467 hsw = mode->hsync_end - mode->hsync_start; 468 vbp = mode->vtotal - mode->vsync_end; 469 vfp = mode->vsync_start - mode->vdisplay; 470 vsw = mode->vsync_end - mode->vsync_start; 471 472 if ((hbp-1) & ~0x3ff) { 473 DBG("Pruning mode: Horizontal Back Porch out of range"); 474 return MODE_HBLANK_WIDE; 475 } 476 477 if ((hfp-1) & ~0x3ff) { 478 DBG("Pruning mode: Horizontal Front Porch out of range"); 479 return MODE_HBLANK_WIDE; 480 } 481 482 if ((hsw-1) & ~0x3ff) { 483 DBG("Pruning mode: Horizontal Sync Width out of range"); 484 return MODE_HSYNC_WIDE; 485 } 486 487 if (vbp & ~0xff) { 488 DBG("Pruning mode: Vertical Back Porch out of range"); 489 return MODE_VBLANK_WIDE; 490 } 491 492 if (vfp & ~0xff) { 493 DBG("Pruning mode: Vertical Front Porch out of range"); 494 return MODE_VBLANK_WIDE; 495 } 496 497 if ((vsw-1) & ~0x3f) { 498 DBG("Pruning mode: Vertical Sync Width out of range"); 499 return MODE_VSYNC_WIDE; 500 } 501 502 /* 503 * some devices have a maximum allowed pixel clock 504 * configured from the DT 505 */ 506 if (mode->clock > priv->max_pixelclock) { 507 DBG("Pruning mode: pixel clock too high"); 508 return MODE_CLOCK_HIGH; 509 } 510 511 /* 512 * some devices further limit the max horizontal resolution 513 * configured from the DT 514 */ 515 if (mode->hdisplay > priv->max_width) 516 return MODE_BAD_WIDTH; 517 518 /* filter out modes that would require too much memory bandwidth: */ 519 bandwidth = mode->hdisplay * mode->vdisplay * 520 drm_mode_vrefresh(mode); 521 if (bandwidth > priv->max_bandwidth) { 522 DBG("Pruning mode: exceeds defined bandwidth limit"); 523 return MODE_BAD; 524 } 525 526 return MODE_OK; 527 } 528 529 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc, 530 const struct tilcdc_panel_info *info) 531 { 532 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 533 tilcdc_crtc->info = info; 534 } 535 536 void tilcdc_crtc_update_clk(struct drm_crtc *crtc) 537 { 538 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 539 struct drm_device *dev = crtc->dev; 540 struct tilcdc_drm_private *priv = dev->dev_private; 541 int dpms = tilcdc_crtc->dpms; 542 unsigned int lcd_clk, div; 543 int ret; 544 545 pm_runtime_get_sync(dev->dev); 546 547 if (dpms == DRM_MODE_DPMS_ON) 548 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 549 550 /* in raster mode, minimum divisor is 2: */ 551 ret = clk_set_rate(priv->disp_clk, crtc->mode.clock * 1000 * 2); 552 if (ret) { 553 dev_err(dev->dev, "failed to set display clock rate to: %d\n", 554 crtc->mode.clock); 555 goto out; 556 } 557 558 lcd_clk = clk_get_rate(priv->clk); 559 div = lcd_clk / (crtc->mode.clock * 1000); 560 561 DBG("lcd_clk=%u, mode clock=%d, div=%u", lcd_clk, crtc->mode.clock, div); 562 DBG("fck=%lu, dpll_disp_ck=%lu", clk_get_rate(priv->clk), clk_get_rate(priv->disp_clk)); 563 564 /* Configure the LCD clock divisor. */ 565 tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(div) | 566 LCDC_RASTER_MODE); 567 568 if (priv->rev == 2) 569 tilcdc_set(dev, LCDC_CLK_ENABLE_REG, 570 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN | 571 LCDC_V2_CORE_CLK_EN); 572 573 if (dpms == DRM_MODE_DPMS_ON) 574 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 575 576 out: 577 pm_runtime_put_sync(dev->dev); 578 } 579 580 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc) 581 { 582 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 583 struct drm_device *dev = crtc->dev; 584 struct tilcdc_drm_private *priv = dev->dev_private; 585 uint32_t stat = tilcdc_read_irqstatus(dev); 586 587 if ((stat & LCDC_SYNC_LOST) && (stat & LCDC_FIFO_UNDERFLOW)) { 588 stop(crtc); 589 dev_err(dev->dev, "error: %08x\n", stat); 590 tilcdc_clear_irqstatus(dev, stat); 591 start(crtc); 592 } else if (stat & LCDC_PL_LOAD_DONE) { 593 tilcdc_clear_irqstatus(dev, stat); 594 } else { 595 struct drm_pending_vblank_event *event; 596 unsigned long flags; 597 uint32_t dirty = tilcdc_crtc->dirty & stat; 598 599 tilcdc_clear_irqstatus(dev, stat); 600 601 if (dirty & LCDC_END_OF_FRAME0) 602 set_scanout(crtc, 0); 603 604 if (dirty & LCDC_END_OF_FRAME1) 605 set_scanout(crtc, 1); 606 607 drm_handle_vblank(dev, 0); 608 609 spin_lock_irqsave(&dev->event_lock, flags); 610 event = tilcdc_crtc->event; 611 tilcdc_crtc->event = NULL; 612 if (event) 613 drm_send_vblank_event(dev, 0, event); 614 spin_unlock_irqrestore(&dev->event_lock, flags); 615 616 if (dirty && !tilcdc_crtc->dirty) 617 drm_vblank_put(dev, 0); 618 } 619 620 if (priv->rev == 2) { 621 if (stat & LCDC_FRAME_DONE) { 622 tilcdc_crtc->frame_done = true; 623 wake_up(&tilcdc_crtc->frame_done_wq); 624 } 625 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0); 626 } 627 628 return IRQ_HANDLED; 629 } 630 631 void tilcdc_crtc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) 632 { 633 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); 634 struct drm_pending_vblank_event *event; 635 struct drm_device *dev = crtc->dev; 636 unsigned long flags; 637 638 /* Destroy the pending vertical blanking event associated with the 639 * pending page flip, if any, and disable vertical blanking interrupts. 640 */ 641 spin_lock_irqsave(&dev->event_lock, flags); 642 event = tilcdc_crtc->event; 643 if (event && event->base.file_priv == file) { 644 tilcdc_crtc->event = NULL; 645 event->base.destroy(&event->base); 646 drm_vblank_put(dev, 0); 647 } 648 spin_unlock_irqrestore(&dev->event_lock, flags); 649 } 650 651 struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev) 652 { 653 struct tilcdc_crtc *tilcdc_crtc; 654 struct drm_crtc *crtc; 655 int ret; 656 657 tilcdc_crtc = kzalloc(sizeof(*tilcdc_crtc), GFP_KERNEL); 658 if (!tilcdc_crtc) { 659 dev_err(dev->dev, "allocation failed\n"); 660 return NULL; 661 } 662 663 crtc = &tilcdc_crtc->base; 664 665 tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF; 666 init_waitqueue_head(&tilcdc_crtc->frame_done_wq); 667 668 drm_flip_work_init(&tilcdc_crtc->unref_work, 669 "unref", unref_worker); 670 671 ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs); 672 if (ret < 0) 673 goto fail; 674 675 drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs); 676 677 return crtc; 678 679 fail: 680 tilcdc_crtc_destroy(crtc); 681 return NULL; 682 } 683