1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
4  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5  */
6 
7 #include <drm/drm_atomic.h>
8 #include <drm/drm_atomic_helper.h>
9 #include <drm/drm_crtc.h>
10 #include <drm/drm_crtc_helper.h>
11 #include <drm/drm_fourcc.h>
12 #include <drm/drm_fb_cma_helper.h>
13 #include <drm/drm_gem_framebuffer_helper.h>
14 
15 #include "tidss_crtc.h"
16 #include "tidss_dispc.h"
17 #include "tidss_drv.h"
18 #include "tidss_plane.h"
19 
20 /* drm_plane_helper_funcs */
21 
22 static int tidss_plane_atomic_check(struct drm_plane *plane,
23 				    struct drm_plane_state *state)
24 {
25 	struct drm_device *ddev = plane->dev;
26 	struct tidss_device *tidss = to_tidss(ddev);
27 	struct tidss_plane *tplane = to_tidss_plane(plane);
28 	const struct drm_format_info *finfo;
29 	struct drm_crtc_state *crtc_state;
30 	u32 hw_plane = tplane->hw_plane_id;
31 	u32 hw_videoport;
32 	int ret;
33 
34 	dev_dbg(ddev->dev, "%s\n", __func__);
35 
36 	if (!state->crtc) {
37 		/*
38 		 * The visible field is not reset by the DRM core but only
39 		 * updated by drm_plane_helper_check_state(), set it manually.
40 		 */
41 		state->visible = false;
42 		return 0;
43 	}
44 
45 	crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
46 	if (IS_ERR(crtc_state))
47 		return PTR_ERR(crtc_state);
48 
49 	ret = drm_atomic_helper_check_plane_state(state, crtc_state, 0,
50 						  INT_MAX, true, true);
51 	if (ret < 0)
52 		return ret;
53 
54 	/*
55 	 * The HW is only able to start drawing at subpixel boundary
56 	 * (the two first checks bellow). At the end of a row the HW
57 	 * can only jump integer number of subpixels forward to the
58 	 * beginning of the next row. So we can only show picture with
59 	 * integer subpixel width (the third check). However, after
60 	 * reaching the end of the drawn picture the drawing starts
61 	 * again at the absolute memory address where top left corner
62 	 * position of the drawn picture is (so there is no need to
63 	 * check for odd height).
64 	 */
65 
66 	finfo = drm_format_info(state->fb->format->format);
67 
68 	if ((state->src_x >> 16) % finfo->hsub != 0) {
69 		dev_dbg(ddev->dev,
70 			"%s: x-position %u not divisible subpixel size %u\n",
71 			__func__, (state->src_x >> 16), finfo->hsub);
72 		return -EINVAL;
73 	}
74 
75 	if ((state->src_y >> 16) % finfo->vsub != 0) {
76 		dev_dbg(ddev->dev,
77 			"%s: y-position %u not divisible subpixel size %u\n",
78 			__func__, (state->src_y >> 16), finfo->vsub);
79 		return -EINVAL;
80 	}
81 
82 	if ((state->src_w >> 16) % finfo->hsub != 0) {
83 		dev_dbg(ddev->dev,
84 			"%s: src width %u not divisible by subpixel size %u\n",
85 			 __func__, (state->src_w >> 16), finfo->hsub);
86 		return -EINVAL;
87 	}
88 
89 	if (!state->visible)
90 		return 0;
91 
92 	hw_videoport = to_tidss_crtc(state->crtc)->hw_videoport;
93 
94 	ret = dispc_plane_check(tidss->dispc, hw_plane, state, hw_videoport);
95 	if (ret)
96 		return ret;
97 
98 	return 0;
99 }
100 
101 static void tidss_plane_atomic_update(struct drm_plane *plane,
102 				      struct drm_plane_state *old_state)
103 {
104 	struct drm_device *ddev = plane->dev;
105 	struct tidss_device *tidss = to_tidss(ddev);
106 	struct tidss_plane *tplane = to_tidss_plane(plane);
107 	struct drm_plane_state *state = plane->state;
108 	u32 hw_videoport;
109 	int ret;
110 
111 	dev_dbg(ddev->dev, "%s\n", __func__);
112 
113 	if (!state->visible) {
114 		dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
115 		return;
116 	}
117 
118 	hw_videoport = to_tidss_crtc(state->crtc)->hw_videoport;
119 
120 	ret = dispc_plane_setup(tidss->dispc, tplane->hw_plane_id,
121 				state, hw_videoport);
122 
123 	if (ret) {
124 		dev_err(plane->dev->dev, "%s: Failed to setup plane %d\n",
125 			__func__, tplane->hw_plane_id);
126 		dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
127 		return;
128 	}
129 
130 	dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, true);
131 }
132 
133 static void tidss_plane_atomic_disable(struct drm_plane *plane,
134 				       struct drm_plane_state *old_state)
135 {
136 	struct drm_device *ddev = plane->dev;
137 	struct tidss_device *tidss = to_tidss(ddev);
138 	struct tidss_plane *tplane = to_tidss_plane(plane);
139 
140 	dev_dbg(ddev->dev, "%s\n", __func__);
141 
142 	dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
143 }
144 
145 static void drm_plane_destroy(struct drm_plane *plane)
146 {
147 	struct tidss_plane *tplane = to_tidss_plane(plane);
148 
149 	drm_plane_cleanup(plane);
150 	kfree(tplane);
151 }
152 
153 static const struct drm_plane_helper_funcs tidss_plane_helper_funcs = {
154 	.prepare_fb = drm_gem_fb_prepare_fb,
155 	.atomic_check = tidss_plane_atomic_check,
156 	.atomic_update = tidss_plane_atomic_update,
157 	.atomic_disable = tidss_plane_atomic_disable,
158 };
159 
160 static const struct drm_plane_funcs tidss_plane_funcs = {
161 	.update_plane = drm_atomic_helper_update_plane,
162 	.disable_plane = drm_atomic_helper_disable_plane,
163 	.reset = drm_atomic_helper_plane_reset,
164 	.destroy = drm_plane_destroy,
165 	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
166 	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
167 };
168 
169 struct tidss_plane *tidss_plane_create(struct tidss_device *tidss,
170 				       u32 hw_plane_id, u32 plane_type,
171 				       u32 crtc_mask, const u32 *formats,
172 				       u32 num_formats)
173 {
174 	struct tidss_plane *tplane;
175 	enum drm_plane_type type;
176 	u32 possible_crtcs;
177 	u32 num_planes = tidss->feat->num_planes;
178 	u32 color_encodings = (BIT(DRM_COLOR_YCBCR_BT601) |
179 			       BIT(DRM_COLOR_YCBCR_BT709));
180 	u32 color_ranges = (BIT(DRM_COLOR_YCBCR_FULL_RANGE) |
181 			    BIT(DRM_COLOR_YCBCR_LIMITED_RANGE));
182 	u32 default_encoding = DRM_COLOR_YCBCR_BT601;
183 	u32 default_range = DRM_COLOR_YCBCR_FULL_RANGE;
184 	u32 blend_modes = (BIT(DRM_MODE_BLEND_PREMULTI) |
185 			   BIT(DRM_MODE_BLEND_COVERAGE));
186 	int ret;
187 
188 	tplane = kzalloc(sizeof(*tplane), GFP_KERNEL);
189 	if (!tplane)
190 		return ERR_PTR(-ENOMEM);
191 
192 	tplane->hw_plane_id = hw_plane_id;
193 
194 	possible_crtcs = crtc_mask;
195 	type = plane_type;
196 
197 	ret = drm_universal_plane_init(&tidss->ddev, &tplane->plane,
198 				       possible_crtcs,
199 				       &tidss_plane_funcs,
200 				       formats, num_formats,
201 				       NULL, type, NULL);
202 	if (ret < 0)
203 		goto err;
204 
205 	drm_plane_helper_add(&tplane->plane, &tidss_plane_helper_funcs);
206 
207 	drm_plane_create_zpos_property(&tplane->plane, hw_plane_id, 0,
208 				       num_planes - 1);
209 
210 	ret = drm_plane_create_color_properties(&tplane->plane,
211 						color_encodings,
212 						color_ranges,
213 						default_encoding,
214 						default_range);
215 	if (ret)
216 		goto err;
217 
218 	ret = drm_plane_create_alpha_property(&tplane->plane);
219 	if (ret)
220 		goto err;
221 
222 	ret = drm_plane_create_blend_mode_property(&tplane->plane, blend_modes);
223 	if (ret)
224 		goto err;
225 
226 	return tplane;
227 
228 err:
229 	kfree(tplane);
230 	return ERR_PTR(ret);
231 }
232