132a1795fSJyri Sarha // SPDX-License-Identifier: GPL-2.0 232a1795fSJyri Sarha /* 39410113fSAlexander A. Klimov * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ 432a1795fSJyri Sarha * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 532a1795fSJyri Sarha */ 632a1795fSJyri Sarha 732a1795fSJyri Sarha #include <drm/drm_atomic.h> 832a1795fSJyri Sarha #include <drm/drm_atomic_helper.h> 932a1795fSJyri Sarha #include <drm/drm_crtc.h> 1032a1795fSJyri Sarha #include <drm/drm_crtc_helper.h> 1132a1795fSJyri Sarha #include <drm/drm_fourcc.h> 1232a1795fSJyri Sarha #include <drm/drm_fb_cma_helper.h> 13820c1707SThomas Zimmermann #include <drm/drm_gem_atomic_helper.h> 1432a1795fSJyri Sarha 1532a1795fSJyri Sarha #include "tidss_crtc.h" 1632a1795fSJyri Sarha #include "tidss_dispc.h" 1732a1795fSJyri Sarha #include "tidss_drv.h" 1832a1795fSJyri Sarha #include "tidss_plane.h" 1932a1795fSJyri Sarha 2032a1795fSJyri Sarha /* drm_plane_helper_funcs */ 2132a1795fSJyri Sarha 2232a1795fSJyri Sarha static int tidss_plane_atomic_check(struct drm_plane *plane, 237c11b99aSMaxime Ripard struct drm_atomic_state *state) 2432a1795fSJyri Sarha { 257c11b99aSMaxime Ripard struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 267c11b99aSMaxime Ripard plane); 2732a1795fSJyri Sarha struct drm_device *ddev = plane->dev; 2802bb1317SDaniel Vetter struct tidss_device *tidss = to_tidss(ddev); 2932a1795fSJyri Sarha struct tidss_plane *tplane = to_tidss_plane(plane); 3032a1795fSJyri Sarha const struct drm_format_info *finfo; 3132a1795fSJyri Sarha struct drm_crtc_state *crtc_state; 3232a1795fSJyri Sarha u32 hw_plane = tplane->hw_plane_id; 3332a1795fSJyri Sarha u32 hw_videoport; 3432a1795fSJyri Sarha int ret; 3532a1795fSJyri Sarha 3632a1795fSJyri Sarha dev_dbg(ddev->dev, "%s\n", __func__); 3732a1795fSJyri Sarha 38ba5c1649SMaxime Ripard if (!new_plane_state->crtc) { 3932a1795fSJyri Sarha /* 4032a1795fSJyri Sarha * The visible field is not reset by the DRM core but only 4132a1795fSJyri Sarha * updated by drm_plane_helper_check_state(), set it manually. 4232a1795fSJyri Sarha */ 43ba5c1649SMaxime Ripard new_plane_state->visible = false; 4432a1795fSJyri Sarha return 0; 4532a1795fSJyri Sarha } 4632a1795fSJyri Sarha 47*dec92020SMaxime Ripard crtc_state = drm_atomic_get_crtc_state(state, 48ba5c1649SMaxime Ripard new_plane_state->crtc); 4932a1795fSJyri Sarha if (IS_ERR(crtc_state)) 5032a1795fSJyri Sarha return PTR_ERR(crtc_state); 5132a1795fSJyri Sarha 52ba5c1649SMaxime Ripard ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, 53ba5c1649SMaxime Ripard 0, 5432a1795fSJyri Sarha INT_MAX, true, true); 5532a1795fSJyri Sarha if (ret < 0) 5632a1795fSJyri Sarha return ret; 5732a1795fSJyri Sarha 5832a1795fSJyri Sarha /* 5932a1795fSJyri Sarha * The HW is only able to start drawing at subpixel boundary 6032a1795fSJyri Sarha * (the two first checks bellow). At the end of a row the HW 6132a1795fSJyri Sarha * can only jump integer number of subpixels forward to the 6232a1795fSJyri Sarha * beginning of the next row. So we can only show picture with 6332a1795fSJyri Sarha * integer subpixel width (the third check). However, after 6432a1795fSJyri Sarha * reaching the end of the drawn picture the drawing starts 6532a1795fSJyri Sarha * again at the absolute memory address where top left corner 6632a1795fSJyri Sarha * position of the drawn picture is (so there is no need to 6732a1795fSJyri Sarha * check for odd height). 6832a1795fSJyri Sarha */ 6932a1795fSJyri Sarha 70ba5c1649SMaxime Ripard finfo = drm_format_info(new_plane_state->fb->format->format); 7132a1795fSJyri Sarha 72ba5c1649SMaxime Ripard if ((new_plane_state->src_x >> 16) % finfo->hsub != 0) { 7332a1795fSJyri Sarha dev_dbg(ddev->dev, 7432a1795fSJyri Sarha "%s: x-position %u not divisible subpixel size %u\n", 75ba5c1649SMaxime Ripard __func__, (new_plane_state->src_x >> 16), finfo->hsub); 7632a1795fSJyri Sarha return -EINVAL; 7732a1795fSJyri Sarha } 7832a1795fSJyri Sarha 79ba5c1649SMaxime Ripard if ((new_plane_state->src_y >> 16) % finfo->vsub != 0) { 8032a1795fSJyri Sarha dev_dbg(ddev->dev, 8132a1795fSJyri Sarha "%s: y-position %u not divisible subpixel size %u\n", 82ba5c1649SMaxime Ripard __func__, (new_plane_state->src_y >> 16), finfo->vsub); 8332a1795fSJyri Sarha return -EINVAL; 8432a1795fSJyri Sarha } 8532a1795fSJyri Sarha 86ba5c1649SMaxime Ripard if ((new_plane_state->src_w >> 16) % finfo->hsub != 0) { 8732a1795fSJyri Sarha dev_dbg(ddev->dev, 8832a1795fSJyri Sarha "%s: src width %u not divisible by subpixel size %u\n", 89ba5c1649SMaxime Ripard __func__, (new_plane_state->src_w >> 16), 90ba5c1649SMaxime Ripard finfo->hsub); 9132a1795fSJyri Sarha return -EINVAL; 9232a1795fSJyri Sarha } 9332a1795fSJyri Sarha 94ba5c1649SMaxime Ripard if (!new_plane_state->visible) 9532a1795fSJyri Sarha return 0; 9632a1795fSJyri Sarha 97ba5c1649SMaxime Ripard hw_videoport = to_tidss_crtc(new_plane_state->crtc)->hw_videoport; 9832a1795fSJyri Sarha 99ba5c1649SMaxime Ripard ret = dispc_plane_check(tidss->dispc, hw_plane, new_plane_state, 100ba5c1649SMaxime Ripard hw_videoport); 10132a1795fSJyri Sarha if (ret) 10232a1795fSJyri Sarha return ret; 10332a1795fSJyri Sarha 10432a1795fSJyri Sarha return 0; 10532a1795fSJyri Sarha } 10632a1795fSJyri Sarha 10732a1795fSJyri Sarha static void tidss_plane_atomic_update(struct drm_plane *plane, 10832a1795fSJyri Sarha struct drm_plane_state *old_state) 10932a1795fSJyri Sarha { 11032a1795fSJyri Sarha struct drm_device *ddev = plane->dev; 11102bb1317SDaniel Vetter struct tidss_device *tidss = to_tidss(ddev); 11232a1795fSJyri Sarha struct tidss_plane *tplane = to_tidss_plane(plane); 11332a1795fSJyri Sarha struct drm_plane_state *state = plane->state; 11432a1795fSJyri Sarha u32 hw_videoport; 11532a1795fSJyri Sarha int ret; 11632a1795fSJyri Sarha 11732a1795fSJyri Sarha dev_dbg(ddev->dev, "%s\n", __func__); 11832a1795fSJyri Sarha 11932a1795fSJyri Sarha if (!state->visible) { 12032a1795fSJyri Sarha dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); 12132a1795fSJyri Sarha return; 12232a1795fSJyri Sarha } 12332a1795fSJyri Sarha 12432a1795fSJyri Sarha hw_videoport = to_tidss_crtc(state->crtc)->hw_videoport; 12532a1795fSJyri Sarha 12632a1795fSJyri Sarha ret = dispc_plane_setup(tidss->dispc, tplane->hw_plane_id, 12732a1795fSJyri Sarha state, hw_videoport); 12832a1795fSJyri Sarha 12932a1795fSJyri Sarha if (ret) { 13032a1795fSJyri Sarha dev_err(plane->dev->dev, "%s: Failed to setup plane %d\n", 13132a1795fSJyri Sarha __func__, tplane->hw_plane_id); 13232a1795fSJyri Sarha dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); 13332a1795fSJyri Sarha return; 13432a1795fSJyri Sarha } 13532a1795fSJyri Sarha 13632a1795fSJyri Sarha dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, true); 13732a1795fSJyri Sarha } 13832a1795fSJyri Sarha 13932a1795fSJyri Sarha static void tidss_plane_atomic_disable(struct drm_plane *plane, 14032a1795fSJyri Sarha struct drm_plane_state *old_state) 14132a1795fSJyri Sarha { 14232a1795fSJyri Sarha struct drm_device *ddev = plane->dev; 14302bb1317SDaniel Vetter struct tidss_device *tidss = to_tidss(ddev); 14432a1795fSJyri Sarha struct tidss_plane *tplane = to_tidss_plane(plane); 14532a1795fSJyri Sarha 14632a1795fSJyri Sarha dev_dbg(ddev->dev, "%s\n", __func__); 14732a1795fSJyri Sarha 14832a1795fSJyri Sarha dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); 14932a1795fSJyri Sarha } 15032a1795fSJyri Sarha 1519da67433STomi Valkeinen static void drm_plane_destroy(struct drm_plane *plane) 1529da67433STomi Valkeinen { 1539da67433STomi Valkeinen struct tidss_plane *tplane = to_tidss_plane(plane); 1549da67433STomi Valkeinen 1559da67433STomi Valkeinen drm_plane_cleanup(plane); 1569da67433STomi Valkeinen kfree(tplane); 1579da67433STomi Valkeinen } 1589da67433STomi Valkeinen 15932a1795fSJyri Sarha static const struct drm_plane_helper_funcs tidss_plane_helper_funcs = { 160820c1707SThomas Zimmermann .prepare_fb = drm_gem_plane_helper_prepare_fb, 16132a1795fSJyri Sarha .atomic_check = tidss_plane_atomic_check, 16232a1795fSJyri Sarha .atomic_update = tidss_plane_atomic_update, 16332a1795fSJyri Sarha .atomic_disable = tidss_plane_atomic_disable, 16432a1795fSJyri Sarha }; 16532a1795fSJyri Sarha 16632a1795fSJyri Sarha static const struct drm_plane_funcs tidss_plane_funcs = { 16732a1795fSJyri Sarha .update_plane = drm_atomic_helper_update_plane, 16832a1795fSJyri Sarha .disable_plane = drm_atomic_helper_disable_plane, 16932a1795fSJyri Sarha .reset = drm_atomic_helper_plane_reset, 1709da67433STomi Valkeinen .destroy = drm_plane_destroy, 17132a1795fSJyri Sarha .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 17232a1795fSJyri Sarha .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 17332a1795fSJyri Sarha }; 17432a1795fSJyri Sarha 17532a1795fSJyri Sarha struct tidss_plane *tidss_plane_create(struct tidss_device *tidss, 17632a1795fSJyri Sarha u32 hw_plane_id, u32 plane_type, 17732a1795fSJyri Sarha u32 crtc_mask, const u32 *formats, 17832a1795fSJyri Sarha u32 num_formats) 17932a1795fSJyri Sarha { 18032a1795fSJyri Sarha struct tidss_plane *tplane; 18132a1795fSJyri Sarha enum drm_plane_type type; 18232a1795fSJyri Sarha u32 possible_crtcs; 18332a1795fSJyri Sarha u32 num_planes = tidss->feat->num_planes; 18432a1795fSJyri Sarha u32 color_encodings = (BIT(DRM_COLOR_YCBCR_BT601) | 18532a1795fSJyri Sarha BIT(DRM_COLOR_YCBCR_BT709)); 18632a1795fSJyri Sarha u32 color_ranges = (BIT(DRM_COLOR_YCBCR_FULL_RANGE) | 18732a1795fSJyri Sarha BIT(DRM_COLOR_YCBCR_LIMITED_RANGE)); 18832a1795fSJyri Sarha u32 default_encoding = DRM_COLOR_YCBCR_BT601; 18932a1795fSJyri Sarha u32 default_range = DRM_COLOR_YCBCR_FULL_RANGE; 19032a1795fSJyri Sarha u32 blend_modes = (BIT(DRM_MODE_BLEND_PREMULTI) | 19132a1795fSJyri Sarha BIT(DRM_MODE_BLEND_COVERAGE)); 19232a1795fSJyri Sarha int ret; 19332a1795fSJyri Sarha 1949da67433STomi Valkeinen tplane = kzalloc(sizeof(*tplane), GFP_KERNEL); 19532a1795fSJyri Sarha if (!tplane) 19632a1795fSJyri Sarha return ERR_PTR(-ENOMEM); 19732a1795fSJyri Sarha 19832a1795fSJyri Sarha tplane->hw_plane_id = hw_plane_id; 19932a1795fSJyri Sarha 20032a1795fSJyri Sarha possible_crtcs = crtc_mask; 20132a1795fSJyri Sarha type = plane_type; 20232a1795fSJyri Sarha 20332a1795fSJyri Sarha ret = drm_universal_plane_init(&tidss->ddev, &tplane->plane, 20432a1795fSJyri Sarha possible_crtcs, 20532a1795fSJyri Sarha &tidss_plane_funcs, 20632a1795fSJyri Sarha formats, num_formats, 20732a1795fSJyri Sarha NULL, type, NULL); 20832a1795fSJyri Sarha if (ret < 0) 2099da67433STomi Valkeinen goto err; 21032a1795fSJyri Sarha 21132a1795fSJyri Sarha drm_plane_helper_add(&tplane->plane, &tidss_plane_helper_funcs); 21232a1795fSJyri Sarha 21332a1795fSJyri Sarha drm_plane_create_zpos_property(&tplane->plane, hw_plane_id, 0, 21432a1795fSJyri Sarha num_planes - 1); 21532a1795fSJyri Sarha 21632a1795fSJyri Sarha ret = drm_plane_create_color_properties(&tplane->plane, 21732a1795fSJyri Sarha color_encodings, 21832a1795fSJyri Sarha color_ranges, 21932a1795fSJyri Sarha default_encoding, 22032a1795fSJyri Sarha default_range); 22132a1795fSJyri Sarha if (ret) 2229da67433STomi Valkeinen goto err; 22332a1795fSJyri Sarha 22432a1795fSJyri Sarha ret = drm_plane_create_alpha_property(&tplane->plane); 22532a1795fSJyri Sarha if (ret) 2269da67433STomi Valkeinen goto err; 22732a1795fSJyri Sarha 22832a1795fSJyri Sarha ret = drm_plane_create_blend_mode_property(&tplane->plane, blend_modes); 22932a1795fSJyri Sarha if (ret) 2309da67433STomi Valkeinen goto err; 23132a1795fSJyri Sarha 23232a1795fSJyri Sarha return tplane; 2339da67433STomi Valkeinen 2349da67433STomi Valkeinen err: 2359da67433STomi Valkeinen kfree(tplane); 2369da67433STomi Valkeinen return ERR_PTR(ret); 23732a1795fSJyri Sarha } 238