132a1795fSJyri Sarha // SPDX-License-Identifier: GPL-2.0
232a1795fSJyri Sarha /*
332a1795fSJyri Sarha  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
432a1795fSJyri Sarha  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
532a1795fSJyri Sarha  */
632a1795fSJyri Sarha 
732a1795fSJyri Sarha #include <drm/drm_atomic.h>
832a1795fSJyri Sarha #include <drm/drm_atomic_helper.h>
932a1795fSJyri Sarha #include <drm/drm_crtc.h>
1032a1795fSJyri Sarha #include <drm/drm_crtc_helper.h>
1132a1795fSJyri Sarha #include <drm/drm_fourcc.h>
1232a1795fSJyri Sarha #include <drm/drm_fb_cma_helper.h>
1332a1795fSJyri Sarha 
1432a1795fSJyri Sarha #include "tidss_crtc.h"
1532a1795fSJyri Sarha #include "tidss_dispc.h"
1632a1795fSJyri Sarha #include "tidss_drv.h"
1732a1795fSJyri Sarha #include "tidss_plane.h"
1832a1795fSJyri Sarha 
1932a1795fSJyri Sarha /* drm_plane_helper_funcs */
2032a1795fSJyri Sarha 
2132a1795fSJyri Sarha static int tidss_plane_atomic_check(struct drm_plane *plane,
2232a1795fSJyri Sarha 				    struct drm_plane_state *state)
2332a1795fSJyri Sarha {
2432a1795fSJyri Sarha 	struct drm_device *ddev = plane->dev;
2532a1795fSJyri Sarha 	struct tidss_device *tidss = ddev->dev_private;
2632a1795fSJyri Sarha 	struct tidss_plane *tplane = to_tidss_plane(plane);
2732a1795fSJyri Sarha 	const struct drm_format_info *finfo;
2832a1795fSJyri Sarha 	struct drm_crtc_state *crtc_state;
2932a1795fSJyri Sarha 	u32 hw_plane = tplane->hw_plane_id;
3032a1795fSJyri Sarha 	u32 hw_videoport;
3132a1795fSJyri Sarha 	int ret;
3232a1795fSJyri Sarha 
3332a1795fSJyri Sarha 	dev_dbg(ddev->dev, "%s\n", __func__);
3432a1795fSJyri Sarha 
3532a1795fSJyri Sarha 	if (!state->crtc) {
3632a1795fSJyri Sarha 		/*
3732a1795fSJyri Sarha 		 * The visible field is not reset by the DRM core but only
3832a1795fSJyri Sarha 		 * updated by drm_plane_helper_check_state(), set it manually.
3932a1795fSJyri Sarha 		 */
4032a1795fSJyri Sarha 		state->visible = false;
4132a1795fSJyri Sarha 		return 0;
4232a1795fSJyri Sarha 	}
4332a1795fSJyri Sarha 
4432a1795fSJyri Sarha 	crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
4532a1795fSJyri Sarha 	if (IS_ERR(crtc_state))
4632a1795fSJyri Sarha 		return PTR_ERR(crtc_state);
4732a1795fSJyri Sarha 
4832a1795fSJyri Sarha 	ret = drm_atomic_helper_check_plane_state(state, crtc_state, 0,
4932a1795fSJyri Sarha 						  INT_MAX, true, true);
5032a1795fSJyri Sarha 	if (ret < 0)
5132a1795fSJyri Sarha 		return ret;
5232a1795fSJyri Sarha 
5332a1795fSJyri Sarha 	/*
5432a1795fSJyri Sarha 	 * The HW is only able to start drawing at subpixel boundary
5532a1795fSJyri Sarha 	 * (the two first checks bellow). At the end of a row the HW
5632a1795fSJyri Sarha 	 * can only jump integer number of subpixels forward to the
5732a1795fSJyri Sarha 	 * beginning of the next row. So we can only show picture with
5832a1795fSJyri Sarha 	 * integer subpixel width (the third check). However, after
5932a1795fSJyri Sarha 	 * reaching the end of the drawn picture the drawing starts
6032a1795fSJyri Sarha 	 * again at the absolute memory address where top left corner
6132a1795fSJyri Sarha 	 * position of the drawn picture is (so there is no need to
6232a1795fSJyri Sarha 	 * check for odd height).
6332a1795fSJyri Sarha 	 */
6432a1795fSJyri Sarha 
6532a1795fSJyri Sarha 	finfo = drm_format_info(state->fb->format->format);
6632a1795fSJyri Sarha 
6732a1795fSJyri Sarha 	if ((state->src_x >> 16) % finfo->hsub != 0) {
6832a1795fSJyri Sarha 		dev_dbg(ddev->dev,
6932a1795fSJyri Sarha 			"%s: x-position %u not divisible subpixel size %u\n",
7032a1795fSJyri Sarha 			__func__, (state->src_x >> 16), finfo->hsub);
7132a1795fSJyri Sarha 		return -EINVAL;
7232a1795fSJyri Sarha 	}
7332a1795fSJyri Sarha 
7432a1795fSJyri Sarha 	if ((state->src_y >> 16) % finfo->vsub != 0) {
7532a1795fSJyri Sarha 		dev_dbg(ddev->dev,
7632a1795fSJyri Sarha 			"%s: y-position %u not divisible subpixel size %u\n",
7732a1795fSJyri Sarha 			__func__, (state->src_y >> 16), finfo->vsub);
7832a1795fSJyri Sarha 		return -EINVAL;
7932a1795fSJyri Sarha 	}
8032a1795fSJyri Sarha 
8132a1795fSJyri Sarha 	if ((state->src_w >> 16) % finfo->hsub != 0) {
8232a1795fSJyri Sarha 		dev_dbg(ddev->dev,
8332a1795fSJyri Sarha 			"%s: src width %u not divisible by subpixel size %u\n",
8432a1795fSJyri Sarha 			 __func__, (state->src_w >> 16), finfo->hsub);
8532a1795fSJyri Sarha 		return -EINVAL;
8632a1795fSJyri Sarha 	}
8732a1795fSJyri Sarha 
8832a1795fSJyri Sarha 	if (!state->visible)
8932a1795fSJyri Sarha 		return 0;
9032a1795fSJyri Sarha 
9132a1795fSJyri Sarha 	hw_videoport = to_tidss_crtc(state->crtc)->hw_videoport;
9232a1795fSJyri Sarha 
9332a1795fSJyri Sarha 	ret = dispc_plane_check(tidss->dispc, hw_plane, state, hw_videoport);
9432a1795fSJyri Sarha 	if (ret)
9532a1795fSJyri Sarha 		return ret;
9632a1795fSJyri Sarha 
9732a1795fSJyri Sarha 	return 0;
9832a1795fSJyri Sarha }
9932a1795fSJyri Sarha 
10032a1795fSJyri Sarha static void tidss_plane_atomic_update(struct drm_plane *plane,
10132a1795fSJyri Sarha 				      struct drm_plane_state *old_state)
10232a1795fSJyri Sarha {
10332a1795fSJyri Sarha 	struct drm_device *ddev = plane->dev;
10432a1795fSJyri Sarha 	struct tidss_device *tidss = ddev->dev_private;
10532a1795fSJyri Sarha 	struct tidss_plane *tplane = to_tidss_plane(plane);
10632a1795fSJyri Sarha 	struct drm_plane_state *state = plane->state;
10732a1795fSJyri Sarha 	u32 hw_videoport;
10832a1795fSJyri Sarha 	int ret;
10932a1795fSJyri Sarha 
11032a1795fSJyri Sarha 	dev_dbg(ddev->dev, "%s\n", __func__);
11132a1795fSJyri Sarha 
11232a1795fSJyri Sarha 	if (!state->visible) {
11332a1795fSJyri Sarha 		dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
11432a1795fSJyri Sarha 		return;
11532a1795fSJyri Sarha 	}
11632a1795fSJyri Sarha 
11732a1795fSJyri Sarha 	hw_videoport = to_tidss_crtc(state->crtc)->hw_videoport;
11832a1795fSJyri Sarha 
11932a1795fSJyri Sarha 	ret = dispc_plane_setup(tidss->dispc, tplane->hw_plane_id,
12032a1795fSJyri Sarha 				state, hw_videoport);
12132a1795fSJyri Sarha 
12232a1795fSJyri Sarha 	if (ret) {
12332a1795fSJyri Sarha 		dev_err(plane->dev->dev, "%s: Failed to setup plane %d\n",
12432a1795fSJyri Sarha 			__func__, tplane->hw_plane_id);
12532a1795fSJyri Sarha 		dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
12632a1795fSJyri Sarha 		return;
12732a1795fSJyri Sarha 	}
12832a1795fSJyri Sarha 
12932a1795fSJyri Sarha 	dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, true);
13032a1795fSJyri Sarha }
13132a1795fSJyri Sarha 
13232a1795fSJyri Sarha static void tidss_plane_atomic_disable(struct drm_plane *plane,
13332a1795fSJyri Sarha 				       struct drm_plane_state *old_state)
13432a1795fSJyri Sarha {
13532a1795fSJyri Sarha 	struct drm_device *ddev = plane->dev;
13632a1795fSJyri Sarha 	struct tidss_device *tidss = ddev->dev_private;
13732a1795fSJyri Sarha 	struct tidss_plane *tplane = to_tidss_plane(plane);
13832a1795fSJyri Sarha 
13932a1795fSJyri Sarha 	dev_dbg(ddev->dev, "%s\n", __func__);
14032a1795fSJyri Sarha 
14132a1795fSJyri Sarha 	dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
14232a1795fSJyri Sarha }
14332a1795fSJyri Sarha 
1449da67433STomi Valkeinen static void drm_plane_destroy(struct drm_plane *plane)
1459da67433STomi Valkeinen {
1469da67433STomi Valkeinen 	struct tidss_plane *tplane = to_tidss_plane(plane);
1479da67433STomi Valkeinen 
1489da67433STomi Valkeinen 	drm_plane_cleanup(plane);
1499da67433STomi Valkeinen 	kfree(tplane);
1509da67433STomi Valkeinen }
1519da67433STomi Valkeinen 
15232a1795fSJyri Sarha static const struct drm_plane_helper_funcs tidss_plane_helper_funcs = {
15332a1795fSJyri Sarha 	.atomic_check = tidss_plane_atomic_check,
15432a1795fSJyri Sarha 	.atomic_update = tidss_plane_atomic_update,
15532a1795fSJyri Sarha 	.atomic_disable = tidss_plane_atomic_disable,
15632a1795fSJyri Sarha };
15732a1795fSJyri Sarha 
15832a1795fSJyri Sarha static const struct drm_plane_funcs tidss_plane_funcs = {
15932a1795fSJyri Sarha 	.update_plane = drm_atomic_helper_update_plane,
16032a1795fSJyri Sarha 	.disable_plane = drm_atomic_helper_disable_plane,
16132a1795fSJyri Sarha 	.reset = drm_atomic_helper_plane_reset,
1629da67433STomi Valkeinen 	.destroy = drm_plane_destroy,
16332a1795fSJyri Sarha 	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
16432a1795fSJyri Sarha 	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
16532a1795fSJyri Sarha };
16632a1795fSJyri Sarha 
16732a1795fSJyri Sarha struct tidss_plane *tidss_plane_create(struct tidss_device *tidss,
16832a1795fSJyri Sarha 				       u32 hw_plane_id, u32 plane_type,
16932a1795fSJyri Sarha 				       u32 crtc_mask, const u32 *formats,
17032a1795fSJyri Sarha 				       u32 num_formats)
17132a1795fSJyri Sarha {
17232a1795fSJyri Sarha 	struct tidss_plane *tplane;
17332a1795fSJyri Sarha 	enum drm_plane_type type;
17432a1795fSJyri Sarha 	u32 possible_crtcs;
17532a1795fSJyri Sarha 	u32 num_planes = tidss->feat->num_planes;
17632a1795fSJyri Sarha 	u32 color_encodings = (BIT(DRM_COLOR_YCBCR_BT601) |
17732a1795fSJyri Sarha 			       BIT(DRM_COLOR_YCBCR_BT709));
17832a1795fSJyri Sarha 	u32 color_ranges = (BIT(DRM_COLOR_YCBCR_FULL_RANGE) |
17932a1795fSJyri Sarha 			    BIT(DRM_COLOR_YCBCR_LIMITED_RANGE));
18032a1795fSJyri Sarha 	u32 default_encoding = DRM_COLOR_YCBCR_BT601;
18132a1795fSJyri Sarha 	u32 default_range = DRM_COLOR_YCBCR_FULL_RANGE;
18232a1795fSJyri Sarha 	u32 blend_modes = (BIT(DRM_MODE_BLEND_PREMULTI) |
18332a1795fSJyri Sarha 			   BIT(DRM_MODE_BLEND_COVERAGE));
18432a1795fSJyri Sarha 	int ret;
18532a1795fSJyri Sarha 
1869da67433STomi Valkeinen 	tplane = kzalloc(sizeof(*tplane), GFP_KERNEL);
18732a1795fSJyri Sarha 	if (!tplane)
18832a1795fSJyri Sarha 		return ERR_PTR(-ENOMEM);
18932a1795fSJyri Sarha 
19032a1795fSJyri Sarha 	tplane->hw_plane_id = hw_plane_id;
19132a1795fSJyri Sarha 
19232a1795fSJyri Sarha 	possible_crtcs = crtc_mask;
19332a1795fSJyri Sarha 	type = plane_type;
19432a1795fSJyri Sarha 
19532a1795fSJyri Sarha 	ret = drm_universal_plane_init(&tidss->ddev, &tplane->plane,
19632a1795fSJyri Sarha 				       possible_crtcs,
19732a1795fSJyri Sarha 				       &tidss_plane_funcs,
19832a1795fSJyri Sarha 				       formats, num_formats,
19932a1795fSJyri Sarha 				       NULL, type, NULL);
20032a1795fSJyri Sarha 	if (ret < 0)
2019da67433STomi Valkeinen 		goto err;
20232a1795fSJyri Sarha 
20332a1795fSJyri Sarha 	drm_plane_helper_add(&tplane->plane, &tidss_plane_helper_funcs);
20432a1795fSJyri Sarha 
20532a1795fSJyri Sarha 	drm_plane_create_zpos_property(&tplane->plane, hw_plane_id, 0,
20632a1795fSJyri Sarha 				       num_planes - 1);
20732a1795fSJyri Sarha 
20832a1795fSJyri Sarha 	ret = drm_plane_create_color_properties(&tplane->plane,
20932a1795fSJyri Sarha 						color_encodings,
21032a1795fSJyri Sarha 						color_ranges,
21132a1795fSJyri Sarha 						default_encoding,
21232a1795fSJyri Sarha 						default_range);
21332a1795fSJyri Sarha 	if (ret)
2149da67433STomi Valkeinen 		goto err;
21532a1795fSJyri Sarha 
21632a1795fSJyri Sarha 	ret = drm_plane_create_alpha_property(&tplane->plane);
21732a1795fSJyri Sarha 	if (ret)
2189da67433STomi Valkeinen 		goto err;
21932a1795fSJyri Sarha 
22032a1795fSJyri Sarha 	ret = drm_plane_create_blend_mode_property(&tplane->plane, blend_modes);
22132a1795fSJyri Sarha 	if (ret)
2229da67433STomi Valkeinen 		goto err;
22332a1795fSJyri Sarha 
22432a1795fSJyri Sarha 	return tplane;
2259da67433STomi Valkeinen 
2269da67433STomi Valkeinen err:
2279da67433STomi Valkeinen 	kfree(tplane);
2289da67433STomi Valkeinen 	return ERR_PTR(ret);
22932a1795fSJyri Sarha }
230