132a1795fSJyri Sarha // SPDX-License-Identifier: GPL-2.0
232a1795fSJyri Sarha /*
39410113fSAlexander A. Klimov  * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
432a1795fSJyri Sarha  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
532a1795fSJyri Sarha  */
632a1795fSJyri Sarha 
732a1795fSJyri Sarha #include <drm/drm_atomic.h>
832a1795fSJyri Sarha #include <drm/drm_atomic_helper.h>
932a1795fSJyri Sarha #include <drm/drm_crtc.h>
1032a1795fSJyri Sarha #include <drm/drm_crtc_helper.h>
1132a1795fSJyri Sarha #include <drm/drm_fourcc.h>
12*720cf96dSVille Syrjälä #include <drm/drm_framebuffer.h>
1332a1795fSJyri Sarha #include <drm/drm_fb_cma_helper.h>
14820c1707SThomas Zimmermann #include <drm/drm_gem_atomic_helper.h>
1532a1795fSJyri Sarha 
1632a1795fSJyri Sarha #include "tidss_crtc.h"
1732a1795fSJyri Sarha #include "tidss_dispc.h"
1832a1795fSJyri Sarha #include "tidss_drv.h"
1932a1795fSJyri Sarha #include "tidss_plane.h"
2032a1795fSJyri Sarha 
2132a1795fSJyri Sarha /* drm_plane_helper_funcs */
2232a1795fSJyri Sarha 
2332a1795fSJyri Sarha static int tidss_plane_atomic_check(struct drm_plane *plane,
247c11b99aSMaxime Ripard 				    struct drm_atomic_state *state)
2532a1795fSJyri Sarha {
267c11b99aSMaxime Ripard 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
277c11b99aSMaxime Ripard 										 plane);
2832a1795fSJyri Sarha 	struct drm_device *ddev = plane->dev;
2902bb1317SDaniel Vetter 	struct tidss_device *tidss = to_tidss(ddev);
3032a1795fSJyri Sarha 	struct tidss_plane *tplane = to_tidss_plane(plane);
3132a1795fSJyri Sarha 	const struct drm_format_info *finfo;
3232a1795fSJyri Sarha 	struct drm_crtc_state *crtc_state;
3332a1795fSJyri Sarha 	u32 hw_plane = tplane->hw_plane_id;
3432a1795fSJyri Sarha 	u32 hw_videoport;
3532a1795fSJyri Sarha 	int ret;
3632a1795fSJyri Sarha 
3732a1795fSJyri Sarha 	dev_dbg(ddev->dev, "%s\n", __func__);
3832a1795fSJyri Sarha 
39ba5c1649SMaxime Ripard 	if (!new_plane_state->crtc) {
4032a1795fSJyri Sarha 		/*
4132a1795fSJyri Sarha 		 * The visible field is not reset by the DRM core but only
4232a1795fSJyri Sarha 		 * updated by drm_plane_helper_check_state(), set it manually.
4332a1795fSJyri Sarha 		 */
44ba5c1649SMaxime Ripard 		new_plane_state->visible = false;
4532a1795fSJyri Sarha 		return 0;
4632a1795fSJyri Sarha 	}
4732a1795fSJyri Sarha 
48dec92020SMaxime Ripard 	crtc_state = drm_atomic_get_crtc_state(state,
49ba5c1649SMaxime Ripard 					       new_plane_state->crtc);
5032a1795fSJyri Sarha 	if (IS_ERR(crtc_state))
5132a1795fSJyri Sarha 		return PTR_ERR(crtc_state);
5232a1795fSJyri Sarha 
53ba5c1649SMaxime Ripard 	ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
54ba5c1649SMaxime Ripard 						  0,
5532a1795fSJyri Sarha 						  INT_MAX, true, true);
5632a1795fSJyri Sarha 	if (ret < 0)
5732a1795fSJyri Sarha 		return ret;
5832a1795fSJyri Sarha 
5932a1795fSJyri Sarha 	/*
6032a1795fSJyri Sarha 	 * The HW is only able to start drawing at subpixel boundary
6132a1795fSJyri Sarha 	 * (the two first checks bellow). At the end of a row the HW
6232a1795fSJyri Sarha 	 * can only jump integer number of subpixels forward to the
6332a1795fSJyri Sarha 	 * beginning of the next row. So we can only show picture with
6432a1795fSJyri Sarha 	 * integer subpixel width (the third check). However, after
6532a1795fSJyri Sarha 	 * reaching the end of the drawn picture the drawing starts
6632a1795fSJyri Sarha 	 * again at the absolute memory address where top left corner
6732a1795fSJyri Sarha 	 * position of the drawn picture is (so there is no need to
6832a1795fSJyri Sarha 	 * check for odd height).
6932a1795fSJyri Sarha 	 */
7032a1795fSJyri Sarha 
71ba5c1649SMaxime Ripard 	finfo = drm_format_info(new_plane_state->fb->format->format);
7232a1795fSJyri Sarha 
73ba5c1649SMaxime Ripard 	if ((new_plane_state->src_x >> 16) % finfo->hsub != 0) {
7432a1795fSJyri Sarha 		dev_dbg(ddev->dev,
7532a1795fSJyri Sarha 			"%s: x-position %u not divisible subpixel size %u\n",
76ba5c1649SMaxime Ripard 			__func__, (new_plane_state->src_x >> 16), finfo->hsub);
7732a1795fSJyri Sarha 		return -EINVAL;
7832a1795fSJyri Sarha 	}
7932a1795fSJyri Sarha 
80ba5c1649SMaxime Ripard 	if ((new_plane_state->src_y >> 16) % finfo->vsub != 0) {
8132a1795fSJyri Sarha 		dev_dbg(ddev->dev,
8232a1795fSJyri Sarha 			"%s: y-position %u not divisible subpixel size %u\n",
83ba5c1649SMaxime Ripard 			__func__, (new_plane_state->src_y >> 16), finfo->vsub);
8432a1795fSJyri Sarha 		return -EINVAL;
8532a1795fSJyri Sarha 	}
8632a1795fSJyri Sarha 
87ba5c1649SMaxime Ripard 	if ((new_plane_state->src_w >> 16) % finfo->hsub != 0) {
8832a1795fSJyri Sarha 		dev_dbg(ddev->dev,
8932a1795fSJyri Sarha 			"%s: src width %u not divisible by subpixel size %u\n",
90ba5c1649SMaxime Ripard 			 __func__, (new_plane_state->src_w >> 16),
91ba5c1649SMaxime Ripard 			 finfo->hsub);
9232a1795fSJyri Sarha 		return -EINVAL;
9332a1795fSJyri Sarha 	}
9432a1795fSJyri Sarha 
95ba5c1649SMaxime Ripard 	if (!new_plane_state->visible)
9632a1795fSJyri Sarha 		return 0;
9732a1795fSJyri Sarha 
98ba5c1649SMaxime Ripard 	hw_videoport = to_tidss_crtc(new_plane_state->crtc)->hw_videoport;
9932a1795fSJyri Sarha 
100ba5c1649SMaxime Ripard 	ret = dispc_plane_check(tidss->dispc, hw_plane, new_plane_state,
101ba5c1649SMaxime Ripard 				hw_videoport);
10232a1795fSJyri Sarha 	if (ret)
10332a1795fSJyri Sarha 		return ret;
10432a1795fSJyri Sarha 
10532a1795fSJyri Sarha 	return 0;
10632a1795fSJyri Sarha }
10732a1795fSJyri Sarha 
10832a1795fSJyri Sarha static void tidss_plane_atomic_update(struct drm_plane *plane,
109977697e2SMaxime Ripard 				      struct drm_atomic_state *state)
11032a1795fSJyri Sarha {
11132a1795fSJyri Sarha 	struct drm_device *ddev = plane->dev;
11202bb1317SDaniel Vetter 	struct tidss_device *tidss = to_tidss(ddev);
11332a1795fSJyri Sarha 	struct tidss_plane *tplane = to_tidss_plane(plane);
11437418bf1SMaxime Ripard 	struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
11537418bf1SMaxime Ripard 									   plane);
11632a1795fSJyri Sarha 	u32 hw_videoport;
11732a1795fSJyri Sarha 	int ret;
11832a1795fSJyri Sarha 
11932a1795fSJyri Sarha 	dev_dbg(ddev->dev, "%s\n", __func__);
12032a1795fSJyri Sarha 
12141016fe1SMaxime Ripard 	if (!new_state->visible) {
12232a1795fSJyri Sarha 		dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
12332a1795fSJyri Sarha 		return;
12432a1795fSJyri Sarha 	}
12532a1795fSJyri Sarha 
12641016fe1SMaxime Ripard 	hw_videoport = to_tidss_crtc(new_state->crtc)->hw_videoport;
12732a1795fSJyri Sarha 
12832a1795fSJyri Sarha 	ret = dispc_plane_setup(tidss->dispc, tplane->hw_plane_id,
12941016fe1SMaxime Ripard 				new_state, hw_videoport);
13032a1795fSJyri Sarha 
13132a1795fSJyri Sarha 	if (ret) {
13232a1795fSJyri Sarha 		dev_err(plane->dev->dev, "%s: Failed to setup plane %d\n",
13332a1795fSJyri Sarha 			__func__, tplane->hw_plane_id);
13432a1795fSJyri Sarha 		dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
13532a1795fSJyri Sarha 		return;
13632a1795fSJyri Sarha 	}
13732a1795fSJyri Sarha 
13832a1795fSJyri Sarha 	dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, true);
13932a1795fSJyri Sarha }
14032a1795fSJyri Sarha 
14132a1795fSJyri Sarha static void tidss_plane_atomic_disable(struct drm_plane *plane,
142977697e2SMaxime Ripard 				       struct drm_atomic_state *state)
14332a1795fSJyri Sarha {
14432a1795fSJyri Sarha 	struct drm_device *ddev = plane->dev;
14502bb1317SDaniel Vetter 	struct tidss_device *tidss = to_tidss(ddev);
14632a1795fSJyri Sarha 	struct tidss_plane *tplane = to_tidss_plane(plane);
14732a1795fSJyri Sarha 
14832a1795fSJyri Sarha 	dev_dbg(ddev->dev, "%s\n", __func__);
14932a1795fSJyri Sarha 
15032a1795fSJyri Sarha 	dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
15132a1795fSJyri Sarha }
15232a1795fSJyri Sarha 
1539da67433STomi Valkeinen static void drm_plane_destroy(struct drm_plane *plane)
1549da67433STomi Valkeinen {
1559da67433STomi Valkeinen 	struct tidss_plane *tplane = to_tidss_plane(plane);
1569da67433STomi Valkeinen 
1579da67433STomi Valkeinen 	drm_plane_cleanup(plane);
1589da67433STomi Valkeinen 	kfree(tplane);
1599da67433STomi Valkeinen }
1609da67433STomi Valkeinen 
16132a1795fSJyri Sarha static const struct drm_plane_helper_funcs tidss_plane_helper_funcs = {
16232a1795fSJyri Sarha 	.atomic_check = tidss_plane_atomic_check,
16332a1795fSJyri Sarha 	.atomic_update = tidss_plane_atomic_update,
16432a1795fSJyri Sarha 	.atomic_disable = tidss_plane_atomic_disable,
16532a1795fSJyri Sarha };
16632a1795fSJyri Sarha 
16732a1795fSJyri Sarha static const struct drm_plane_funcs tidss_plane_funcs = {
16832a1795fSJyri Sarha 	.update_plane = drm_atomic_helper_update_plane,
16932a1795fSJyri Sarha 	.disable_plane = drm_atomic_helper_disable_plane,
17032a1795fSJyri Sarha 	.reset = drm_atomic_helper_plane_reset,
1719da67433STomi Valkeinen 	.destroy = drm_plane_destroy,
17232a1795fSJyri Sarha 	.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
17332a1795fSJyri Sarha 	.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
17432a1795fSJyri Sarha };
17532a1795fSJyri Sarha 
17632a1795fSJyri Sarha struct tidss_plane *tidss_plane_create(struct tidss_device *tidss,
17732a1795fSJyri Sarha 				       u32 hw_plane_id, u32 plane_type,
17832a1795fSJyri Sarha 				       u32 crtc_mask, const u32 *formats,
17932a1795fSJyri Sarha 				       u32 num_formats)
18032a1795fSJyri Sarha {
18132a1795fSJyri Sarha 	struct tidss_plane *tplane;
18232a1795fSJyri Sarha 	enum drm_plane_type type;
18332a1795fSJyri Sarha 	u32 possible_crtcs;
18432a1795fSJyri Sarha 	u32 num_planes = tidss->feat->num_planes;
18532a1795fSJyri Sarha 	u32 color_encodings = (BIT(DRM_COLOR_YCBCR_BT601) |
18632a1795fSJyri Sarha 			       BIT(DRM_COLOR_YCBCR_BT709));
18732a1795fSJyri Sarha 	u32 color_ranges = (BIT(DRM_COLOR_YCBCR_FULL_RANGE) |
18832a1795fSJyri Sarha 			    BIT(DRM_COLOR_YCBCR_LIMITED_RANGE));
18932a1795fSJyri Sarha 	u32 default_encoding = DRM_COLOR_YCBCR_BT601;
19032a1795fSJyri Sarha 	u32 default_range = DRM_COLOR_YCBCR_FULL_RANGE;
19132a1795fSJyri Sarha 	u32 blend_modes = (BIT(DRM_MODE_BLEND_PREMULTI) |
19232a1795fSJyri Sarha 			   BIT(DRM_MODE_BLEND_COVERAGE));
19332a1795fSJyri Sarha 	int ret;
19432a1795fSJyri Sarha 
1959da67433STomi Valkeinen 	tplane = kzalloc(sizeof(*tplane), GFP_KERNEL);
19632a1795fSJyri Sarha 	if (!tplane)
19732a1795fSJyri Sarha 		return ERR_PTR(-ENOMEM);
19832a1795fSJyri Sarha 
19932a1795fSJyri Sarha 	tplane->hw_plane_id = hw_plane_id;
20032a1795fSJyri Sarha 
20132a1795fSJyri Sarha 	possible_crtcs = crtc_mask;
20232a1795fSJyri Sarha 	type = plane_type;
20332a1795fSJyri Sarha 
20432a1795fSJyri Sarha 	ret = drm_universal_plane_init(&tidss->ddev, &tplane->plane,
20532a1795fSJyri Sarha 				       possible_crtcs,
20632a1795fSJyri Sarha 				       &tidss_plane_funcs,
20732a1795fSJyri Sarha 				       formats, num_formats,
20832a1795fSJyri Sarha 				       NULL, type, NULL);
20932a1795fSJyri Sarha 	if (ret < 0)
2109da67433STomi Valkeinen 		goto err;
21132a1795fSJyri Sarha 
21232a1795fSJyri Sarha 	drm_plane_helper_add(&tplane->plane, &tidss_plane_helper_funcs);
21332a1795fSJyri Sarha 
21432a1795fSJyri Sarha 	drm_plane_create_zpos_property(&tplane->plane, hw_plane_id, 0,
21532a1795fSJyri Sarha 				       num_planes - 1);
21632a1795fSJyri Sarha 
21732a1795fSJyri Sarha 	ret = drm_plane_create_color_properties(&tplane->plane,
21832a1795fSJyri Sarha 						color_encodings,
21932a1795fSJyri Sarha 						color_ranges,
22032a1795fSJyri Sarha 						default_encoding,
22132a1795fSJyri Sarha 						default_range);
22232a1795fSJyri Sarha 	if (ret)
2239da67433STomi Valkeinen 		goto err;
22432a1795fSJyri Sarha 
22532a1795fSJyri Sarha 	ret = drm_plane_create_alpha_property(&tplane->plane);
22632a1795fSJyri Sarha 	if (ret)
2279da67433STomi Valkeinen 		goto err;
22832a1795fSJyri Sarha 
22932a1795fSJyri Sarha 	ret = drm_plane_create_blend_mode_property(&tplane->plane, blend_modes);
23032a1795fSJyri Sarha 	if (ret)
2319da67433STomi Valkeinen 		goto err;
23232a1795fSJyri Sarha 
23332a1795fSJyri Sarha 	return tplane;
2349da67433STomi Valkeinen 
2359da67433STomi Valkeinen err:
2369da67433STomi Valkeinen 	kfree(tplane);
2379da67433STomi Valkeinen 	return ERR_PTR(ret);
23832a1795fSJyri Sarha }
239