132a1795fSJyri Sarha /* SPDX-License-Identifier: GPL-2.0 */ 232a1795fSJyri Sarha /* 332a1795fSJyri Sarha * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 432a1795fSJyri Sarha * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 532a1795fSJyri Sarha */ 632a1795fSJyri Sarha 732a1795fSJyri Sarha #ifndef __TIDSS_DISPC_H__ 832a1795fSJyri Sarha #define __TIDSS_DISPC_H__ 932a1795fSJyri Sarha 1032a1795fSJyri Sarha #include "tidss_drv.h" 1132a1795fSJyri Sarha 1232a1795fSJyri Sarha struct dispc_device; 1332a1795fSJyri Sarha 1432a1795fSJyri Sarha struct drm_crtc_state; 1532a1795fSJyri Sarha 1632a1795fSJyri Sarha enum tidss_gamma_type { TIDSS_GAMMA_8BIT, TIDSS_GAMMA_10BIT }; 1732a1795fSJyri Sarha 1832a1795fSJyri Sarha struct tidss_vp_feat { 1932a1795fSJyri Sarha struct tidss_vp_color_feat { 2032a1795fSJyri Sarha u32 gamma_size; 2132a1795fSJyri Sarha enum tidss_gamma_type gamma_type; 2232a1795fSJyri Sarha bool has_ctm; 2332a1795fSJyri Sarha } color; 2432a1795fSJyri Sarha }; 2532a1795fSJyri Sarha 2632a1795fSJyri Sarha struct tidss_plane_feat { 2732a1795fSJyri Sarha struct tidss_plane_color_feat { 2832a1795fSJyri Sarha u32 encodings; 2932a1795fSJyri Sarha u32 ranges; 3032a1795fSJyri Sarha enum drm_color_encoding default_encoding; 3132a1795fSJyri Sarha enum drm_color_range default_range; 3232a1795fSJyri Sarha } color; 3332a1795fSJyri Sarha struct tidss_plane_blend_feat { 3432a1795fSJyri Sarha bool global_alpha; 3532a1795fSJyri Sarha } blend; 3632a1795fSJyri Sarha }; 3732a1795fSJyri Sarha 3832a1795fSJyri Sarha struct dispc_features_scaling { 3932a1795fSJyri Sarha u32 in_width_max_5tap_rgb; 4032a1795fSJyri Sarha u32 in_width_max_3tap_rgb; 4132a1795fSJyri Sarha u32 in_width_max_5tap_yuv; 4232a1795fSJyri Sarha u32 in_width_max_3tap_yuv; 4332a1795fSJyri Sarha u32 upscale_limit; 4432a1795fSJyri Sarha u32 downscale_limit_5tap; 4532a1795fSJyri Sarha u32 downscale_limit_3tap; 4632a1795fSJyri Sarha u32 xinc_max; 4732a1795fSJyri Sarha }; 4832a1795fSJyri Sarha 4932a1795fSJyri Sarha struct dispc_errata { 5032a1795fSJyri Sarha bool i2000; /* DSS Does Not Support YUV Pixel Data Formats */ 5132a1795fSJyri Sarha }; 5232a1795fSJyri Sarha 5332a1795fSJyri Sarha enum dispc_vp_bus_type { 5432a1795fSJyri Sarha DISPC_VP_DPI, /* DPI output */ 5532a1795fSJyri Sarha DISPC_VP_OLDI, /* OLDI (LVDS) output */ 5632a1795fSJyri Sarha DISPC_VP_INTERNAL, /* SoC internal routing */ 5732a1795fSJyri Sarha DISPC_VP_MAX_BUS_TYPE, 5832a1795fSJyri Sarha }; 5932a1795fSJyri Sarha 6032a1795fSJyri Sarha enum dispc_dss_subrevision { 6132a1795fSJyri Sarha DISPC_K2G, 6232a1795fSJyri Sarha DISPC_AM65X, 6332a1795fSJyri Sarha DISPC_J721E, 6432a1795fSJyri Sarha }; 6532a1795fSJyri Sarha 6632a1795fSJyri Sarha struct dispc_features { 6732a1795fSJyri Sarha int min_pclk_khz; 6832a1795fSJyri Sarha int max_pclk_khz[DISPC_VP_MAX_BUS_TYPE]; 6932a1795fSJyri Sarha 7032a1795fSJyri Sarha struct dispc_features_scaling scaling; 7132a1795fSJyri Sarha 7232a1795fSJyri Sarha enum dispc_dss_subrevision subrev; 7332a1795fSJyri Sarha 7432a1795fSJyri Sarha const char *common; 7532a1795fSJyri Sarha const u16 *common_regs; 7632a1795fSJyri Sarha u32 num_vps; 7732a1795fSJyri Sarha const char *vp_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ 7832a1795fSJyri Sarha const char *ovr_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ 7932a1795fSJyri Sarha const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */ 8032a1795fSJyri Sarha const enum dispc_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS]; 8132a1795fSJyri Sarha struct tidss_vp_feat vp_feat; 8232a1795fSJyri Sarha u32 num_planes; 8332a1795fSJyri Sarha const char *vid_name[TIDSS_MAX_PLANES]; /* Should match dt reg names */ 8432a1795fSJyri Sarha bool vid_lite[TIDSS_MAX_PLANES]; 8532a1795fSJyri Sarha u32 vid_order[TIDSS_MAX_PLANES]; 8632a1795fSJyri Sarha 8732a1795fSJyri Sarha struct dispc_errata errata; 8832a1795fSJyri Sarha }; 8932a1795fSJyri Sarha 9032a1795fSJyri Sarha extern const struct dispc_features dispc_k2g_feats; 9132a1795fSJyri Sarha extern const struct dispc_features dispc_am65x_feats; 9232a1795fSJyri Sarha extern const struct dispc_features dispc_j721e_feats; 9332a1795fSJyri Sarha 9432a1795fSJyri Sarha void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask); 9532a1795fSJyri Sarha dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc); 9632a1795fSJyri Sarha 9732a1795fSJyri Sarha void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport, 9832a1795fSJyri Sarha const struct drm_crtc_state *state); 9932a1795fSJyri Sarha void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, 10032a1795fSJyri Sarha const struct drm_crtc_state *state); 10132a1795fSJyri Sarha void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport); 10232a1795fSJyri Sarha void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport); 10332a1795fSJyri Sarha bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport); 10432a1795fSJyri Sarha void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport); 10532a1795fSJyri Sarha int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport, 10632a1795fSJyri Sarha const struct drm_crtc_state *state); 10732a1795fSJyri Sarha enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc, 10832a1795fSJyri Sarha u32 hw_videoport, 10932a1795fSJyri Sarha const struct drm_display_mode *mode); 11032a1795fSJyri Sarha int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport); 11132a1795fSJyri Sarha void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport); 11232a1795fSJyri Sarha int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport, 11332a1795fSJyri Sarha unsigned long rate); 11432a1795fSJyri Sarha void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport, 11532a1795fSJyri Sarha const struct drm_crtc_state *state, bool newmodeset); 11632a1795fSJyri Sarha 11732a1795fSJyri Sarha int dispc_runtime_suspend(struct dispc_device *dispc); 11832a1795fSJyri Sarha int dispc_runtime_resume(struct dispc_device *dispc); 11932a1795fSJyri Sarha 12032a1795fSJyri Sarha int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane, 12132a1795fSJyri Sarha const struct drm_plane_state *state, 12232a1795fSJyri Sarha u32 hw_videoport); 12332a1795fSJyri Sarha int dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane, 12432a1795fSJyri Sarha const struct drm_plane_state *state, 12532a1795fSJyri Sarha u32 hw_videoport); 12632a1795fSJyri Sarha int dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable); 12732a1795fSJyri Sarha const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len); 12832a1795fSJyri Sarha 12932a1795fSJyri Sarha int dispc_init(struct tidss_device *tidss); 13032a1795fSJyri Sarha void dispc_remove(struct tidss_device *tidss); 13132a1795fSJyri Sarha 13232a1795fSJyri Sarha #endif 133