1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, NVIDIA Corporation. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/host1x.h> 9 #include <linux/iommu.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/reset.h> 17 18 #include <soc/tegra/pmc.h> 19 20 #include "drm.h" 21 #include "falcon.h" 22 #include "vic.h" 23 24 struct vic_config { 25 const char *firmware; 26 unsigned int version; 27 bool supports_sid; 28 }; 29 30 struct vic { 31 struct falcon falcon; 32 33 void __iomem *regs; 34 struct tegra_drm_client client; 35 struct host1x_channel *channel; 36 struct device *dev; 37 struct clk *clk; 38 struct reset_control *rst; 39 40 /* Platform configuration */ 41 const struct vic_config *config; 42 }; 43 44 static inline struct vic *to_vic(struct tegra_drm_client *client) 45 { 46 return container_of(client, struct vic, client); 47 } 48 49 static void vic_writel(struct vic *vic, u32 value, unsigned int offset) 50 { 51 writel(value, vic->regs + offset); 52 } 53 54 static int vic_boot(struct vic *vic) 55 { 56 #ifdef CONFIG_IOMMU_API 57 struct iommu_fwspec *spec = dev_iommu_fwspec_get(vic->dev); 58 #endif 59 u32 fce_ucode_size, fce_bin_data_offset; 60 void *hdr; 61 int err = 0; 62 63 #ifdef CONFIG_IOMMU_API 64 if (vic->config->supports_sid && spec) { 65 u32 value; 66 67 value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | 68 TRANSCFG_ATT(0, TRANSCFG_SID_HW); 69 vic_writel(vic, value, VIC_TFBIF_TRANSCFG); 70 71 if (spec->num_ids > 0) { 72 value = spec->ids[0] & 0xffff; 73 74 /* 75 * STREAMID0 is used for input/output buffers. 76 * Initialize it to SID_VIC in case context isolation 77 * is not enabled, and SID_VIC is used for both firmware 78 * and data buffers. 79 * 80 * If context isolation is enabled, it will be 81 * overridden by the SETSTREAMID opcode as part of 82 * each job. 83 */ 84 vic_writel(vic, value, VIC_THI_STREAMID0); 85 86 /* STREAMID1 is used for firmware loading. */ 87 vic_writel(vic, value, VIC_THI_STREAMID1); 88 } 89 } 90 #endif 91 92 /* setup clockgating registers */ 93 vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) | 94 CG_IDLE_CG_EN | 95 CG_WAKEUP_DLY_CNT(4), 96 NV_PVIC_MISC_PRI_VIC_CG); 97 98 err = falcon_boot(&vic->falcon); 99 if (err < 0) 100 return err; 101 102 hdr = vic->falcon.firmware.virt; 103 fce_bin_data_offset = *(u32 *)(hdr + VIC_UCODE_FCE_DATA_OFFSET); 104 105 /* Old VIC firmware needs kernel help with setting up FCE microcode. */ 106 if (fce_bin_data_offset != 0x0 && fce_bin_data_offset != 0xa5a5a5a5) { 107 hdr = vic->falcon.firmware.virt + 108 *(u32 *)(hdr + VIC_UCODE_FCE_HEADER_OFFSET); 109 fce_ucode_size = *(u32 *)(hdr + FCE_UCODE_SIZE_OFFSET); 110 111 falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE, 112 fce_ucode_size); 113 falcon_execute_method( 114 &vic->falcon, VIC_SET_FCE_UCODE_OFFSET, 115 (vic->falcon.firmware.iova + fce_bin_data_offset) >> 8); 116 } 117 118 err = falcon_wait_idle(&vic->falcon); 119 if (err < 0) { 120 dev_err(vic->dev, 121 "failed to set application ID and FCE base\n"); 122 return err; 123 } 124 125 return 0; 126 } 127 128 static int vic_init(struct host1x_client *client) 129 { 130 struct tegra_drm_client *drm = host1x_to_drm_client(client); 131 struct drm_device *dev = dev_get_drvdata(client->host); 132 struct tegra_drm *tegra = dev->dev_private; 133 struct vic *vic = to_vic(drm); 134 int err; 135 136 err = host1x_client_iommu_attach(client); 137 if (err < 0 && err != -ENODEV) { 138 dev_err(vic->dev, "failed to attach to domain: %d\n", err); 139 return err; 140 } 141 142 vic->channel = host1x_channel_request(client); 143 if (!vic->channel) { 144 err = -ENOMEM; 145 goto detach; 146 } 147 148 client->syncpts[0] = host1x_syncpt_request(client, 0); 149 if (!client->syncpts[0]) { 150 err = -ENOMEM; 151 goto free_channel; 152 } 153 154 err = tegra_drm_register_client(tegra, drm); 155 if (err < 0) 156 goto free_syncpt; 157 158 /* 159 * Inherit the DMA parameters (such as maximum segment size) from the 160 * parent host1x device. 161 */ 162 client->dev->dma_parms = client->host->dma_parms; 163 164 return 0; 165 166 free_syncpt: 167 host1x_syncpt_put(client->syncpts[0]); 168 free_channel: 169 host1x_channel_put(vic->channel); 170 detach: 171 host1x_client_iommu_detach(client); 172 173 return err; 174 } 175 176 static int vic_exit(struct host1x_client *client) 177 { 178 struct tegra_drm_client *drm = host1x_to_drm_client(client); 179 struct drm_device *dev = dev_get_drvdata(client->host); 180 struct tegra_drm *tegra = dev->dev_private; 181 struct vic *vic = to_vic(drm); 182 int err; 183 184 /* avoid a dangling pointer just in case this disappears */ 185 client->dev->dma_parms = NULL; 186 187 err = tegra_drm_unregister_client(tegra, drm); 188 if (err < 0) 189 return err; 190 191 host1x_syncpt_put(client->syncpts[0]); 192 host1x_channel_put(vic->channel); 193 host1x_client_iommu_detach(client); 194 195 if (client->group) { 196 dma_unmap_single(vic->dev, vic->falcon.firmware.phys, 197 vic->falcon.firmware.size, DMA_TO_DEVICE); 198 tegra_drm_free(tegra, vic->falcon.firmware.size, 199 vic->falcon.firmware.virt, 200 vic->falcon.firmware.iova); 201 } else { 202 dma_free_coherent(vic->dev, vic->falcon.firmware.size, 203 vic->falcon.firmware.virt, 204 vic->falcon.firmware.iova); 205 } 206 207 return 0; 208 } 209 210 static const struct host1x_client_ops vic_client_ops = { 211 .init = vic_init, 212 .exit = vic_exit, 213 }; 214 215 static int vic_load_firmware(struct vic *vic) 216 { 217 struct host1x_client *client = &vic->client.base; 218 struct tegra_drm *tegra = vic->client.drm; 219 dma_addr_t iova; 220 size_t size; 221 void *virt; 222 int err; 223 224 if (vic->falcon.firmware.virt) 225 return 0; 226 227 err = falcon_read_firmware(&vic->falcon, vic->config->firmware); 228 if (err < 0) 229 return err; 230 231 size = vic->falcon.firmware.size; 232 233 if (!client->group) { 234 virt = dma_alloc_coherent(vic->dev, size, &iova, GFP_KERNEL); 235 236 err = dma_mapping_error(vic->dev, iova); 237 if (err < 0) 238 return err; 239 } else { 240 virt = tegra_drm_alloc(tegra, size, &iova); 241 } 242 243 vic->falcon.firmware.virt = virt; 244 vic->falcon.firmware.iova = iova; 245 246 err = falcon_load_firmware(&vic->falcon); 247 if (err < 0) 248 goto cleanup; 249 250 /* 251 * In this case we have received an IOVA from the shared domain, so we 252 * need to make sure to get the physical address so that the DMA API 253 * knows what memory pages to flush the cache for. 254 */ 255 if (client->group) { 256 dma_addr_t phys; 257 258 phys = dma_map_single(vic->dev, virt, size, DMA_TO_DEVICE); 259 260 err = dma_mapping_error(vic->dev, phys); 261 if (err < 0) 262 goto cleanup; 263 264 vic->falcon.firmware.phys = phys; 265 } 266 267 return 0; 268 269 cleanup: 270 if (!client->group) 271 dma_free_coherent(vic->dev, size, virt, iova); 272 else 273 tegra_drm_free(tegra, size, virt, iova); 274 275 return err; 276 } 277 278 279 static int vic_runtime_resume(struct device *dev) 280 { 281 struct vic *vic = dev_get_drvdata(dev); 282 int err; 283 284 err = clk_prepare_enable(vic->clk); 285 if (err < 0) 286 return err; 287 288 usleep_range(10, 20); 289 290 err = reset_control_deassert(vic->rst); 291 if (err < 0) 292 goto disable; 293 294 usleep_range(10, 20); 295 296 err = vic_load_firmware(vic); 297 if (err < 0) 298 goto assert; 299 300 err = vic_boot(vic); 301 if (err < 0) 302 goto assert; 303 304 return 0; 305 306 assert: 307 reset_control_assert(vic->rst); 308 disable: 309 clk_disable_unprepare(vic->clk); 310 return err; 311 } 312 313 static int vic_runtime_suspend(struct device *dev) 314 { 315 struct vic *vic = dev_get_drvdata(dev); 316 int err; 317 318 err = reset_control_assert(vic->rst); 319 if (err < 0) 320 return err; 321 322 usleep_range(2000, 4000); 323 324 clk_disable_unprepare(vic->clk); 325 326 return 0; 327 } 328 329 static int vic_open_channel(struct tegra_drm_client *client, 330 struct tegra_drm_context *context) 331 { 332 struct vic *vic = to_vic(client); 333 int err; 334 335 err = pm_runtime_resume_and_get(vic->dev); 336 if (err < 0) 337 return err; 338 339 context->channel = host1x_channel_get(vic->channel); 340 if (!context->channel) { 341 pm_runtime_put(vic->dev); 342 return -ENOMEM; 343 } 344 345 return 0; 346 } 347 348 static void vic_close_channel(struct tegra_drm_context *context) 349 { 350 struct vic *vic = to_vic(context->client); 351 352 host1x_channel_put(context->channel); 353 pm_runtime_put(vic->dev); 354 } 355 356 static const struct tegra_drm_client_ops vic_ops = { 357 .open_channel = vic_open_channel, 358 .close_channel = vic_close_channel, 359 .submit = tegra_drm_submit, 360 }; 361 362 #define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin" 363 364 static const struct vic_config vic_t124_config = { 365 .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE, 366 .version = 0x40, 367 .supports_sid = false, 368 }; 369 370 #define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin" 371 372 static const struct vic_config vic_t210_config = { 373 .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE, 374 .version = 0x21, 375 .supports_sid = false, 376 }; 377 378 #define NVIDIA_TEGRA_186_VIC_FIRMWARE "nvidia/tegra186/vic04_ucode.bin" 379 380 static const struct vic_config vic_t186_config = { 381 .firmware = NVIDIA_TEGRA_186_VIC_FIRMWARE, 382 .version = 0x18, 383 .supports_sid = true, 384 }; 385 386 #define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin" 387 388 static const struct vic_config vic_t194_config = { 389 .firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE, 390 .version = 0x19, 391 .supports_sid = true, 392 }; 393 394 static const struct of_device_id tegra_vic_of_match[] = { 395 { .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config }, 396 { .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config }, 397 { .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config }, 398 { .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config }, 399 { }, 400 }; 401 MODULE_DEVICE_TABLE(of, tegra_vic_of_match); 402 403 static int vic_probe(struct platform_device *pdev) 404 { 405 struct device *dev = &pdev->dev; 406 struct host1x_syncpt **syncpts; 407 struct resource *regs; 408 struct vic *vic; 409 int err; 410 411 /* inherit DMA mask from host1x parent */ 412 err = dma_coerce_mask_and_coherent(dev, *dev->parent->dma_mask); 413 if (err < 0) { 414 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 415 return err; 416 } 417 418 vic = devm_kzalloc(dev, sizeof(*vic), GFP_KERNEL); 419 if (!vic) 420 return -ENOMEM; 421 422 vic->config = of_device_get_match_data(dev); 423 424 syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL); 425 if (!syncpts) 426 return -ENOMEM; 427 428 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 429 if (!regs) { 430 dev_err(&pdev->dev, "failed to get registers\n"); 431 return -ENXIO; 432 } 433 434 vic->regs = devm_ioremap_resource(dev, regs); 435 if (IS_ERR(vic->regs)) 436 return PTR_ERR(vic->regs); 437 438 vic->clk = devm_clk_get(dev, NULL); 439 if (IS_ERR(vic->clk)) { 440 dev_err(&pdev->dev, "failed to get clock\n"); 441 return PTR_ERR(vic->clk); 442 } 443 444 if (!dev->pm_domain) { 445 vic->rst = devm_reset_control_get(dev, "vic"); 446 if (IS_ERR(vic->rst)) { 447 dev_err(&pdev->dev, "failed to get reset\n"); 448 return PTR_ERR(vic->rst); 449 } 450 } 451 452 vic->falcon.dev = dev; 453 vic->falcon.regs = vic->regs; 454 455 err = falcon_init(&vic->falcon); 456 if (err < 0) 457 return err; 458 459 platform_set_drvdata(pdev, vic); 460 461 INIT_LIST_HEAD(&vic->client.base.list); 462 vic->client.base.ops = &vic_client_ops; 463 vic->client.base.dev = dev; 464 vic->client.base.class = HOST1X_CLASS_VIC; 465 vic->client.base.syncpts = syncpts; 466 vic->client.base.num_syncpts = 1; 467 vic->dev = dev; 468 469 INIT_LIST_HEAD(&vic->client.list); 470 vic->client.version = vic->config->version; 471 vic->client.ops = &vic_ops; 472 473 err = host1x_client_register(&vic->client.base); 474 if (err < 0) { 475 dev_err(dev, "failed to register host1x client: %d\n", err); 476 goto exit_falcon; 477 } 478 479 pm_runtime_enable(&pdev->dev); 480 if (!pm_runtime_enabled(&pdev->dev)) { 481 err = vic_runtime_resume(&pdev->dev); 482 if (err < 0) 483 goto unregister_client; 484 } 485 486 return 0; 487 488 unregister_client: 489 host1x_client_unregister(&vic->client.base); 490 exit_falcon: 491 falcon_exit(&vic->falcon); 492 493 return err; 494 } 495 496 static int vic_remove(struct platform_device *pdev) 497 { 498 struct vic *vic = platform_get_drvdata(pdev); 499 int err; 500 501 err = host1x_client_unregister(&vic->client.base); 502 if (err < 0) { 503 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 504 err); 505 return err; 506 } 507 508 if (pm_runtime_enabled(&pdev->dev)) 509 pm_runtime_disable(&pdev->dev); 510 else 511 vic_runtime_suspend(&pdev->dev); 512 513 falcon_exit(&vic->falcon); 514 515 return 0; 516 } 517 518 static const struct dev_pm_ops vic_pm_ops = { 519 SET_RUNTIME_PM_OPS(vic_runtime_suspend, vic_runtime_resume, NULL) 520 }; 521 522 struct platform_driver tegra_vic_driver = { 523 .driver = { 524 .name = "tegra-vic", 525 .of_match_table = tegra_vic_of_match, 526 .pm = &vic_pm_ops 527 }, 528 .probe = vic_probe, 529 .remove = vic_remove, 530 }; 531 532 #if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) 533 MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE); 534 #endif 535 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) 536 MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE); 537 #endif 538 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) 539 MODULE_FIRMWARE(NVIDIA_TEGRA_186_VIC_FIRMWARE); 540 #endif 541 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) 542 MODULE_FIRMWARE(NVIDIA_TEGRA_194_VIC_FIRMWARE); 543 #endif 544