1 /* 2 * Copyright (C) 2013 NVIDIA Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/debugfs.h> 11 #include <linux/io.h> 12 #include <linux/platform_device.h> 13 #include <linux/reset.h> 14 #include <linux/tegra-powergate.h> 15 16 #include <drm/drm_dp_helper.h> 17 18 #include "dc.h" 19 #include "drm.h" 20 #include "sor.h" 21 22 struct tegra_sor { 23 struct host1x_client client; 24 struct tegra_output output; 25 struct device *dev; 26 27 void __iomem *regs; 28 29 struct reset_control *rst; 30 struct clk *clk_parent; 31 struct clk *clk_safe; 32 struct clk *clk_dp; 33 struct clk *clk; 34 35 struct tegra_dpaux *dpaux; 36 37 struct mutex lock; 38 bool enabled; 39 40 struct dentry *debugfs; 41 }; 42 43 struct tegra_sor_config { 44 u32 bits_per_pixel; 45 46 u32 active_polarity; 47 u32 active_count; 48 u32 tu_size; 49 u32 active_frac; 50 u32 watermark; 51 52 u32 hblank_symbols; 53 u32 vblank_symbols; 54 }; 55 56 static inline struct tegra_sor * 57 host1x_client_to_sor(struct host1x_client *client) 58 { 59 return container_of(client, struct tegra_sor, client); 60 } 61 62 static inline struct tegra_sor *to_sor(struct tegra_output *output) 63 { 64 return container_of(output, struct tegra_sor, output); 65 } 66 67 static inline unsigned long tegra_sor_readl(struct tegra_sor *sor, 68 unsigned long offset) 69 { 70 return readl(sor->regs + (offset << 2)); 71 } 72 73 static inline void tegra_sor_writel(struct tegra_sor *sor, unsigned long value, 74 unsigned long offset) 75 { 76 writel(value, sor->regs + (offset << 2)); 77 } 78 79 static int tegra_sor_dp_train_fast(struct tegra_sor *sor, 80 struct drm_dp_link *link) 81 { 82 unsigned long value; 83 unsigned int i; 84 u8 pattern; 85 int err; 86 87 /* setup lane parameters */ 88 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | 89 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) | 90 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) | 91 SOR_LANE_DRIVE_CURRENT_LANE0(0x40); 92 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT_0); 93 94 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | 95 SOR_LANE_PREEMPHASIS_LANE2(0x0f) | 96 SOR_LANE_PREEMPHASIS_LANE1(0x0f) | 97 SOR_LANE_PREEMPHASIS_LANE0(0x0f); 98 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS_0); 99 100 value = SOR_LANE_POST_CURSOR_LANE3(0x00) | 101 SOR_LANE_POST_CURSOR_LANE2(0x00) | 102 SOR_LANE_POST_CURSOR_LANE1(0x00) | 103 SOR_LANE_POST_CURSOR_LANE0(0x00); 104 tegra_sor_writel(sor, value, SOR_LANE_POST_CURSOR_0); 105 106 /* disable LVDS mode */ 107 tegra_sor_writel(sor, 0, SOR_LVDS); 108 109 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 110 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 111 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 112 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ 113 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 114 115 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 116 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 117 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0; 118 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 119 120 usleep_range(10, 100); 121 122 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 123 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 124 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); 125 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 126 127 err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B); 128 if (err < 0) 129 return err; 130 131 for (i = 0, value = 0; i < link->num_lanes; i++) { 132 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 133 SOR_DP_TPG_SCRAMBLER_NONE | 134 SOR_DP_TPG_PATTERN_TRAIN1; 135 value = (value << 8) | lane; 136 } 137 138 tegra_sor_writel(sor, value, SOR_DP_TPG); 139 140 pattern = DP_TRAINING_PATTERN_1; 141 142 err = tegra_dpaux_train(sor->dpaux, link, pattern); 143 if (err < 0) 144 return err; 145 146 value = tegra_sor_readl(sor, SOR_DP_SPARE_0); 147 value |= SOR_DP_SPARE_SEQ_ENABLE; 148 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 149 value |= SOR_DP_SPARE_MACRO_SOR_CLK; 150 tegra_sor_writel(sor, value, SOR_DP_SPARE_0); 151 152 for (i = 0, value = 0; i < link->num_lanes; i++) { 153 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 154 SOR_DP_TPG_SCRAMBLER_NONE | 155 SOR_DP_TPG_PATTERN_TRAIN2; 156 value = (value << 8) | lane; 157 } 158 159 tegra_sor_writel(sor, value, SOR_DP_TPG); 160 161 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2; 162 163 err = tegra_dpaux_train(sor->dpaux, link, pattern); 164 if (err < 0) 165 return err; 166 167 for (i = 0, value = 0; i < link->num_lanes; i++) { 168 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 169 SOR_DP_TPG_SCRAMBLER_GALIOS | 170 SOR_DP_TPG_PATTERN_NONE; 171 value = (value << 8) | lane; 172 } 173 174 tegra_sor_writel(sor, value, SOR_DP_TPG); 175 176 pattern = DP_TRAINING_PATTERN_DISABLE; 177 178 err = tegra_dpaux_train(sor->dpaux, link, pattern); 179 if (err < 0) 180 return err; 181 182 return 0; 183 } 184 185 static void tegra_sor_super_update(struct tegra_sor *sor) 186 { 187 tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0); 188 tegra_sor_writel(sor, 1, SOR_SUPER_STATE_0); 189 tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0); 190 } 191 192 static void tegra_sor_update(struct tegra_sor *sor) 193 { 194 tegra_sor_writel(sor, 0, SOR_STATE_0); 195 tegra_sor_writel(sor, 1, SOR_STATE_0); 196 tegra_sor_writel(sor, 0, SOR_STATE_0); 197 } 198 199 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) 200 { 201 unsigned long value; 202 203 value = tegra_sor_readl(sor, SOR_PWM_DIV); 204 value &= ~SOR_PWM_DIV_MASK; 205 value |= 0x400; /* period */ 206 tegra_sor_writel(sor, value, SOR_PWM_DIV); 207 208 value = tegra_sor_readl(sor, SOR_PWM_CTL); 209 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; 210 value |= 0x400; /* duty cycle */ 211 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ 212 value |= SOR_PWM_CTL_TRIGGER; 213 tegra_sor_writel(sor, value, SOR_PWM_CTL); 214 215 timeout = jiffies + msecs_to_jiffies(timeout); 216 217 while (time_before(jiffies, timeout)) { 218 value = tegra_sor_readl(sor, SOR_PWM_CTL); 219 if ((value & SOR_PWM_CTL_TRIGGER) == 0) 220 return 0; 221 222 usleep_range(25, 100); 223 } 224 225 return -ETIMEDOUT; 226 } 227 228 static int tegra_sor_attach(struct tegra_sor *sor) 229 { 230 unsigned long value, timeout; 231 232 /* wake up in normal mode */ 233 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 234 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; 235 value |= SOR_SUPER_STATE_MODE_NORMAL; 236 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 237 tegra_sor_super_update(sor); 238 239 /* attach */ 240 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 241 value |= SOR_SUPER_STATE_ATTACHED; 242 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 243 tegra_sor_super_update(sor); 244 245 timeout = jiffies + msecs_to_jiffies(250); 246 247 while (time_before(jiffies, timeout)) { 248 value = tegra_sor_readl(sor, SOR_TEST); 249 if ((value & SOR_TEST_ATTACHED) != 0) 250 return 0; 251 252 usleep_range(25, 100); 253 } 254 255 return -ETIMEDOUT; 256 } 257 258 static int tegra_sor_wakeup(struct tegra_sor *sor) 259 { 260 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); 261 unsigned long value, timeout; 262 263 /* enable display controller outputs */ 264 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 265 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 266 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; 267 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 268 269 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); 270 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 271 272 timeout = jiffies + msecs_to_jiffies(250); 273 274 /* wait for head to wake up */ 275 while (time_before(jiffies, timeout)) { 276 value = tegra_sor_readl(sor, SOR_TEST); 277 value &= SOR_TEST_HEAD_MODE_MASK; 278 279 if (value == SOR_TEST_HEAD_MODE_AWAKE) 280 return 0; 281 282 usleep_range(25, 100); 283 } 284 285 return -ETIMEDOUT; 286 } 287 288 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) 289 { 290 unsigned long value; 291 292 value = tegra_sor_readl(sor, SOR_PWR); 293 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; 294 tegra_sor_writel(sor, value, SOR_PWR); 295 296 timeout = jiffies + msecs_to_jiffies(timeout); 297 298 while (time_before(jiffies, timeout)) { 299 value = tegra_sor_readl(sor, SOR_PWR); 300 if ((value & SOR_PWR_TRIGGER) == 0) 301 return 0; 302 303 usleep_range(25, 100); 304 } 305 306 return -ETIMEDOUT; 307 } 308 309 struct tegra_sor_params { 310 /* number of link clocks per line */ 311 unsigned int num_clocks; 312 /* ratio between input and output */ 313 u64 ratio; 314 /* precision factor */ 315 u64 precision; 316 317 unsigned int active_polarity; 318 unsigned int active_count; 319 unsigned int active_frac; 320 unsigned int tu_size; 321 unsigned int error; 322 }; 323 324 static int tegra_sor_compute_params(struct tegra_sor *sor, 325 struct tegra_sor_params *params, 326 unsigned int tu_size) 327 { 328 u64 active_sym, active_count, frac, approx; 329 u32 active_polarity, active_frac = 0; 330 const u64 f = params->precision; 331 s64 error; 332 333 active_sym = params->ratio * tu_size; 334 active_count = div_u64(active_sym, f) * f; 335 frac = active_sym - active_count; 336 337 /* fraction < 0.5 */ 338 if (frac >= (f / 2)) { 339 active_polarity = 1; 340 frac = f - frac; 341 } else { 342 active_polarity = 0; 343 } 344 345 if (frac != 0) { 346 frac = div_u64(f * f, frac); /* 1/fraction */ 347 if (frac <= (15 * f)) { 348 active_frac = div_u64(frac, f); 349 350 /* round up */ 351 if (active_polarity) 352 active_frac++; 353 } else { 354 active_frac = active_polarity ? 1 : 15; 355 } 356 } 357 358 if (active_frac == 1) 359 active_polarity = 0; 360 361 if (active_polarity == 1) { 362 if (active_frac) { 363 approx = active_count + (active_frac * (f - 1)) * f; 364 approx = div_u64(approx, active_frac * f); 365 } else { 366 approx = active_count + f; 367 } 368 } else { 369 if (active_frac) 370 approx = active_count + div_u64(f, active_frac); 371 else 372 approx = active_count; 373 } 374 375 error = div_s64(active_sym - approx, tu_size); 376 error *= params->num_clocks; 377 378 if (error <= 0 && abs64(error) < params->error) { 379 params->active_count = div_u64(active_count, f); 380 params->active_polarity = active_polarity; 381 params->active_frac = active_frac; 382 params->error = abs64(error); 383 params->tu_size = tu_size; 384 385 if (error == 0) 386 return true; 387 } 388 389 return false; 390 } 391 392 static int tegra_sor_calc_config(struct tegra_sor *sor, 393 struct drm_display_mode *mode, 394 struct tegra_sor_config *config, 395 struct drm_dp_link *link) 396 { 397 const u64 f = 100000, link_rate = link->rate * 1000; 398 const u64 pclk = mode->clock * 1000; 399 u64 input, output, watermark, num; 400 struct tegra_sor_params params; 401 u32 num_syms_per_line; 402 unsigned int i; 403 404 if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel) 405 return -EINVAL; 406 407 output = link_rate * 8 * link->num_lanes; 408 input = pclk * config->bits_per_pixel; 409 410 if (input >= output) 411 return -ERANGE; 412 413 memset(¶ms, 0, sizeof(params)); 414 params.ratio = div64_u64(input * f, output); 415 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); 416 params.precision = f; 417 params.error = 64 * f; 418 params.tu_size = 64; 419 420 for (i = params.tu_size; i >= 32; i--) 421 if (tegra_sor_compute_params(sor, ¶ms, i)) 422 break; 423 424 if (params.active_frac == 0) { 425 config->active_polarity = 0; 426 config->active_count = params.active_count; 427 428 if (!params.active_polarity) 429 config->active_count--; 430 431 config->tu_size = params.tu_size; 432 config->active_frac = 1; 433 } else { 434 config->active_polarity = params.active_polarity; 435 config->active_count = params.active_count; 436 config->active_frac = params.active_frac; 437 config->tu_size = params.tu_size; 438 } 439 440 dev_dbg(sor->dev, 441 "polarity: %d active count: %d tu size: %d active frac: %d\n", 442 config->active_polarity, config->active_count, 443 config->tu_size, config->active_frac); 444 445 watermark = params.ratio * config->tu_size * (f - params.ratio); 446 watermark = div_u64(watermark, f); 447 448 watermark = div_u64(watermark + params.error, f); 449 config->watermark = watermark + (config->bits_per_pixel / 8) + 2; 450 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * 451 (link->num_lanes * 8); 452 453 if (config->watermark > 30) { 454 config->watermark = 30; 455 dev_err(sor->dev, 456 "unable to compute TU size, forcing watermark to %u\n", 457 config->watermark); 458 } else if (config->watermark > num_syms_per_line) { 459 config->watermark = num_syms_per_line; 460 dev_err(sor->dev, "watermark too high, forcing to %u\n", 461 config->watermark); 462 } 463 464 /* compute the number of symbols per horizontal blanking interval */ 465 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; 466 config->hblank_symbols = div_u64(num, pclk); 467 468 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 469 config->hblank_symbols -= 3; 470 471 config->hblank_symbols -= 12 / link->num_lanes; 472 473 /* compute the number of symbols per vertical blanking interval */ 474 num = (mode->hdisplay - 25) * link_rate; 475 config->vblank_symbols = div_u64(num, pclk); 476 config->vblank_symbols -= 36 / link->num_lanes + 4; 477 478 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, 479 config->vblank_symbols); 480 481 return 0; 482 } 483 484 static int tegra_output_sor_enable(struct tegra_output *output) 485 { 486 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); 487 struct drm_display_mode *mode = &dc->base.mode; 488 unsigned int vbe, vse, hbe, hse, vbs, hbs, i; 489 struct tegra_sor *sor = to_sor(output); 490 struct tegra_sor_config config; 491 struct drm_dp_link link; 492 struct drm_dp_aux *aux; 493 unsigned long value; 494 int err = 0; 495 496 mutex_lock(&sor->lock); 497 498 if (sor->enabled) 499 goto unlock; 500 501 err = clk_prepare_enable(sor->clk); 502 if (err < 0) 503 goto unlock; 504 505 reset_control_deassert(sor->rst); 506 507 /* FIXME: properly convert to struct drm_dp_aux */ 508 aux = (struct drm_dp_aux *)sor->dpaux; 509 510 if (sor->dpaux) { 511 err = tegra_dpaux_enable(sor->dpaux); 512 if (err < 0) 513 dev_err(sor->dev, "failed to enable DP: %d\n", err); 514 515 err = drm_dp_link_probe(aux, &link); 516 if (err < 0) { 517 dev_err(sor->dev, "failed to probe eDP link: %d\n", 518 err); 519 return err; 520 } 521 } 522 523 err = clk_set_parent(sor->clk, sor->clk_safe); 524 if (err < 0) 525 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 526 527 memset(&config, 0, sizeof(config)); 528 config.bits_per_pixel = 24; /* XXX: don't hardcode? */ 529 530 err = tegra_sor_calc_config(sor, mode, &config, &link); 531 if (err < 0) 532 dev_err(sor->dev, "failed to compute link configuration: %d\n", 533 err); 534 535 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 536 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 537 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 538 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 539 540 value = tegra_sor_readl(sor, SOR_PLL_2); 541 value &= ~SOR_PLL_2_BANDGAP_POWERDOWN; 542 tegra_sor_writel(sor, value, SOR_PLL_2); 543 usleep_range(20, 100); 544 545 value = tegra_sor_readl(sor, SOR_PLL_3); 546 value |= SOR_PLL_3_PLL_VDD_MODE_V3_3; 547 tegra_sor_writel(sor, value, SOR_PLL_3); 548 549 value = SOR_PLL_0_ICHPMP(0xf) | SOR_PLL_0_VCOCAP_RST | 550 SOR_PLL_0_PLLREG_LEVEL_V45 | SOR_PLL_0_RESISTOR_EXT; 551 tegra_sor_writel(sor, value, SOR_PLL_0); 552 553 value = tegra_sor_readl(sor, SOR_PLL_2); 554 value |= SOR_PLL_2_SEQ_PLLCAPPD; 555 value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; 556 value |= SOR_PLL_2_LVDS_ENABLE; 557 tegra_sor_writel(sor, value, SOR_PLL_2); 558 559 value = SOR_PLL_1_TERM_COMPOUT | SOR_PLL_1_TMDS_TERM; 560 tegra_sor_writel(sor, value, SOR_PLL_1); 561 562 while (true) { 563 value = tegra_sor_readl(sor, SOR_PLL_2); 564 if ((value & SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE) == 0) 565 break; 566 567 usleep_range(250, 1000); 568 } 569 570 value = tegra_sor_readl(sor, SOR_PLL_2); 571 value &= ~SOR_PLL_2_POWERDOWN_OVERRIDE; 572 value &= ~SOR_PLL_2_PORT_POWERDOWN; 573 tegra_sor_writel(sor, value, SOR_PLL_2); 574 575 /* 576 * power up 577 */ 578 579 /* set safe link bandwidth (1.62 Gbps) */ 580 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 581 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 582 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; 583 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 584 585 /* step 1 */ 586 value = tegra_sor_readl(sor, SOR_PLL_2); 587 value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL_2_PORT_POWERDOWN | 588 SOR_PLL_2_BANDGAP_POWERDOWN; 589 tegra_sor_writel(sor, value, SOR_PLL_2); 590 591 value = tegra_sor_readl(sor, SOR_PLL_0); 592 value |= SOR_PLL_0_VCOPD | SOR_PLL_0_POWER_OFF; 593 tegra_sor_writel(sor, value, SOR_PLL_0); 594 595 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 596 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 597 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 598 599 /* step 2 */ 600 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); 601 if (err < 0) { 602 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err); 603 goto unlock; 604 } 605 606 usleep_range(5, 100); 607 608 /* step 3 */ 609 value = tegra_sor_readl(sor, SOR_PLL_2); 610 value &= ~SOR_PLL_2_BANDGAP_POWERDOWN; 611 tegra_sor_writel(sor, value, SOR_PLL_2); 612 613 usleep_range(20, 100); 614 615 /* step 4 */ 616 value = tegra_sor_readl(sor, SOR_PLL_0); 617 value &= ~SOR_PLL_0_POWER_OFF; 618 value &= ~SOR_PLL_0_VCOPD; 619 tegra_sor_writel(sor, value, SOR_PLL_0); 620 621 value = tegra_sor_readl(sor, SOR_PLL_2); 622 value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; 623 tegra_sor_writel(sor, value, SOR_PLL_2); 624 625 usleep_range(200, 1000); 626 627 /* step 5 */ 628 value = tegra_sor_readl(sor, SOR_PLL_2); 629 value &= ~SOR_PLL_2_PORT_POWERDOWN; 630 tegra_sor_writel(sor, value, SOR_PLL_2); 631 632 /* switch to DP clock */ 633 err = clk_set_parent(sor->clk, sor->clk_dp); 634 if (err < 0) 635 dev_err(sor->dev, "failed to set DP parent clock: %d\n", err); 636 637 /* power DP lanes */ 638 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 639 640 if (link.num_lanes <= 2) 641 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); 642 else 643 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2; 644 645 if (link.num_lanes <= 1) 646 value &= ~SOR_DP_PADCTL_PD_TXD_1; 647 else 648 value |= SOR_DP_PADCTL_PD_TXD_1; 649 650 if (link.num_lanes == 0) 651 value &= ~SOR_DP_PADCTL_PD_TXD_0; 652 else 653 value |= SOR_DP_PADCTL_PD_TXD_0; 654 655 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 656 657 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); 658 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 659 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes); 660 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); 661 662 /* start lane sequencer */ 663 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 664 SOR_LANE_SEQ_CTL_POWER_STATE_UP; 665 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 666 667 while (true) { 668 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 669 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 670 break; 671 672 usleep_range(250, 1000); 673 } 674 675 /* set link bandwidth */ 676 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 677 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 678 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; 679 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 680 681 /* set linkctl */ 682 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); 683 value |= SOR_DP_LINKCTL_ENABLE; 684 685 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; 686 value |= SOR_DP_LINKCTL_TU_SIZE(config.tu_size); 687 688 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 689 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); 690 691 for (i = 0, value = 0; i < 4; i++) { 692 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 693 SOR_DP_TPG_SCRAMBLER_GALIOS | 694 SOR_DP_TPG_PATTERN_NONE; 695 value = (value << 8) | lane; 696 } 697 698 tegra_sor_writel(sor, value, SOR_DP_TPG); 699 700 value = tegra_sor_readl(sor, SOR_DP_CONFIG_0); 701 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; 702 value |= SOR_DP_CONFIG_WATERMARK(config.watermark); 703 704 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; 705 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config.active_count); 706 707 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; 708 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config.active_frac); 709 710 if (config.active_polarity) 711 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 712 else 713 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 714 715 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; 716 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; 717 tegra_sor_writel(sor, value, SOR_DP_CONFIG_0); 718 719 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); 720 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; 721 value |= config.hblank_symbols & 0xffff; 722 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); 723 724 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); 725 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; 726 value |= config.vblank_symbols & 0xffff; 727 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); 728 729 /* enable pad calibration logic */ 730 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 731 value |= SOR_DP_PADCTL_PAD_CAL_PD; 732 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 733 734 if (sor->dpaux) { 735 u8 rate, lanes; 736 737 err = drm_dp_link_probe(aux, &link); 738 if (err < 0) { 739 dev_err(sor->dev, "failed to probe eDP link: %d\n", 740 err); 741 goto unlock; 742 } 743 744 err = drm_dp_link_power_up(aux, &link); 745 if (err < 0) { 746 dev_err(sor->dev, "failed to power up eDP link: %d\n", 747 err); 748 goto unlock; 749 } 750 751 err = drm_dp_link_configure(aux, &link); 752 if (err < 0) { 753 dev_err(sor->dev, "failed to configure eDP link: %d\n", 754 err); 755 goto unlock; 756 } 757 758 rate = drm_dp_link_rate_to_bw_code(link.rate); 759 lanes = link.num_lanes; 760 761 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 762 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 763 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); 764 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 765 766 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); 767 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 768 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); 769 770 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 771 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 772 773 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); 774 775 /* disable training pattern generator */ 776 777 for (i = 0; i < link.num_lanes; i++) { 778 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 779 SOR_DP_TPG_SCRAMBLER_GALIOS | 780 SOR_DP_TPG_PATTERN_NONE; 781 value = (value << 8) | lane; 782 } 783 784 tegra_sor_writel(sor, value, SOR_DP_TPG); 785 786 err = tegra_sor_dp_train_fast(sor, &link); 787 if (err < 0) { 788 dev_err(sor->dev, "DP fast link training failed: %d\n", 789 err); 790 goto unlock; 791 } 792 793 dev_dbg(sor->dev, "fast link training succeeded\n"); 794 } 795 796 err = tegra_sor_power_up(sor, 250); 797 if (err < 0) { 798 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 799 goto unlock; 800 } 801 802 /* start display controller in continuous mode */ 803 value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS); 804 value |= WRITE_MUX; 805 tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS); 806 807 tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS); 808 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND); 809 810 value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS); 811 value &= ~WRITE_MUX; 812 tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS); 813 814 /* 815 * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete 816 * raster, associate with display controller) 817 */ 818 value = SOR_STATE_ASY_VSYNCPOL | 819 SOR_STATE_ASY_HSYNCPOL | 820 SOR_STATE_ASY_PROTOCOL_DP_A | 821 SOR_STATE_ASY_CRC_MODE_COMPLETE | 822 SOR_STATE_ASY_OWNER(dc->pipe + 1); 823 824 switch (config.bits_per_pixel) { 825 case 24: 826 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 827 break; 828 829 case 18: 830 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; 831 break; 832 833 default: 834 BUG(); 835 break; 836 } 837 838 tegra_sor_writel(sor, value, SOR_STATE_1); 839 840 /* 841 * TODO: The video timing programming below doesn't seem to match the 842 * register definitions. 843 */ 844 845 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); 846 tegra_sor_writel(sor, value, SOR_HEAD_STATE_1(0)); 847 848 vse = mode->vsync_end - mode->vsync_start - 1; 849 hse = mode->hsync_end - mode->hsync_start - 1; 850 851 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); 852 tegra_sor_writel(sor, value, SOR_HEAD_STATE_2(0)); 853 854 vbe = vse + (mode->vsync_start - mode->vdisplay); 855 hbe = hse + (mode->hsync_start - mode->hdisplay); 856 857 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); 858 tegra_sor_writel(sor, value, SOR_HEAD_STATE_3(0)); 859 860 vbs = vbe + mode->vdisplay; 861 hbs = hbe + mode->hdisplay; 862 863 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); 864 tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0)); 865 866 /* CSTM (LVDS, link A/B, upper) */ 867 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | 868 SOR_CSTM_UPPER; 869 tegra_sor_writel(sor, value, SOR_CSTM); 870 871 /* PWM setup */ 872 err = tegra_sor_setup_pwm(sor, 250); 873 if (err < 0) { 874 dev_err(sor->dev, "failed to setup PWM: %d\n", err); 875 goto unlock; 876 } 877 878 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 879 value |= SOR_ENABLE; 880 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 881 882 tegra_sor_update(sor); 883 884 err = tegra_sor_attach(sor); 885 if (err < 0) { 886 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 887 goto unlock; 888 } 889 890 err = tegra_sor_wakeup(sor); 891 if (err < 0) { 892 dev_err(sor->dev, "failed to enable DC: %d\n", err); 893 goto unlock; 894 } 895 896 sor->enabled = true; 897 898 unlock: 899 mutex_unlock(&sor->lock); 900 return err; 901 } 902 903 static int tegra_sor_detach(struct tegra_sor *sor) 904 { 905 unsigned long value, timeout; 906 907 /* switch to safe mode */ 908 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 909 value &= ~SOR_SUPER_STATE_MODE_NORMAL; 910 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 911 tegra_sor_super_update(sor); 912 913 timeout = jiffies + msecs_to_jiffies(250); 914 915 while (time_before(jiffies, timeout)) { 916 value = tegra_sor_readl(sor, SOR_PWR); 917 if (value & SOR_PWR_MODE_SAFE) 918 break; 919 } 920 921 if ((value & SOR_PWR_MODE_SAFE) == 0) 922 return -ETIMEDOUT; 923 924 /* go to sleep */ 925 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 926 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; 927 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 928 tegra_sor_super_update(sor); 929 930 /* detach */ 931 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1); 932 value &= ~SOR_SUPER_STATE_ATTACHED; 933 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1); 934 tegra_sor_super_update(sor); 935 936 timeout = jiffies + msecs_to_jiffies(250); 937 938 while (time_before(jiffies, timeout)) { 939 value = tegra_sor_readl(sor, SOR_TEST); 940 if ((value & SOR_TEST_ATTACHED) == 0) 941 break; 942 943 usleep_range(25, 100); 944 } 945 946 if ((value & SOR_TEST_ATTACHED) != 0) 947 return -ETIMEDOUT; 948 949 return 0; 950 } 951 952 static int tegra_sor_power_down(struct tegra_sor *sor) 953 { 954 unsigned long value, timeout; 955 int err; 956 957 value = tegra_sor_readl(sor, SOR_PWR); 958 value &= ~SOR_PWR_NORMAL_STATE_PU; 959 value |= SOR_PWR_TRIGGER; 960 tegra_sor_writel(sor, value, SOR_PWR); 961 962 timeout = jiffies + msecs_to_jiffies(250); 963 964 while (time_before(jiffies, timeout)) { 965 value = tegra_sor_readl(sor, SOR_PWR); 966 if ((value & SOR_PWR_TRIGGER) == 0) 967 return 0; 968 969 usleep_range(25, 100); 970 } 971 972 if ((value & SOR_PWR_TRIGGER) != 0) 973 return -ETIMEDOUT; 974 975 err = clk_set_parent(sor->clk, sor->clk_safe); 976 if (err < 0) 977 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 978 979 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 980 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 981 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); 982 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 983 984 /* stop lane sequencer */ 985 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | 986 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; 987 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 988 989 timeout = jiffies + msecs_to_jiffies(250); 990 991 while (time_before(jiffies, timeout)) { 992 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 993 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 994 break; 995 996 usleep_range(25, 100); 997 } 998 999 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 1000 return -ETIMEDOUT; 1001 1002 value = tegra_sor_readl(sor, SOR_PLL_2); 1003 value |= SOR_PLL_2_PORT_POWERDOWN; 1004 tegra_sor_writel(sor, value, SOR_PLL_2); 1005 1006 usleep_range(20, 100); 1007 1008 value = tegra_sor_readl(sor, SOR_PLL_0); 1009 value |= SOR_PLL_0_POWER_OFF; 1010 value |= SOR_PLL_0_VCOPD; 1011 tegra_sor_writel(sor, value, SOR_PLL_0); 1012 1013 value = tegra_sor_readl(sor, SOR_PLL_2); 1014 value |= SOR_PLL_2_SEQ_PLLCAPPD; 1015 value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE; 1016 tegra_sor_writel(sor, value, SOR_PLL_2); 1017 1018 usleep_range(20, 100); 1019 1020 return 0; 1021 } 1022 1023 static int tegra_output_sor_disable(struct tegra_output *output) 1024 { 1025 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); 1026 struct tegra_sor *sor = to_sor(output); 1027 unsigned long value; 1028 int err = 0; 1029 1030 mutex_lock(&sor->lock); 1031 1032 if (!sor->enabled) 1033 goto unlock; 1034 1035 err = tegra_sor_detach(sor); 1036 if (err < 0) { 1037 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 1038 goto unlock; 1039 } 1040 1041 tegra_sor_writel(sor, 0, SOR_STATE_1); 1042 tegra_sor_update(sor); 1043 1044 /* 1045 * The following accesses registers of the display controller, so make 1046 * sure it's only executed when the output is attached to one. 1047 */ 1048 if (dc) { 1049 /* 1050 * XXX: We can't do this here because it causes the SOR to go 1051 * into an erroneous state and the output will look scrambled 1052 * the next time it is enabled. Presumably this is because we 1053 * should be doing this only on the next VBLANK. A possible 1054 * solution would be to queue a "power-off" event to trigger 1055 * this code to be run during the next VBLANK. 1056 */ 1057 /* 1058 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 1059 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 1060 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); 1061 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 1062 */ 1063 1064 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 1065 value &= ~DISP_CTRL_MODE_MASK; 1066 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 1067 1068 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1069 value &= ~SOR_ENABLE; 1070 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1071 1072 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); 1073 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 1074 } 1075 1076 err = tegra_sor_power_down(sor); 1077 if (err < 0) { 1078 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 1079 goto unlock; 1080 } 1081 1082 if (sor->dpaux) { 1083 err = tegra_dpaux_disable(sor->dpaux); 1084 if (err < 0) { 1085 dev_err(sor->dev, "failed to disable DP: %d\n", err); 1086 goto unlock; 1087 } 1088 } 1089 1090 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS); 1091 if (err < 0) { 1092 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err); 1093 goto unlock; 1094 } 1095 1096 reset_control_assert(sor->rst); 1097 clk_disable_unprepare(sor->clk); 1098 1099 sor->enabled = false; 1100 1101 unlock: 1102 mutex_unlock(&sor->lock); 1103 return err; 1104 } 1105 1106 static int tegra_output_sor_setup_clock(struct tegra_output *output, 1107 struct clk *clk, unsigned long pclk, 1108 unsigned int *div) 1109 { 1110 struct tegra_sor *sor = to_sor(output); 1111 int err; 1112 1113 err = clk_set_parent(clk, sor->clk_parent); 1114 if (err < 0) { 1115 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 1116 return err; 1117 } 1118 1119 err = clk_set_rate(sor->clk_parent, pclk); 1120 if (err < 0) { 1121 dev_err(sor->dev, "failed to set clock rate to %lu Hz\n", pclk); 1122 return err; 1123 } 1124 1125 *div = 0; 1126 1127 return 0; 1128 } 1129 1130 static int tegra_output_sor_check_mode(struct tegra_output *output, 1131 struct drm_display_mode *mode, 1132 enum drm_mode_status *status) 1133 { 1134 /* 1135 * FIXME: For now, always assume that the mode is okay. 1136 */ 1137 1138 *status = MODE_OK; 1139 1140 return 0; 1141 } 1142 1143 static enum drm_connector_status 1144 tegra_output_sor_detect(struct tegra_output *output) 1145 { 1146 struct tegra_sor *sor = to_sor(output); 1147 1148 if (sor->dpaux) 1149 return tegra_dpaux_detect(sor->dpaux); 1150 1151 return connector_status_unknown; 1152 } 1153 1154 static const struct tegra_output_ops sor_ops = { 1155 .enable = tegra_output_sor_enable, 1156 .disable = tegra_output_sor_disable, 1157 .setup_clock = tegra_output_sor_setup_clock, 1158 .check_mode = tegra_output_sor_check_mode, 1159 .detect = tegra_output_sor_detect, 1160 }; 1161 1162 static int tegra_sor_crc_open(struct inode *inode, struct file *file) 1163 { 1164 file->private_data = inode->i_private; 1165 1166 return 0; 1167 } 1168 1169 static int tegra_sor_crc_release(struct inode *inode, struct file *file) 1170 { 1171 return 0; 1172 } 1173 1174 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) 1175 { 1176 u32 value; 1177 1178 timeout = jiffies + msecs_to_jiffies(timeout); 1179 1180 while (time_before(jiffies, timeout)) { 1181 value = tegra_sor_readl(sor, SOR_CRC_A); 1182 if (value & SOR_CRC_A_VALID) 1183 return 0; 1184 1185 usleep_range(100, 200); 1186 } 1187 1188 return -ETIMEDOUT; 1189 } 1190 1191 static ssize_t tegra_sor_crc_read(struct file *file, char __user *buffer, 1192 size_t size, loff_t *ppos) 1193 { 1194 struct tegra_sor *sor = file->private_data; 1195 ssize_t num, err; 1196 char buf[10]; 1197 u32 value; 1198 1199 mutex_lock(&sor->lock); 1200 1201 if (!sor->enabled) { 1202 err = -EAGAIN; 1203 goto unlock; 1204 } 1205 1206 value = tegra_sor_readl(sor, SOR_STATE_1); 1207 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 1208 tegra_sor_writel(sor, value, SOR_STATE_1); 1209 1210 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); 1211 value |= SOR_CRC_CNTRL_ENABLE; 1212 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); 1213 1214 value = tegra_sor_readl(sor, SOR_TEST); 1215 value &= ~SOR_TEST_CRC_POST_SERIALIZE; 1216 tegra_sor_writel(sor, value, SOR_TEST); 1217 1218 err = tegra_sor_crc_wait(sor, 100); 1219 if (err < 0) 1220 goto unlock; 1221 1222 tegra_sor_writel(sor, SOR_CRC_A_RESET, SOR_CRC_A); 1223 value = tegra_sor_readl(sor, SOR_CRC_B); 1224 1225 num = scnprintf(buf, sizeof(buf), "%08x\n", value); 1226 1227 err = simple_read_from_buffer(buffer, size, ppos, buf, num); 1228 1229 unlock: 1230 mutex_unlock(&sor->lock); 1231 return err; 1232 } 1233 1234 static const struct file_operations tegra_sor_crc_fops = { 1235 .owner = THIS_MODULE, 1236 .open = tegra_sor_crc_open, 1237 .read = tegra_sor_crc_read, 1238 .release = tegra_sor_crc_release, 1239 }; 1240 1241 static int tegra_sor_debugfs_init(struct tegra_sor *sor, 1242 struct drm_minor *minor) 1243 { 1244 struct dentry *entry; 1245 int err = 0; 1246 1247 sor->debugfs = debugfs_create_dir("sor", minor->debugfs_root); 1248 if (!sor->debugfs) 1249 return -ENOMEM; 1250 1251 entry = debugfs_create_file("crc", 0644, sor->debugfs, sor, 1252 &tegra_sor_crc_fops); 1253 if (!entry) { 1254 dev_err(sor->dev, 1255 "cannot create /sys/kernel/debug/dri/%s/sor/crc\n", 1256 minor->debugfs_root->d_name.name); 1257 err = -ENOMEM; 1258 goto remove; 1259 } 1260 1261 return err; 1262 1263 remove: 1264 debugfs_remove(sor->debugfs); 1265 sor->debugfs = NULL; 1266 return err; 1267 } 1268 1269 static int tegra_sor_debugfs_exit(struct tegra_sor *sor) 1270 { 1271 debugfs_remove_recursive(sor->debugfs); 1272 sor->debugfs = NULL; 1273 1274 return 0; 1275 } 1276 1277 static int tegra_sor_init(struct host1x_client *client) 1278 { 1279 struct drm_device *drm = dev_get_drvdata(client->parent); 1280 struct tegra_sor *sor = host1x_client_to_sor(client); 1281 int err; 1282 1283 if (!sor->dpaux) 1284 return -ENODEV; 1285 1286 sor->output.type = TEGRA_OUTPUT_EDP; 1287 1288 sor->output.dev = sor->dev; 1289 sor->output.ops = &sor_ops; 1290 1291 err = tegra_output_init(drm, &sor->output); 1292 if (err < 0) { 1293 dev_err(sor->dev, "output setup failed: %d\n", err); 1294 return err; 1295 } 1296 1297 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1298 err = tegra_sor_debugfs_init(sor, drm->primary); 1299 if (err < 0) 1300 dev_err(sor->dev, "debugfs setup failed: %d\n", err); 1301 } 1302 1303 if (sor->dpaux) { 1304 err = tegra_dpaux_attach(sor->dpaux, &sor->output); 1305 if (err < 0) { 1306 dev_err(sor->dev, "failed to attach DP: %d\n", err); 1307 return err; 1308 } 1309 } 1310 1311 return 0; 1312 } 1313 1314 static int tegra_sor_exit(struct host1x_client *client) 1315 { 1316 struct tegra_sor *sor = host1x_client_to_sor(client); 1317 int err; 1318 1319 err = tegra_output_disable(&sor->output); 1320 if (err < 0) { 1321 dev_err(sor->dev, "output failed to disable: %d\n", err); 1322 return err; 1323 } 1324 1325 if (sor->dpaux) { 1326 err = tegra_dpaux_detach(sor->dpaux); 1327 if (err < 0) { 1328 dev_err(sor->dev, "failed to detach DP: %d\n", err); 1329 return err; 1330 } 1331 } 1332 1333 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1334 err = tegra_sor_debugfs_exit(sor); 1335 if (err < 0) 1336 dev_err(sor->dev, "debugfs cleanup failed: %d\n", err); 1337 } 1338 1339 err = tegra_output_exit(&sor->output); 1340 if (err < 0) { 1341 dev_err(sor->dev, "output cleanup failed: %d\n", err); 1342 return err; 1343 } 1344 1345 return 0; 1346 } 1347 1348 static const struct host1x_client_ops sor_client_ops = { 1349 .init = tegra_sor_init, 1350 .exit = tegra_sor_exit, 1351 }; 1352 1353 static int tegra_sor_probe(struct platform_device *pdev) 1354 { 1355 struct device_node *np; 1356 struct tegra_sor *sor; 1357 struct resource *regs; 1358 int err; 1359 1360 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); 1361 if (!sor) 1362 return -ENOMEM; 1363 1364 sor->output.dev = sor->dev = &pdev->dev; 1365 1366 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); 1367 if (np) { 1368 sor->dpaux = tegra_dpaux_find_by_of_node(np); 1369 of_node_put(np); 1370 1371 if (!sor->dpaux) 1372 return -EPROBE_DEFER; 1373 } 1374 1375 err = tegra_output_probe(&sor->output); 1376 if (err < 0) 1377 return err; 1378 1379 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1380 sor->regs = devm_ioremap_resource(&pdev->dev, regs); 1381 if (IS_ERR(sor->regs)) 1382 return PTR_ERR(sor->regs); 1383 1384 sor->rst = devm_reset_control_get(&pdev->dev, "sor"); 1385 if (IS_ERR(sor->rst)) 1386 return PTR_ERR(sor->rst); 1387 1388 sor->clk = devm_clk_get(&pdev->dev, NULL); 1389 if (IS_ERR(sor->clk)) 1390 return PTR_ERR(sor->clk); 1391 1392 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); 1393 if (IS_ERR(sor->clk_parent)) 1394 return PTR_ERR(sor->clk_parent); 1395 1396 err = clk_prepare_enable(sor->clk_parent); 1397 if (err < 0) 1398 return err; 1399 1400 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); 1401 if (IS_ERR(sor->clk_safe)) 1402 return PTR_ERR(sor->clk_safe); 1403 1404 err = clk_prepare_enable(sor->clk_safe); 1405 if (err < 0) 1406 return err; 1407 1408 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); 1409 if (IS_ERR(sor->clk_dp)) 1410 return PTR_ERR(sor->clk_dp); 1411 1412 err = clk_prepare_enable(sor->clk_dp); 1413 if (err < 0) 1414 return err; 1415 1416 INIT_LIST_HEAD(&sor->client.list); 1417 sor->client.ops = &sor_client_ops; 1418 sor->client.dev = &pdev->dev; 1419 1420 mutex_init(&sor->lock); 1421 1422 err = host1x_client_register(&sor->client); 1423 if (err < 0) { 1424 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 1425 err); 1426 return err; 1427 } 1428 1429 platform_set_drvdata(pdev, sor); 1430 1431 return 0; 1432 } 1433 1434 static int tegra_sor_remove(struct platform_device *pdev) 1435 { 1436 struct tegra_sor *sor = platform_get_drvdata(pdev); 1437 int err; 1438 1439 err = host1x_client_unregister(&sor->client); 1440 if (err < 0) { 1441 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 1442 err); 1443 return err; 1444 } 1445 1446 clk_disable_unprepare(sor->clk_parent); 1447 clk_disable_unprepare(sor->clk_safe); 1448 clk_disable_unprepare(sor->clk_dp); 1449 clk_disable_unprepare(sor->clk); 1450 1451 return 0; 1452 } 1453 1454 static const struct of_device_id tegra_sor_of_match[] = { 1455 { .compatible = "nvidia,tegra124-sor", }, 1456 { }, 1457 }; 1458 1459 struct platform_driver tegra_sor_driver = { 1460 .driver = { 1461 .name = "tegra-sor", 1462 .of_match_table = tegra_sor_of_match, 1463 }, 1464 .probe = tegra_sor_probe, 1465 .remove = tegra_sor_remove, 1466 }; 1467