1 /* 2 * Copyright (C) 2013 NVIDIA Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/debugfs.h> 12 #include <linux/gpio.h> 13 #include <linux/io.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/reset.h> 19 20 #include <soc/tegra/pmc.h> 21 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_dp_helper.h> 24 #include <drm/drm_panel.h> 25 #include <drm/drm_scdc_helper.h> 26 27 #include "dc.h" 28 #include "drm.h" 29 #include "sor.h" 30 #include "trace.h" 31 32 /* 33 * XXX Remove this after the commit adding it to soc/tegra/pmc.h has been 34 * merged. Having this around after the commit is merged should be safe since 35 * the preprocessor will effectively replace all occurrences and therefore no 36 * duplicate will be defined. 37 */ 38 #define TEGRA_IO_PAD_HDMI_DP0 26 39 40 #define SOR_REKEY 0x38 41 42 struct tegra_sor_hdmi_settings { 43 unsigned long frequency; 44 45 u8 vcocap; 46 u8 filter; 47 u8 ichpmp; 48 u8 loadadj; 49 u8 tmds_termadj; 50 u8 tx_pu_value; 51 u8 bg_temp_coef; 52 u8 bg_vref_level; 53 u8 avdd10_level; 54 u8 avdd14_level; 55 u8 sparepll; 56 57 u8 drive_current[4]; 58 u8 preemphasis[4]; 59 }; 60 61 #if 1 62 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 63 { 64 .frequency = 54000000, 65 .vcocap = 0x0, 66 .filter = 0x0, 67 .ichpmp = 0x1, 68 .loadadj = 0x3, 69 .tmds_termadj = 0x9, 70 .tx_pu_value = 0x10, 71 .bg_temp_coef = 0x3, 72 .bg_vref_level = 0x8, 73 .avdd10_level = 0x4, 74 .avdd14_level = 0x4, 75 .sparepll = 0x0, 76 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 77 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 78 }, { 79 .frequency = 75000000, 80 .vcocap = 0x3, 81 .filter = 0x0, 82 .ichpmp = 0x1, 83 .loadadj = 0x3, 84 .tmds_termadj = 0x9, 85 .tx_pu_value = 0x40, 86 .bg_temp_coef = 0x3, 87 .bg_vref_level = 0x8, 88 .avdd10_level = 0x4, 89 .avdd14_level = 0x4, 90 .sparepll = 0x0, 91 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 92 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 93 }, { 94 .frequency = 150000000, 95 .vcocap = 0x3, 96 .filter = 0x0, 97 .ichpmp = 0x1, 98 .loadadj = 0x3, 99 .tmds_termadj = 0x9, 100 .tx_pu_value = 0x66, 101 .bg_temp_coef = 0x3, 102 .bg_vref_level = 0x8, 103 .avdd10_level = 0x4, 104 .avdd14_level = 0x4, 105 .sparepll = 0x0, 106 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 107 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 108 }, { 109 .frequency = 300000000, 110 .vcocap = 0x3, 111 .filter = 0x0, 112 .ichpmp = 0x1, 113 .loadadj = 0x3, 114 .tmds_termadj = 0x9, 115 .tx_pu_value = 0x66, 116 .bg_temp_coef = 0x3, 117 .bg_vref_level = 0xa, 118 .avdd10_level = 0x4, 119 .avdd14_level = 0x4, 120 .sparepll = 0x0, 121 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 122 .preemphasis = { 0x00, 0x17, 0x17, 0x17 }, 123 }, { 124 .frequency = 600000000, 125 .vcocap = 0x3, 126 .filter = 0x0, 127 .ichpmp = 0x1, 128 .loadadj = 0x3, 129 .tmds_termadj = 0x9, 130 .tx_pu_value = 0x66, 131 .bg_temp_coef = 0x3, 132 .bg_vref_level = 0x8, 133 .avdd10_level = 0x4, 134 .avdd14_level = 0x4, 135 .sparepll = 0x0, 136 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 137 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 138 }, 139 }; 140 #else 141 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 142 { 143 .frequency = 75000000, 144 .vcocap = 0x3, 145 .filter = 0x0, 146 .ichpmp = 0x1, 147 .loadadj = 0x3, 148 .tmds_termadj = 0x9, 149 .tx_pu_value = 0x40, 150 .bg_temp_coef = 0x3, 151 .bg_vref_level = 0x8, 152 .avdd10_level = 0x4, 153 .avdd14_level = 0x4, 154 .sparepll = 0x0, 155 .drive_current = { 0x29, 0x29, 0x29, 0x29 }, 156 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 157 }, { 158 .frequency = 150000000, 159 .vcocap = 0x3, 160 .filter = 0x0, 161 .ichpmp = 0x1, 162 .loadadj = 0x3, 163 .tmds_termadj = 0x9, 164 .tx_pu_value = 0x66, 165 .bg_temp_coef = 0x3, 166 .bg_vref_level = 0x8, 167 .avdd10_level = 0x4, 168 .avdd14_level = 0x4, 169 .sparepll = 0x0, 170 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 171 .preemphasis = { 0x01, 0x02, 0x02, 0x02 }, 172 }, { 173 .frequency = 300000000, 174 .vcocap = 0x3, 175 .filter = 0x0, 176 .ichpmp = 0x6, 177 .loadadj = 0x3, 178 .tmds_termadj = 0x9, 179 .tx_pu_value = 0x66, 180 .bg_temp_coef = 0x3, 181 .bg_vref_level = 0xf, 182 .avdd10_level = 0x4, 183 .avdd14_level = 0x4, 184 .sparepll = 0x0, 185 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 186 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e }, 187 }, { 188 .frequency = 600000000, 189 .vcocap = 0x3, 190 .filter = 0x0, 191 .ichpmp = 0xa, 192 .loadadj = 0x3, 193 .tmds_termadj = 0xb, 194 .tx_pu_value = 0x66, 195 .bg_temp_coef = 0x3, 196 .bg_vref_level = 0xe, 197 .avdd10_level = 0x4, 198 .avdd14_level = 0x4, 199 .sparepll = 0x0, 200 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e }, 201 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f }, 202 }, 203 }; 204 #endif 205 206 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = { 207 { 208 .frequency = 54000000, 209 .vcocap = 0, 210 .filter = 5, 211 .ichpmp = 5, 212 .loadadj = 3, 213 .tmds_termadj = 0xf, 214 .tx_pu_value = 0, 215 .bg_temp_coef = 3, 216 .bg_vref_level = 8, 217 .avdd10_level = 4, 218 .avdd14_level = 4, 219 .sparepll = 0x54, 220 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 221 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 222 }, { 223 .frequency = 75000000, 224 .vcocap = 1, 225 .filter = 5, 226 .ichpmp = 5, 227 .loadadj = 3, 228 .tmds_termadj = 0xf, 229 .tx_pu_value = 0, 230 .bg_temp_coef = 3, 231 .bg_vref_level = 8, 232 .avdd10_level = 4, 233 .avdd14_level = 4, 234 .sparepll = 0x44, 235 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 236 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 237 }, { 238 .frequency = 150000000, 239 .vcocap = 3, 240 .filter = 5, 241 .ichpmp = 5, 242 .loadadj = 3, 243 .tmds_termadj = 15, 244 .tx_pu_value = 0x66 /* 0 */, 245 .bg_temp_coef = 3, 246 .bg_vref_level = 8, 247 .avdd10_level = 4, 248 .avdd14_level = 4, 249 .sparepll = 0x00, /* 0x34 */ 250 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 }, 251 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 252 }, { 253 .frequency = 300000000, 254 .vcocap = 3, 255 .filter = 5, 256 .ichpmp = 5, 257 .loadadj = 3, 258 .tmds_termadj = 15, 259 .tx_pu_value = 64, 260 .bg_temp_coef = 3, 261 .bg_vref_level = 8, 262 .avdd10_level = 4, 263 .avdd14_level = 4, 264 .sparepll = 0x34, 265 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 266 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 267 }, { 268 .frequency = 600000000, 269 .vcocap = 3, 270 .filter = 5, 271 .ichpmp = 5, 272 .loadadj = 3, 273 .tmds_termadj = 12, 274 .tx_pu_value = 96, 275 .bg_temp_coef = 3, 276 .bg_vref_level = 8, 277 .avdd10_level = 4, 278 .avdd14_level = 4, 279 .sparepll = 0x34, 280 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 281 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 282 } 283 }; 284 285 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = { 286 { 287 .frequency = 54000000, 288 .vcocap = 0, 289 .filter = 5, 290 .ichpmp = 5, 291 .loadadj = 3, 292 .tmds_termadj = 0xf, 293 .tx_pu_value = 0, 294 .bg_temp_coef = 3, 295 .bg_vref_level = 8, 296 .avdd10_level = 4, 297 .avdd14_level = 4, 298 .sparepll = 0x54, 299 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 300 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 301 }, { 302 .frequency = 75000000, 303 .vcocap = 1, 304 .filter = 5, 305 .ichpmp = 5, 306 .loadadj = 3, 307 .tmds_termadj = 0xf, 308 .tx_pu_value = 0, 309 .bg_temp_coef = 3, 310 .bg_vref_level = 8, 311 .avdd10_level = 4, 312 .avdd14_level = 4, 313 .sparepll = 0x44, 314 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 315 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 316 }, { 317 .frequency = 150000000, 318 .vcocap = 3, 319 .filter = 5, 320 .ichpmp = 5, 321 .loadadj = 3, 322 .tmds_termadj = 15, 323 .tx_pu_value = 0x66 /* 0 */, 324 .bg_temp_coef = 3, 325 .bg_vref_level = 8, 326 .avdd10_level = 4, 327 .avdd14_level = 4, 328 .sparepll = 0x00, /* 0x34 */ 329 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 }, 330 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 331 }, { 332 .frequency = 300000000, 333 .vcocap = 3, 334 .filter = 5, 335 .ichpmp = 5, 336 .loadadj = 3, 337 .tmds_termadj = 15, 338 .tx_pu_value = 64, 339 .bg_temp_coef = 3, 340 .bg_vref_level = 8, 341 .avdd10_level = 4, 342 .avdd14_level = 4, 343 .sparepll = 0x34, 344 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 345 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 346 }, { 347 .frequency = 600000000, 348 .vcocap = 3, 349 .filter = 5, 350 .ichpmp = 5, 351 .loadadj = 3, 352 .tmds_termadj = 12, 353 .tx_pu_value = 96, 354 .bg_temp_coef = 3, 355 .bg_vref_level = 8, 356 .avdd10_level = 4, 357 .avdd14_level = 4, 358 .sparepll = 0x34, 359 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 360 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 361 } 362 }; 363 364 struct tegra_sor_regs { 365 unsigned int head_state0; 366 unsigned int head_state1; 367 unsigned int head_state2; 368 unsigned int head_state3; 369 unsigned int head_state4; 370 unsigned int head_state5; 371 unsigned int pll0; 372 unsigned int pll1; 373 unsigned int pll2; 374 unsigned int pll3; 375 unsigned int dp_padctl0; 376 unsigned int dp_padctl2; 377 }; 378 379 struct tegra_sor_soc { 380 bool supports_edp; 381 bool supports_lvds; 382 bool supports_hdmi; 383 bool supports_dp; 384 385 const struct tegra_sor_regs *regs; 386 bool has_nvdisplay; 387 388 const struct tegra_sor_hdmi_settings *settings; 389 unsigned int num_settings; 390 391 const u8 *xbar_cfg; 392 }; 393 394 struct tegra_sor; 395 396 struct tegra_sor_ops { 397 const char *name; 398 int (*probe)(struct tegra_sor *sor); 399 int (*remove)(struct tegra_sor *sor); 400 }; 401 402 struct tegra_sor { 403 struct host1x_client client; 404 struct tegra_output output; 405 struct device *dev; 406 407 const struct tegra_sor_soc *soc; 408 void __iomem *regs; 409 unsigned int index; 410 411 struct reset_control *rst; 412 struct clk *clk_parent; 413 struct clk *clk_safe; 414 struct clk *clk_out; 415 struct clk *clk_pad; 416 struct clk *clk_dp; 417 struct clk *clk; 418 419 struct drm_dp_aux *aux; 420 421 struct drm_info_list *debugfs_files; 422 423 const struct tegra_sor_ops *ops; 424 enum tegra_io_pad pad; 425 426 /* for HDMI 2.0 */ 427 struct tegra_sor_hdmi_settings *settings; 428 unsigned int num_settings; 429 430 struct regulator *avdd_io_supply; 431 struct regulator *vdd_pll_supply; 432 struct regulator *hdmi_supply; 433 434 struct delayed_work scdc; 435 bool scdc_enabled; 436 }; 437 438 struct tegra_sor_state { 439 struct drm_connector_state base; 440 441 unsigned int link_speed; 442 unsigned long pclk; 443 unsigned int bpc; 444 }; 445 446 static inline struct tegra_sor_state * 447 to_sor_state(struct drm_connector_state *state) 448 { 449 return container_of(state, struct tegra_sor_state, base); 450 } 451 452 struct tegra_sor_config { 453 u32 bits_per_pixel; 454 455 u32 active_polarity; 456 u32 active_count; 457 u32 tu_size; 458 u32 active_frac; 459 u32 watermark; 460 461 u32 hblank_symbols; 462 u32 vblank_symbols; 463 }; 464 465 static inline struct tegra_sor * 466 host1x_client_to_sor(struct host1x_client *client) 467 { 468 return container_of(client, struct tegra_sor, client); 469 } 470 471 static inline struct tegra_sor *to_sor(struct tegra_output *output) 472 { 473 return container_of(output, struct tegra_sor, output); 474 } 475 476 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) 477 { 478 u32 value = readl(sor->regs + (offset << 2)); 479 480 trace_sor_readl(sor->dev, offset, value); 481 482 return value; 483 } 484 485 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, 486 unsigned int offset) 487 { 488 trace_sor_writel(sor->dev, offset, value); 489 writel(value, sor->regs + (offset << 2)); 490 } 491 492 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) 493 { 494 int err; 495 496 clk_disable_unprepare(sor->clk); 497 498 err = clk_set_parent(sor->clk_out, parent); 499 if (err < 0) 500 return err; 501 502 err = clk_prepare_enable(sor->clk); 503 if (err < 0) 504 return err; 505 506 return 0; 507 } 508 509 struct tegra_clk_sor_pad { 510 struct clk_hw hw; 511 struct tegra_sor *sor; 512 }; 513 514 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw) 515 { 516 return container_of(hw, struct tegra_clk_sor_pad, hw); 517 } 518 519 static const char * const tegra_clk_sor_pad_parents[] = { 520 "pll_d2_out0", "pll_dp" 521 }; 522 523 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index) 524 { 525 struct tegra_clk_sor_pad *pad = to_pad(hw); 526 struct tegra_sor *sor = pad->sor; 527 u32 value; 528 529 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 530 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 531 532 switch (index) { 533 case 0: 534 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 535 break; 536 537 case 1: 538 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 539 break; 540 } 541 542 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 543 544 return 0; 545 } 546 547 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw) 548 { 549 struct tegra_clk_sor_pad *pad = to_pad(hw); 550 struct tegra_sor *sor = pad->sor; 551 u8 parent = U8_MAX; 552 u32 value; 553 554 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 555 556 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) { 557 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK: 558 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK: 559 parent = 0; 560 break; 561 562 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK: 563 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK: 564 parent = 1; 565 break; 566 } 567 568 return parent; 569 } 570 571 static const struct clk_ops tegra_clk_sor_pad_ops = { 572 .set_parent = tegra_clk_sor_pad_set_parent, 573 .get_parent = tegra_clk_sor_pad_get_parent, 574 }; 575 576 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, 577 const char *name) 578 { 579 struct tegra_clk_sor_pad *pad; 580 struct clk_init_data init; 581 struct clk *clk; 582 583 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); 584 if (!pad) 585 return ERR_PTR(-ENOMEM); 586 587 pad->sor = sor; 588 589 init.name = name; 590 init.flags = 0; 591 init.parent_names = tegra_clk_sor_pad_parents; 592 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents); 593 init.ops = &tegra_clk_sor_pad_ops; 594 595 pad->hw.init = &init; 596 597 clk = devm_clk_register(sor->dev, &pad->hw); 598 599 return clk; 600 } 601 602 static int tegra_sor_dp_train_fast(struct tegra_sor *sor, 603 struct drm_dp_link *link) 604 { 605 unsigned int i; 606 u8 pattern; 607 u32 value; 608 int err; 609 610 /* setup lane parameters */ 611 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | 612 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) | 613 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) | 614 SOR_LANE_DRIVE_CURRENT_LANE0(0x40); 615 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); 616 617 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | 618 SOR_LANE_PREEMPHASIS_LANE2(0x0f) | 619 SOR_LANE_PREEMPHASIS_LANE1(0x0f) | 620 SOR_LANE_PREEMPHASIS_LANE0(0x0f); 621 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); 622 623 value = SOR_LANE_POSTCURSOR_LANE3(0x00) | 624 SOR_LANE_POSTCURSOR_LANE2(0x00) | 625 SOR_LANE_POSTCURSOR_LANE1(0x00) | 626 SOR_LANE_POSTCURSOR_LANE0(0x00); 627 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); 628 629 /* disable LVDS mode */ 630 tegra_sor_writel(sor, 0, SOR_LVDS); 631 632 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 633 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 634 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 635 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ 636 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 637 638 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 639 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 640 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0; 641 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 642 643 usleep_range(10, 100); 644 645 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 646 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 647 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); 648 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 649 650 err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B); 651 if (err < 0) 652 return err; 653 654 for (i = 0, value = 0; i < link->num_lanes; i++) { 655 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 656 SOR_DP_TPG_SCRAMBLER_NONE | 657 SOR_DP_TPG_PATTERN_TRAIN1; 658 value = (value << 8) | lane; 659 } 660 661 tegra_sor_writel(sor, value, SOR_DP_TPG); 662 663 pattern = DP_TRAINING_PATTERN_1; 664 665 err = drm_dp_aux_train(sor->aux, link, pattern); 666 if (err < 0) 667 return err; 668 669 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 670 value |= SOR_DP_SPARE_SEQ_ENABLE; 671 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 672 value |= SOR_DP_SPARE_MACRO_SOR_CLK; 673 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 674 675 for (i = 0, value = 0; i < link->num_lanes; i++) { 676 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 677 SOR_DP_TPG_SCRAMBLER_NONE | 678 SOR_DP_TPG_PATTERN_TRAIN2; 679 value = (value << 8) | lane; 680 } 681 682 tegra_sor_writel(sor, value, SOR_DP_TPG); 683 684 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2; 685 686 err = drm_dp_aux_train(sor->aux, link, pattern); 687 if (err < 0) 688 return err; 689 690 for (i = 0, value = 0; i < link->num_lanes; i++) { 691 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 692 SOR_DP_TPG_SCRAMBLER_GALIOS | 693 SOR_DP_TPG_PATTERN_NONE; 694 value = (value << 8) | lane; 695 } 696 697 tegra_sor_writel(sor, value, SOR_DP_TPG); 698 699 pattern = DP_TRAINING_PATTERN_DISABLE; 700 701 err = drm_dp_aux_train(sor->aux, link, pattern); 702 if (err < 0) 703 return err; 704 705 return 0; 706 } 707 708 static void tegra_sor_super_update(struct tegra_sor *sor) 709 { 710 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 711 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); 712 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 713 } 714 715 static void tegra_sor_update(struct tegra_sor *sor) 716 { 717 tegra_sor_writel(sor, 0, SOR_STATE0); 718 tegra_sor_writel(sor, 1, SOR_STATE0); 719 tegra_sor_writel(sor, 0, SOR_STATE0); 720 } 721 722 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) 723 { 724 u32 value; 725 726 value = tegra_sor_readl(sor, SOR_PWM_DIV); 727 value &= ~SOR_PWM_DIV_MASK; 728 value |= 0x400; /* period */ 729 tegra_sor_writel(sor, value, SOR_PWM_DIV); 730 731 value = tegra_sor_readl(sor, SOR_PWM_CTL); 732 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; 733 value |= 0x400; /* duty cycle */ 734 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ 735 value |= SOR_PWM_CTL_TRIGGER; 736 tegra_sor_writel(sor, value, SOR_PWM_CTL); 737 738 timeout = jiffies + msecs_to_jiffies(timeout); 739 740 while (time_before(jiffies, timeout)) { 741 value = tegra_sor_readl(sor, SOR_PWM_CTL); 742 if ((value & SOR_PWM_CTL_TRIGGER) == 0) 743 return 0; 744 745 usleep_range(25, 100); 746 } 747 748 return -ETIMEDOUT; 749 } 750 751 static int tegra_sor_attach(struct tegra_sor *sor) 752 { 753 unsigned long value, timeout; 754 755 /* wake up in normal mode */ 756 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 757 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; 758 value |= SOR_SUPER_STATE_MODE_NORMAL; 759 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 760 tegra_sor_super_update(sor); 761 762 /* attach */ 763 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 764 value |= SOR_SUPER_STATE_ATTACHED; 765 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 766 tegra_sor_super_update(sor); 767 768 timeout = jiffies + msecs_to_jiffies(250); 769 770 while (time_before(jiffies, timeout)) { 771 value = tegra_sor_readl(sor, SOR_TEST); 772 if ((value & SOR_TEST_ATTACHED) != 0) 773 return 0; 774 775 usleep_range(25, 100); 776 } 777 778 return -ETIMEDOUT; 779 } 780 781 static int tegra_sor_wakeup(struct tegra_sor *sor) 782 { 783 unsigned long value, timeout; 784 785 timeout = jiffies + msecs_to_jiffies(250); 786 787 /* wait for head to wake up */ 788 while (time_before(jiffies, timeout)) { 789 value = tegra_sor_readl(sor, SOR_TEST); 790 value &= SOR_TEST_HEAD_MODE_MASK; 791 792 if (value == SOR_TEST_HEAD_MODE_AWAKE) 793 return 0; 794 795 usleep_range(25, 100); 796 } 797 798 return -ETIMEDOUT; 799 } 800 801 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) 802 { 803 u32 value; 804 805 value = tegra_sor_readl(sor, SOR_PWR); 806 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; 807 tegra_sor_writel(sor, value, SOR_PWR); 808 809 timeout = jiffies + msecs_to_jiffies(timeout); 810 811 while (time_before(jiffies, timeout)) { 812 value = tegra_sor_readl(sor, SOR_PWR); 813 if ((value & SOR_PWR_TRIGGER) == 0) 814 return 0; 815 816 usleep_range(25, 100); 817 } 818 819 return -ETIMEDOUT; 820 } 821 822 struct tegra_sor_params { 823 /* number of link clocks per line */ 824 unsigned int num_clocks; 825 /* ratio between input and output */ 826 u64 ratio; 827 /* precision factor */ 828 u64 precision; 829 830 unsigned int active_polarity; 831 unsigned int active_count; 832 unsigned int active_frac; 833 unsigned int tu_size; 834 unsigned int error; 835 }; 836 837 static int tegra_sor_compute_params(struct tegra_sor *sor, 838 struct tegra_sor_params *params, 839 unsigned int tu_size) 840 { 841 u64 active_sym, active_count, frac, approx; 842 u32 active_polarity, active_frac = 0; 843 const u64 f = params->precision; 844 s64 error; 845 846 active_sym = params->ratio * tu_size; 847 active_count = div_u64(active_sym, f) * f; 848 frac = active_sym - active_count; 849 850 /* fraction < 0.5 */ 851 if (frac >= (f / 2)) { 852 active_polarity = 1; 853 frac = f - frac; 854 } else { 855 active_polarity = 0; 856 } 857 858 if (frac != 0) { 859 frac = div_u64(f * f, frac); /* 1/fraction */ 860 if (frac <= (15 * f)) { 861 active_frac = div_u64(frac, f); 862 863 /* round up */ 864 if (active_polarity) 865 active_frac++; 866 } else { 867 active_frac = active_polarity ? 1 : 15; 868 } 869 } 870 871 if (active_frac == 1) 872 active_polarity = 0; 873 874 if (active_polarity == 1) { 875 if (active_frac) { 876 approx = active_count + (active_frac * (f - 1)) * f; 877 approx = div_u64(approx, active_frac * f); 878 } else { 879 approx = active_count + f; 880 } 881 } else { 882 if (active_frac) 883 approx = active_count + div_u64(f, active_frac); 884 else 885 approx = active_count; 886 } 887 888 error = div_s64(active_sym - approx, tu_size); 889 error *= params->num_clocks; 890 891 if (error <= 0 && abs(error) < params->error) { 892 params->active_count = div_u64(active_count, f); 893 params->active_polarity = active_polarity; 894 params->active_frac = active_frac; 895 params->error = abs(error); 896 params->tu_size = tu_size; 897 898 if (error == 0) 899 return true; 900 } 901 902 return false; 903 } 904 905 static int tegra_sor_compute_config(struct tegra_sor *sor, 906 const struct drm_display_mode *mode, 907 struct tegra_sor_config *config, 908 struct drm_dp_link *link) 909 { 910 const u64 f = 100000, link_rate = link->rate * 1000; 911 const u64 pclk = mode->clock * 1000; 912 u64 input, output, watermark, num; 913 struct tegra_sor_params params; 914 u32 num_syms_per_line; 915 unsigned int i; 916 917 if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel) 918 return -EINVAL; 919 920 output = link_rate * 8 * link->num_lanes; 921 input = pclk * config->bits_per_pixel; 922 923 if (input >= output) 924 return -ERANGE; 925 926 memset(¶ms, 0, sizeof(params)); 927 params.ratio = div64_u64(input * f, output); 928 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); 929 params.precision = f; 930 params.error = 64 * f; 931 params.tu_size = 64; 932 933 for (i = params.tu_size; i >= 32; i--) 934 if (tegra_sor_compute_params(sor, ¶ms, i)) 935 break; 936 937 if (params.active_frac == 0) { 938 config->active_polarity = 0; 939 config->active_count = params.active_count; 940 941 if (!params.active_polarity) 942 config->active_count--; 943 944 config->tu_size = params.tu_size; 945 config->active_frac = 1; 946 } else { 947 config->active_polarity = params.active_polarity; 948 config->active_count = params.active_count; 949 config->active_frac = params.active_frac; 950 config->tu_size = params.tu_size; 951 } 952 953 dev_dbg(sor->dev, 954 "polarity: %d active count: %d tu size: %d active frac: %d\n", 955 config->active_polarity, config->active_count, 956 config->tu_size, config->active_frac); 957 958 watermark = params.ratio * config->tu_size * (f - params.ratio); 959 watermark = div_u64(watermark, f); 960 961 watermark = div_u64(watermark + params.error, f); 962 config->watermark = watermark + (config->bits_per_pixel / 8) + 2; 963 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * 964 (link->num_lanes * 8); 965 966 if (config->watermark > 30) { 967 config->watermark = 30; 968 dev_err(sor->dev, 969 "unable to compute TU size, forcing watermark to %u\n", 970 config->watermark); 971 } else if (config->watermark > num_syms_per_line) { 972 config->watermark = num_syms_per_line; 973 dev_err(sor->dev, "watermark too high, forcing to %u\n", 974 config->watermark); 975 } 976 977 /* compute the number of symbols per horizontal blanking interval */ 978 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; 979 config->hblank_symbols = div_u64(num, pclk); 980 981 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 982 config->hblank_symbols -= 3; 983 984 config->hblank_symbols -= 12 / link->num_lanes; 985 986 /* compute the number of symbols per vertical blanking interval */ 987 num = (mode->hdisplay - 25) * link_rate; 988 config->vblank_symbols = div_u64(num, pclk); 989 config->vblank_symbols -= 36 / link->num_lanes + 4; 990 991 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, 992 config->vblank_symbols); 993 994 return 0; 995 } 996 997 static void tegra_sor_apply_config(struct tegra_sor *sor, 998 const struct tegra_sor_config *config) 999 { 1000 u32 value; 1001 1002 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1003 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; 1004 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); 1005 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1006 1007 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); 1008 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; 1009 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); 1010 1011 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; 1012 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); 1013 1014 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; 1015 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); 1016 1017 if (config->active_polarity) 1018 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 1019 else 1020 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 1021 1022 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; 1023 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; 1024 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); 1025 1026 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); 1027 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; 1028 value |= config->hblank_symbols & 0xffff; 1029 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); 1030 1031 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); 1032 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; 1033 value |= config->vblank_symbols & 0xffff; 1034 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); 1035 } 1036 1037 static void tegra_sor_mode_set(struct tegra_sor *sor, 1038 const struct drm_display_mode *mode, 1039 struct tegra_sor_state *state) 1040 { 1041 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); 1042 unsigned int vbe, vse, hbe, hse, vbs, hbs; 1043 u32 value; 1044 1045 value = tegra_sor_readl(sor, SOR_STATE1); 1046 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; 1047 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 1048 value &= ~SOR_STATE_ASY_OWNER_MASK; 1049 1050 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | 1051 SOR_STATE_ASY_OWNER(dc->pipe + 1); 1052 1053 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1054 value &= ~SOR_STATE_ASY_HSYNCPOL; 1055 1056 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1057 value |= SOR_STATE_ASY_HSYNCPOL; 1058 1059 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1060 value &= ~SOR_STATE_ASY_VSYNCPOL; 1061 1062 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1063 value |= SOR_STATE_ASY_VSYNCPOL; 1064 1065 switch (state->bpc) { 1066 case 16: 1067 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444; 1068 break; 1069 1070 case 12: 1071 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444; 1072 break; 1073 1074 case 10: 1075 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444; 1076 break; 1077 1078 case 8: 1079 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 1080 break; 1081 1082 case 6: 1083 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; 1084 break; 1085 1086 default: 1087 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 1088 break; 1089 } 1090 1091 tegra_sor_writel(sor, value, SOR_STATE1); 1092 1093 /* 1094 * TODO: The video timing programming below doesn't seem to match the 1095 * register definitions. 1096 */ 1097 1098 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); 1099 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); 1100 1101 /* sync end = sync width - 1 */ 1102 vse = mode->vsync_end - mode->vsync_start - 1; 1103 hse = mode->hsync_end - mode->hsync_start - 1; 1104 1105 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); 1106 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); 1107 1108 /* blank end = sync end + back porch */ 1109 vbe = vse + (mode->vtotal - mode->vsync_end); 1110 hbe = hse + (mode->htotal - mode->hsync_end); 1111 1112 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); 1113 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); 1114 1115 /* blank start = blank end + active */ 1116 vbs = vbe + mode->vdisplay; 1117 hbs = hbe + mode->hdisplay; 1118 1119 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); 1120 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); 1121 1122 /* XXX interlacing support */ 1123 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); 1124 } 1125 1126 static int tegra_sor_detach(struct tegra_sor *sor) 1127 { 1128 unsigned long value, timeout; 1129 1130 /* switch to safe mode */ 1131 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1132 value &= ~SOR_SUPER_STATE_MODE_NORMAL; 1133 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1134 tegra_sor_super_update(sor); 1135 1136 timeout = jiffies + msecs_to_jiffies(250); 1137 1138 while (time_before(jiffies, timeout)) { 1139 value = tegra_sor_readl(sor, SOR_PWR); 1140 if (value & SOR_PWR_MODE_SAFE) 1141 break; 1142 } 1143 1144 if ((value & SOR_PWR_MODE_SAFE) == 0) 1145 return -ETIMEDOUT; 1146 1147 /* go to sleep */ 1148 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1149 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; 1150 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1151 tegra_sor_super_update(sor); 1152 1153 /* detach */ 1154 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1155 value &= ~SOR_SUPER_STATE_ATTACHED; 1156 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1157 tegra_sor_super_update(sor); 1158 1159 timeout = jiffies + msecs_to_jiffies(250); 1160 1161 while (time_before(jiffies, timeout)) { 1162 value = tegra_sor_readl(sor, SOR_TEST); 1163 if ((value & SOR_TEST_ATTACHED) == 0) 1164 break; 1165 1166 usleep_range(25, 100); 1167 } 1168 1169 if ((value & SOR_TEST_ATTACHED) != 0) 1170 return -ETIMEDOUT; 1171 1172 return 0; 1173 } 1174 1175 static int tegra_sor_power_down(struct tegra_sor *sor) 1176 { 1177 unsigned long value, timeout; 1178 int err; 1179 1180 value = tegra_sor_readl(sor, SOR_PWR); 1181 value &= ~SOR_PWR_NORMAL_STATE_PU; 1182 value |= SOR_PWR_TRIGGER; 1183 tegra_sor_writel(sor, value, SOR_PWR); 1184 1185 timeout = jiffies + msecs_to_jiffies(250); 1186 1187 while (time_before(jiffies, timeout)) { 1188 value = tegra_sor_readl(sor, SOR_PWR); 1189 if ((value & SOR_PWR_TRIGGER) == 0) 1190 return 0; 1191 1192 usleep_range(25, 100); 1193 } 1194 1195 if ((value & SOR_PWR_TRIGGER) != 0) 1196 return -ETIMEDOUT; 1197 1198 /* switch to safe parent clock */ 1199 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 1200 if (err < 0) { 1201 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 1202 return err; 1203 } 1204 1205 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 1206 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 1207 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); 1208 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 1209 1210 /* stop lane sequencer */ 1211 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | 1212 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; 1213 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 1214 1215 timeout = jiffies + msecs_to_jiffies(250); 1216 1217 while (time_before(jiffies, timeout)) { 1218 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 1219 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 1220 break; 1221 1222 usleep_range(25, 100); 1223 } 1224 1225 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 1226 return -ETIMEDOUT; 1227 1228 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1229 value |= SOR_PLL2_PORT_POWERDOWN; 1230 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1231 1232 usleep_range(20, 100); 1233 1234 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 1235 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; 1236 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 1237 1238 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1239 value |= SOR_PLL2_SEQ_PLLCAPPD; 1240 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1241 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1242 1243 usleep_range(20, 100); 1244 1245 return 0; 1246 } 1247 1248 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) 1249 { 1250 u32 value; 1251 1252 timeout = jiffies + msecs_to_jiffies(timeout); 1253 1254 while (time_before(jiffies, timeout)) { 1255 value = tegra_sor_readl(sor, SOR_CRCA); 1256 if (value & SOR_CRCA_VALID) 1257 return 0; 1258 1259 usleep_range(100, 200); 1260 } 1261 1262 return -ETIMEDOUT; 1263 } 1264 1265 static int tegra_sor_show_crc(struct seq_file *s, void *data) 1266 { 1267 struct drm_info_node *node = s->private; 1268 struct tegra_sor *sor = node->info_ent->data; 1269 struct drm_crtc *crtc = sor->output.encoder.crtc; 1270 struct drm_device *drm = node->minor->dev; 1271 int err = 0; 1272 u32 value; 1273 1274 drm_modeset_lock_all(drm); 1275 1276 if (!crtc || !crtc->state->active) { 1277 err = -EBUSY; 1278 goto unlock; 1279 } 1280 1281 value = tegra_sor_readl(sor, SOR_STATE1); 1282 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 1283 tegra_sor_writel(sor, value, SOR_STATE1); 1284 1285 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); 1286 value |= SOR_CRC_CNTRL_ENABLE; 1287 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); 1288 1289 value = tegra_sor_readl(sor, SOR_TEST); 1290 value &= ~SOR_TEST_CRC_POST_SERIALIZE; 1291 tegra_sor_writel(sor, value, SOR_TEST); 1292 1293 err = tegra_sor_crc_wait(sor, 100); 1294 if (err < 0) 1295 goto unlock; 1296 1297 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); 1298 value = tegra_sor_readl(sor, SOR_CRCB); 1299 1300 seq_printf(s, "%08x\n", value); 1301 1302 unlock: 1303 drm_modeset_unlock_all(drm); 1304 return err; 1305 } 1306 1307 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 1308 1309 static const struct debugfs_reg32 tegra_sor_regs[] = { 1310 DEBUGFS_REG32(SOR_CTXSW), 1311 DEBUGFS_REG32(SOR_SUPER_STATE0), 1312 DEBUGFS_REG32(SOR_SUPER_STATE1), 1313 DEBUGFS_REG32(SOR_STATE0), 1314 DEBUGFS_REG32(SOR_STATE1), 1315 DEBUGFS_REG32(SOR_HEAD_STATE0(0)), 1316 DEBUGFS_REG32(SOR_HEAD_STATE0(1)), 1317 DEBUGFS_REG32(SOR_HEAD_STATE1(0)), 1318 DEBUGFS_REG32(SOR_HEAD_STATE1(1)), 1319 DEBUGFS_REG32(SOR_HEAD_STATE2(0)), 1320 DEBUGFS_REG32(SOR_HEAD_STATE2(1)), 1321 DEBUGFS_REG32(SOR_HEAD_STATE3(0)), 1322 DEBUGFS_REG32(SOR_HEAD_STATE3(1)), 1323 DEBUGFS_REG32(SOR_HEAD_STATE4(0)), 1324 DEBUGFS_REG32(SOR_HEAD_STATE4(1)), 1325 DEBUGFS_REG32(SOR_HEAD_STATE5(0)), 1326 DEBUGFS_REG32(SOR_HEAD_STATE5(1)), 1327 DEBUGFS_REG32(SOR_CRC_CNTRL), 1328 DEBUGFS_REG32(SOR_DP_DEBUG_MVID), 1329 DEBUGFS_REG32(SOR_CLK_CNTRL), 1330 DEBUGFS_REG32(SOR_CAP), 1331 DEBUGFS_REG32(SOR_PWR), 1332 DEBUGFS_REG32(SOR_TEST), 1333 DEBUGFS_REG32(SOR_PLL0), 1334 DEBUGFS_REG32(SOR_PLL1), 1335 DEBUGFS_REG32(SOR_PLL2), 1336 DEBUGFS_REG32(SOR_PLL3), 1337 DEBUGFS_REG32(SOR_CSTM), 1338 DEBUGFS_REG32(SOR_LVDS), 1339 DEBUGFS_REG32(SOR_CRCA), 1340 DEBUGFS_REG32(SOR_CRCB), 1341 DEBUGFS_REG32(SOR_BLANK), 1342 DEBUGFS_REG32(SOR_SEQ_CTL), 1343 DEBUGFS_REG32(SOR_LANE_SEQ_CTL), 1344 DEBUGFS_REG32(SOR_SEQ_INST(0)), 1345 DEBUGFS_REG32(SOR_SEQ_INST(1)), 1346 DEBUGFS_REG32(SOR_SEQ_INST(2)), 1347 DEBUGFS_REG32(SOR_SEQ_INST(3)), 1348 DEBUGFS_REG32(SOR_SEQ_INST(4)), 1349 DEBUGFS_REG32(SOR_SEQ_INST(5)), 1350 DEBUGFS_REG32(SOR_SEQ_INST(6)), 1351 DEBUGFS_REG32(SOR_SEQ_INST(7)), 1352 DEBUGFS_REG32(SOR_SEQ_INST(8)), 1353 DEBUGFS_REG32(SOR_SEQ_INST(9)), 1354 DEBUGFS_REG32(SOR_SEQ_INST(10)), 1355 DEBUGFS_REG32(SOR_SEQ_INST(11)), 1356 DEBUGFS_REG32(SOR_SEQ_INST(12)), 1357 DEBUGFS_REG32(SOR_SEQ_INST(13)), 1358 DEBUGFS_REG32(SOR_SEQ_INST(14)), 1359 DEBUGFS_REG32(SOR_SEQ_INST(15)), 1360 DEBUGFS_REG32(SOR_PWM_DIV), 1361 DEBUGFS_REG32(SOR_PWM_CTL), 1362 DEBUGFS_REG32(SOR_VCRC_A0), 1363 DEBUGFS_REG32(SOR_VCRC_A1), 1364 DEBUGFS_REG32(SOR_VCRC_B0), 1365 DEBUGFS_REG32(SOR_VCRC_B1), 1366 DEBUGFS_REG32(SOR_CCRC_A0), 1367 DEBUGFS_REG32(SOR_CCRC_A1), 1368 DEBUGFS_REG32(SOR_CCRC_B0), 1369 DEBUGFS_REG32(SOR_CCRC_B1), 1370 DEBUGFS_REG32(SOR_EDATA_A0), 1371 DEBUGFS_REG32(SOR_EDATA_A1), 1372 DEBUGFS_REG32(SOR_EDATA_B0), 1373 DEBUGFS_REG32(SOR_EDATA_B1), 1374 DEBUGFS_REG32(SOR_COUNT_A0), 1375 DEBUGFS_REG32(SOR_COUNT_A1), 1376 DEBUGFS_REG32(SOR_COUNT_B0), 1377 DEBUGFS_REG32(SOR_COUNT_B1), 1378 DEBUGFS_REG32(SOR_DEBUG_A0), 1379 DEBUGFS_REG32(SOR_DEBUG_A1), 1380 DEBUGFS_REG32(SOR_DEBUG_B0), 1381 DEBUGFS_REG32(SOR_DEBUG_B1), 1382 DEBUGFS_REG32(SOR_TRIG), 1383 DEBUGFS_REG32(SOR_MSCHECK), 1384 DEBUGFS_REG32(SOR_XBAR_CTRL), 1385 DEBUGFS_REG32(SOR_XBAR_POL), 1386 DEBUGFS_REG32(SOR_DP_LINKCTL0), 1387 DEBUGFS_REG32(SOR_DP_LINKCTL1), 1388 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0), 1389 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1), 1390 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0), 1391 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1), 1392 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0), 1393 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1), 1394 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0), 1395 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1), 1396 DEBUGFS_REG32(SOR_LANE_POSTCURSOR0), 1397 DEBUGFS_REG32(SOR_LANE_POSTCURSOR1), 1398 DEBUGFS_REG32(SOR_DP_CONFIG0), 1399 DEBUGFS_REG32(SOR_DP_CONFIG1), 1400 DEBUGFS_REG32(SOR_DP_MN0), 1401 DEBUGFS_REG32(SOR_DP_MN1), 1402 DEBUGFS_REG32(SOR_DP_PADCTL0), 1403 DEBUGFS_REG32(SOR_DP_PADCTL1), 1404 DEBUGFS_REG32(SOR_DP_PADCTL2), 1405 DEBUGFS_REG32(SOR_DP_DEBUG0), 1406 DEBUGFS_REG32(SOR_DP_DEBUG1), 1407 DEBUGFS_REG32(SOR_DP_SPARE0), 1408 DEBUGFS_REG32(SOR_DP_SPARE1), 1409 DEBUGFS_REG32(SOR_DP_AUDIO_CTRL), 1410 DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS), 1411 DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS), 1412 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER), 1413 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0), 1414 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1), 1415 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2), 1416 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3), 1417 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4), 1418 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5), 1419 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6), 1420 DEBUGFS_REG32(SOR_DP_TPG), 1421 DEBUGFS_REG32(SOR_DP_TPG_CONFIG), 1422 DEBUGFS_REG32(SOR_DP_LQ_CSTM0), 1423 DEBUGFS_REG32(SOR_DP_LQ_CSTM1), 1424 DEBUGFS_REG32(SOR_DP_LQ_CSTM2), 1425 }; 1426 1427 static int tegra_sor_show_regs(struct seq_file *s, void *data) 1428 { 1429 struct drm_info_node *node = s->private; 1430 struct tegra_sor *sor = node->info_ent->data; 1431 struct drm_crtc *crtc = sor->output.encoder.crtc; 1432 struct drm_device *drm = node->minor->dev; 1433 unsigned int i; 1434 int err = 0; 1435 1436 drm_modeset_lock_all(drm); 1437 1438 if (!crtc || !crtc->state->active) { 1439 err = -EBUSY; 1440 goto unlock; 1441 } 1442 1443 for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) { 1444 unsigned int offset = tegra_sor_regs[i].offset; 1445 1446 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name, 1447 offset, tegra_sor_readl(sor, offset)); 1448 } 1449 1450 unlock: 1451 drm_modeset_unlock_all(drm); 1452 return err; 1453 } 1454 1455 static const struct drm_info_list debugfs_files[] = { 1456 { "crc", tegra_sor_show_crc, 0, NULL }, 1457 { "regs", tegra_sor_show_regs, 0, NULL }, 1458 }; 1459 1460 static int tegra_sor_late_register(struct drm_connector *connector) 1461 { 1462 struct tegra_output *output = connector_to_output(connector); 1463 unsigned int i, count = ARRAY_SIZE(debugfs_files); 1464 struct drm_minor *minor = connector->dev->primary; 1465 struct dentry *root = connector->debugfs_entry; 1466 struct tegra_sor *sor = to_sor(output); 1467 int err; 1468 1469 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1470 GFP_KERNEL); 1471 if (!sor->debugfs_files) 1472 return -ENOMEM; 1473 1474 for (i = 0; i < count; i++) 1475 sor->debugfs_files[i].data = sor; 1476 1477 err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor); 1478 if (err < 0) 1479 goto free; 1480 1481 return 0; 1482 1483 free: 1484 kfree(sor->debugfs_files); 1485 sor->debugfs_files = NULL; 1486 1487 return err; 1488 } 1489 1490 static void tegra_sor_early_unregister(struct drm_connector *connector) 1491 { 1492 struct tegra_output *output = connector_to_output(connector); 1493 unsigned int count = ARRAY_SIZE(debugfs_files); 1494 struct tegra_sor *sor = to_sor(output); 1495 1496 drm_debugfs_remove_files(sor->debugfs_files, count, 1497 connector->dev->primary); 1498 kfree(sor->debugfs_files); 1499 sor->debugfs_files = NULL; 1500 } 1501 1502 static void tegra_sor_connector_reset(struct drm_connector *connector) 1503 { 1504 struct tegra_sor_state *state; 1505 1506 state = kzalloc(sizeof(*state), GFP_KERNEL); 1507 if (!state) 1508 return; 1509 1510 if (connector->state) { 1511 __drm_atomic_helper_connector_destroy_state(connector->state); 1512 kfree(connector->state); 1513 } 1514 1515 __drm_atomic_helper_connector_reset(connector, &state->base); 1516 } 1517 1518 static enum drm_connector_status 1519 tegra_sor_connector_detect(struct drm_connector *connector, bool force) 1520 { 1521 struct tegra_output *output = connector_to_output(connector); 1522 struct tegra_sor *sor = to_sor(output); 1523 1524 if (sor->aux) 1525 return drm_dp_aux_detect(sor->aux); 1526 1527 return tegra_output_connector_detect(connector, force); 1528 } 1529 1530 static struct drm_connector_state * 1531 tegra_sor_connector_duplicate_state(struct drm_connector *connector) 1532 { 1533 struct tegra_sor_state *state = to_sor_state(connector->state); 1534 struct tegra_sor_state *copy; 1535 1536 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); 1537 if (!copy) 1538 return NULL; 1539 1540 __drm_atomic_helper_connector_duplicate_state(connector, ©->base); 1541 1542 return ©->base; 1543 } 1544 1545 static const struct drm_connector_funcs tegra_sor_connector_funcs = { 1546 .reset = tegra_sor_connector_reset, 1547 .detect = tegra_sor_connector_detect, 1548 .fill_modes = drm_helper_probe_single_connector_modes, 1549 .destroy = tegra_output_connector_destroy, 1550 .atomic_duplicate_state = tegra_sor_connector_duplicate_state, 1551 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1552 .late_register = tegra_sor_late_register, 1553 .early_unregister = tegra_sor_early_unregister, 1554 }; 1555 1556 static int tegra_sor_connector_get_modes(struct drm_connector *connector) 1557 { 1558 struct tegra_output *output = connector_to_output(connector); 1559 struct tegra_sor *sor = to_sor(output); 1560 int err; 1561 1562 if (sor->aux) 1563 drm_dp_aux_enable(sor->aux); 1564 1565 err = tegra_output_connector_get_modes(connector); 1566 1567 if (sor->aux) 1568 drm_dp_aux_disable(sor->aux); 1569 1570 return err; 1571 } 1572 1573 static enum drm_mode_status 1574 tegra_sor_connector_mode_valid(struct drm_connector *connector, 1575 struct drm_display_mode *mode) 1576 { 1577 return MODE_OK; 1578 } 1579 1580 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = { 1581 .get_modes = tegra_sor_connector_get_modes, 1582 .mode_valid = tegra_sor_connector_mode_valid, 1583 }; 1584 1585 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = { 1586 .destroy = tegra_output_encoder_destroy, 1587 }; 1588 1589 static void tegra_sor_edp_disable(struct drm_encoder *encoder) 1590 { 1591 struct tegra_output *output = encoder_to_output(encoder); 1592 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1593 struct tegra_sor *sor = to_sor(output); 1594 u32 value; 1595 int err; 1596 1597 if (output->panel) 1598 drm_panel_disable(output->panel); 1599 1600 err = tegra_sor_detach(sor); 1601 if (err < 0) 1602 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 1603 1604 tegra_sor_writel(sor, 0, SOR_STATE1); 1605 tegra_sor_update(sor); 1606 1607 /* 1608 * The following accesses registers of the display controller, so make 1609 * sure it's only executed when the output is attached to one. 1610 */ 1611 if (dc) { 1612 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1613 value &= ~SOR_ENABLE(0); 1614 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1615 1616 tegra_dc_commit(dc); 1617 } 1618 1619 err = tegra_sor_power_down(sor); 1620 if (err < 0) 1621 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 1622 1623 if (sor->aux) { 1624 err = drm_dp_aux_disable(sor->aux); 1625 if (err < 0) 1626 dev_err(sor->dev, "failed to disable DP: %d\n", err); 1627 } 1628 1629 err = tegra_io_pad_power_disable(sor->pad); 1630 if (err < 0) 1631 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); 1632 1633 if (output->panel) 1634 drm_panel_unprepare(output->panel); 1635 1636 pm_runtime_put(sor->dev); 1637 } 1638 1639 #if 0 1640 static int calc_h_ref_to_sync(const struct drm_display_mode *mode, 1641 unsigned int *value) 1642 { 1643 unsigned int hfp, hsw, hbp, a = 0, b; 1644 1645 hfp = mode->hsync_start - mode->hdisplay; 1646 hsw = mode->hsync_end - mode->hsync_start; 1647 hbp = mode->htotal - mode->hsync_end; 1648 1649 pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp); 1650 1651 b = hfp - 1; 1652 1653 pr_info("a: %u, b: %u\n", a, b); 1654 pr_info("a + hsw + hbp = %u\n", a + hsw + hbp); 1655 1656 if (a + hsw + hbp <= 11) { 1657 a = 1 + 11 - hsw - hbp; 1658 pr_info("a: %u\n", a); 1659 } 1660 1661 if (a > b) 1662 return -EINVAL; 1663 1664 if (hsw < 1) 1665 return -EINVAL; 1666 1667 if (mode->hdisplay < 16) 1668 return -EINVAL; 1669 1670 if (value) { 1671 if (b > a && a % 2) 1672 *value = a + 1; 1673 else 1674 *value = a; 1675 } 1676 1677 return 0; 1678 } 1679 #endif 1680 1681 static void tegra_sor_edp_enable(struct drm_encoder *encoder) 1682 { 1683 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 1684 struct tegra_output *output = encoder_to_output(encoder); 1685 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1686 struct tegra_sor *sor = to_sor(output); 1687 struct tegra_sor_config config; 1688 struct tegra_sor_state *state; 1689 struct drm_dp_link link; 1690 u8 rate, lanes; 1691 unsigned int i; 1692 int err = 0; 1693 u32 value; 1694 1695 state = to_sor_state(output->connector.state); 1696 1697 pm_runtime_get_sync(sor->dev); 1698 1699 if (output->panel) 1700 drm_panel_prepare(output->panel); 1701 1702 err = drm_dp_aux_enable(sor->aux); 1703 if (err < 0) 1704 dev_err(sor->dev, "failed to enable DP: %d\n", err); 1705 1706 err = drm_dp_link_probe(sor->aux, &link); 1707 if (err < 0) { 1708 dev_err(sor->dev, "failed to probe eDP link: %d\n", err); 1709 return; 1710 } 1711 1712 /* switch to safe parent clock */ 1713 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 1714 if (err < 0) 1715 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 1716 1717 memset(&config, 0, sizeof(config)); 1718 config.bits_per_pixel = state->bpc * 3; 1719 1720 err = tegra_sor_compute_config(sor, mode, &config, &link); 1721 if (err < 0) 1722 dev_err(sor->dev, "failed to compute configuration: %d\n", err); 1723 1724 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1725 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 1726 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 1727 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1728 1729 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1730 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 1731 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1732 usleep_range(20, 100); 1733 1734 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 1735 value |= SOR_PLL3_PLL_VDD_MODE_3V3; 1736 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 1737 1738 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST | 1739 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT; 1740 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 1741 1742 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1743 value |= SOR_PLL2_SEQ_PLLCAPPD; 1744 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1745 value |= SOR_PLL2_LVDS_ENABLE; 1746 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1747 1748 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM; 1749 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 1750 1751 while (true) { 1752 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1753 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0) 1754 break; 1755 1756 usleep_range(250, 1000); 1757 } 1758 1759 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1760 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 1761 value &= ~SOR_PLL2_PORT_POWERDOWN; 1762 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1763 1764 /* 1765 * power up 1766 */ 1767 1768 /* set safe link bandwidth (1.62 Gbps) */ 1769 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1770 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 1771 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; 1772 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1773 1774 /* step 1 */ 1775 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1776 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN | 1777 SOR_PLL2_BANDGAP_POWERDOWN; 1778 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1779 1780 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 1781 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; 1782 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 1783 1784 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 1785 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 1786 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 1787 1788 /* step 2 */ 1789 err = tegra_io_pad_power_enable(sor->pad); 1790 if (err < 0) 1791 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); 1792 1793 usleep_range(5, 100); 1794 1795 /* step 3 */ 1796 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1797 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 1798 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1799 1800 usleep_range(20, 100); 1801 1802 /* step 4 */ 1803 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 1804 value &= ~SOR_PLL0_VCOPD; 1805 value &= ~SOR_PLL0_PWR; 1806 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 1807 1808 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1809 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1810 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1811 1812 usleep_range(200, 1000); 1813 1814 /* step 5 */ 1815 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1816 value &= ~SOR_PLL2_PORT_POWERDOWN; 1817 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1818 1819 /* XXX not in TRM */ 1820 for (value = 0, i = 0; i < 5; i++) 1821 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | 1822 SOR_XBAR_CTRL_LINK1_XSEL(i, i); 1823 1824 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); 1825 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 1826 1827 /* switch to DP parent clock */ 1828 err = tegra_sor_set_parent_clock(sor, sor->clk_dp); 1829 if (err < 0) 1830 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 1831 1832 /* power DP lanes */ 1833 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 1834 1835 if (link.num_lanes <= 2) 1836 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); 1837 else 1838 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2; 1839 1840 if (link.num_lanes <= 1) 1841 value &= ~SOR_DP_PADCTL_PD_TXD_1; 1842 else 1843 value |= SOR_DP_PADCTL_PD_TXD_1; 1844 1845 if (link.num_lanes == 0) 1846 value &= ~SOR_DP_PADCTL_PD_TXD_0; 1847 else 1848 value |= SOR_DP_PADCTL_PD_TXD_0; 1849 1850 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 1851 1852 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1853 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 1854 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes); 1855 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1856 1857 /* start lane sequencer */ 1858 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 1859 SOR_LANE_SEQ_CTL_POWER_STATE_UP; 1860 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 1861 1862 while (true) { 1863 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 1864 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 1865 break; 1866 1867 usleep_range(250, 1000); 1868 } 1869 1870 /* set link bandwidth */ 1871 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1872 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 1873 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; 1874 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1875 1876 tegra_sor_apply_config(sor, &config); 1877 1878 /* enable link */ 1879 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1880 value |= SOR_DP_LINKCTL_ENABLE; 1881 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 1882 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1883 1884 for (i = 0, value = 0; i < 4; i++) { 1885 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 1886 SOR_DP_TPG_SCRAMBLER_GALIOS | 1887 SOR_DP_TPG_PATTERN_NONE; 1888 value = (value << 8) | lane; 1889 } 1890 1891 tegra_sor_writel(sor, value, SOR_DP_TPG); 1892 1893 /* enable pad calibration logic */ 1894 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 1895 value |= SOR_DP_PADCTL_PAD_CAL_PD; 1896 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 1897 1898 err = drm_dp_link_probe(sor->aux, &link); 1899 if (err < 0) 1900 dev_err(sor->dev, "failed to probe eDP link: %d\n", err); 1901 1902 err = drm_dp_link_power_up(sor->aux, &link); 1903 if (err < 0) 1904 dev_err(sor->dev, "failed to power up eDP link: %d\n", err); 1905 1906 err = drm_dp_link_configure(sor->aux, &link); 1907 if (err < 0) 1908 dev_err(sor->dev, "failed to configure eDP link: %d\n", err); 1909 1910 rate = drm_dp_link_rate_to_bw_code(link.rate); 1911 lanes = link.num_lanes; 1912 1913 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1914 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 1915 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); 1916 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1917 1918 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1919 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 1920 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); 1921 1922 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 1923 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 1924 1925 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1926 1927 /* disable training pattern generator */ 1928 1929 for (i = 0; i < link.num_lanes; i++) { 1930 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 1931 SOR_DP_TPG_SCRAMBLER_GALIOS | 1932 SOR_DP_TPG_PATTERN_NONE; 1933 value = (value << 8) | lane; 1934 } 1935 1936 tegra_sor_writel(sor, value, SOR_DP_TPG); 1937 1938 err = tegra_sor_dp_train_fast(sor, &link); 1939 if (err < 0) 1940 dev_err(sor->dev, "DP fast link training failed: %d\n", err); 1941 1942 dev_dbg(sor->dev, "fast link training succeeded\n"); 1943 1944 err = tegra_sor_power_up(sor, 250); 1945 if (err < 0) 1946 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 1947 1948 /* CSTM (LVDS, link A/B, upper) */ 1949 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | 1950 SOR_CSTM_UPPER; 1951 tegra_sor_writel(sor, value, SOR_CSTM); 1952 1953 /* use DP-A protocol */ 1954 value = tegra_sor_readl(sor, SOR_STATE1); 1955 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 1956 value |= SOR_STATE_ASY_PROTOCOL_DP_A; 1957 tegra_sor_writel(sor, value, SOR_STATE1); 1958 1959 tegra_sor_mode_set(sor, mode, state); 1960 1961 /* PWM setup */ 1962 err = tegra_sor_setup_pwm(sor, 250); 1963 if (err < 0) 1964 dev_err(sor->dev, "failed to setup PWM: %d\n", err); 1965 1966 tegra_sor_update(sor); 1967 1968 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1969 value |= SOR_ENABLE(0); 1970 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1971 1972 tegra_dc_commit(dc); 1973 1974 err = tegra_sor_attach(sor); 1975 if (err < 0) 1976 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 1977 1978 err = tegra_sor_wakeup(sor); 1979 if (err < 0) 1980 dev_err(sor->dev, "failed to enable DC: %d\n", err); 1981 1982 if (output->panel) 1983 drm_panel_enable(output->panel); 1984 } 1985 1986 static int 1987 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder, 1988 struct drm_crtc_state *crtc_state, 1989 struct drm_connector_state *conn_state) 1990 { 1991 struct tegra_output *output = encoder_to_output(encoder); 1992 struct tegra_sor_state *state = to_sor_state(conn_state); 1993 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 1994 unsigned long pclk = crtc_state->mode.clock * 1000; 1995 struct tegra_sor *sor = to_sor(output); 1996 struct drm_display_info *info; 1997 int err; 1998 1999 info = &output->connector.display_info; 2000 2001 /* 2002 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so 2003 * the pixel clock must be corrected accordingly. 2004 */ 2005 if (pclk >= 340000000) { 2006 state->link_speed = 20; 2007 state->pclk = pclk / 2; 2008 } else { 2009 state->link_speed = 10; 2010 state->pclk = pclk; 2011 } 2012 2013 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, 2014 pclk, 0); 2015 if (err < 0) { 2016 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 2017 return err; 2018 } 2019 2020 switch (info->bpc) { 2021 case 8: 2022 case 6: 2023 state->bpc = info->bpc; 2024 break; 2025 2026 default: 2027 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc); 2028 state->bpc = 8; 2029 break; 2030 } 2031 2032 return 0; 2033 } 2034 2035 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = { 2036 .disable = tegra_sor_edp_disable, 2037 .enable = tegra_sor_edp_enable, 2038 .atomic_check = tegra_sor_encoder_atomic_check, 2039 }; 2040 2041 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size) 2042 { 2043 u32 value = 0; 2044 size_t i; 2045 2046 for (i = size; i > 0; i--) 2047 value = (value << 8) | ptr[i - 1]; 2048 2049 return value; 2050 } 2051 2052 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, 2053 const void *data, size_t size) 2054 { 2055 const u8 *ptr = data; 2056 unsigned long offset; 2057 size_t i, j; 2058 u32 value; 2059 2060 switch (ptr[0]) { 2061 case HDMI_INFOFRAME_TYPE_AVI: 2062 offset = SOR_HDMI_AVI_INFOFRAME_HEADER; 2063 break; 2064 2065 case HDMI_INFOFRAME_TYPE_AUDIO: 2066 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER; 2067 break; 2068 2069 case HDMI_INFOFRAME_TYPE_VENDOR: 2070 offset = SOR_HDMI_VSI_INFOFRAME_HEADER; 2071 break; 2072 2073 default: 2074 dev_err(sor->dev, "unsupported infoframe type: %02x\n", 2075 ptr[0]); 2076 return; 2077 } 2078 2079 value = INFOFRAME_HEADER_TYPE(ptr[0]) | 2080 INFOFRAME_HEADER_VERSION(ptr[1]) | 2081 INFOFRAME_HEADER_LEN(ptr[2]); 2082 tegra_sor_writel(sor, value, offset); 2083 offset++; 2084 2085 /* 2086 * Each subpack contains 7 bytes, divided into: 2087 * - subpack_low: bytes 0 - 3 2088 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) 2089 */ 2090 for (i = 3, j = 0; i < size; i += 7, j += 8) { 2091 size_t rem = size - i, num = min_t(size_t, rem, 4); 2092 2093 value = tegra_sor_hdmi_subpack(&ptr[i], num); 2094 tegra_sor_writel(sor, value, offset++); 2095 2096 num = min_t(size_t, rem - num, 3); 2097 2098 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); 2099 tegra_sor_writel(sor, value, offset++); 2100 } 2101 } 2102 2103 static int 2104 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, 2105 const struct drm_display_mode *mode) 2106 { 2107 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; 2108 struct hdmi_avi_infoframe frame; 2109 u32 value; 2110 int err; 2111 2112 /* disable AVI infoframe */ 2113 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 2114 value &= ~INFOFRAME_CTRL_SINGLE; 2115 value &= ~INFOFRAME_CTRL_OTHER; 2116 value &= ~INFOFRAME_CTRL_ENABLE; 2117 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 2118 2119 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); 2120 if (err < 0) { 2121 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 2122 return err; 2123 } 2124 2125 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 2126 if (err < 0) { 2127 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); 2128 return err; 2129 } 2130 2131 tegra_sor_hdmi_write_infopack(sor, buffer, err); 2132 2133 /* enable AVI infoframe */ 2134 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 2135 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; 2136 value |= INFOFRAME_CTRL_ENABLE; 2137 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 2138 2139 return 0; 2140 } 2141 2142 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) 2143 { 2144 u32 value; 2145 2146 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2147 value &= ~INFOFRAME_CTRL_ENABLE; 2148 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2149 } 2150 2151 static struct tegra_sor_hdmi_settings * 2152 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) 2153 { 2154 unsigned int i; 2155 2156 for (i = 0; i < sor->num_settings; i++) 2157 if (frequency <= sor->settings[i].frequency) 2158 return &sor->settings[i]; 2159 2160 return NULL; 2161 } 2162 2163 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor) 2164 { 2165 u32 value; 2166 2167 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); 2168 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; 2169 value &= ~SOR_HDMI2_CTRL_SCRAMBLE; 2170 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); 2171 } 2172 2173 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor) 2174 { 2175 struct i2c_adapter *ddc = sor->output.ddc; 2176 2177 drm_scdc_set_high_tmds_clock_ratio(ddc, false); 2178 drm_scdc_set_scrambling(ddc, false); 2179 2180 tegra_sor_hdmi_disable_scrambling(sor); 2181 } 2182 2183 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor) 2184 { 2185 if (sor->scdc_enabled) { 2186 cancel_delayed_work_sync(&sor->scdc); 2187 tegra_sor_hdmi_scdc_disable(sor); 2188 } 2189 } 2190 2191 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor) 2192 { 2193 u32 value; 2194 2195 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); 2196 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; 2197 value |= SOR_HDMI2_CTRL_SCRAMBLE; 2198 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); 2199 } 2200 2201 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor) 2202 { 2203 struct i2c_adapter *ddc = sor->output.ddc; 2204 2205 drm_scdc_set_high_tmds_clock_ratio(ddc, true); 2206 drm_scdc_set_scrambling(ddc, true); 2207 2208 tegra_sor_hdmi_enable_scrambling(sor); 2209 } 2210 2211 static void tegra_sor_hdmi_scdc_work(struct work_struct *work) 2212 { 2213 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work); 2214 struct i2c_adapter *ddc = sor->output.ddc; 2215 2216 if (!drm_scdc_get_scrambling_status(ddc)) { 2217 DRM_DEBUG_KMS("SCDC not scrambled\n"); 2218 tegra_sor_hdmi_scdc_enable(sor); 2219 } 2220 2221 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); 2222 } 2223 2224 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor) 2225 { 2226 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; 2227 struct drm_display_mode *mode; 2228 2229 mode = &sor->output.encoder.crtc->state->adjusted_mode; 2230 2231 if (mode->clock >= 340000 && scdc->supported) { 2232 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); 2233 tegra_sor_hdmi_scdc_enable(sor); 2234 sor->scdc_enabled = true; 2235 } 2236 } 2237 2238 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) 2239 { 2240 struct tegra_output *output = encoder_to_output(encoder); 2241 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2242 struct tegra_sor *sor = to_sor(output); 2243 u32 value; 2244 int err; 2245 2246 tegra_sor_hdmi_scdc_stop(sor); 2247 2248 err = tegra_sor_detach(sor); 2249 if (err < 0) 2250 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 2251 2252 tegra_sor_writel(sor, 0, SOR_STATE1); 2253 tegra_sor_update(sor); 2254 2255 /* disable display to SOR clock */ 2256 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2257 2258 if (!sor->soc->has_nvdisplay) 2259 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1)); 2260 else 2261 value &= ~SOR_ENABLE(sor->index); 2262 2263 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2264 2265 tegra_dc_commit(dc); 2266 2267 err = tegra_sor_power_down(sor); 2268 if (err < 0) 2269 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 2270 2271 err = tegra_io_pad_power_disable(sor->pad); 2272 if (err < 0) 2273 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); 2274 2275 pm_runtime_put(sor->dev); 2276 } 2277 2278 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) 2279 { 2280 struct tegra_output *output = encoder_to_output(encoder); 2281 unsigned int h_ref_to_sync = 1, pulse_start, max_ac; 2282 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2283 struct tegra_sor_hdmi_settings *settings; 2284 struct tegra_sor *sor = to_sor(output); 2285 struct tegra_sor_state *state; 2286 struct drm_display_mode *mode; 2287 unsigned long rate, pclk; 2288 unsigned int div, i; 2289 u32 value; 2290 int err; 2291 2292 state = to_sor_state(output->connector.state); 2293 mode = &encoder->crtc->state->adjusted_mode; 2294 pclk = mode->clock * 1000; 2295 2296 pm_runtime_get_sync(sor->dev); 2297 2298 /* switch to safe parent clock */ 2299 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 2300 if (err < 0) { 2301 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 2302 return; 2303 } 2304 2305 div = clk_get_rate(sor->clk) / 1000000 * 4; 2306 2307 err = tegra_io_pad_power_enable(sor->pad); 2308 if (err < 0) 2309 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); 2310 2311 usleep_range(20, 100); 2312 2313 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2314 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 2315 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2316 2317 usleep_range(20, 100); 2318 2319 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 2320 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; 2321 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 2322 2323 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2324 value &= ~SOR_PLL0_VCOPD; 2325 value &= ~SOR_PLL0_PWR; 2326 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2327 2328 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2329 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 2330 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2331 2332 usleep_range(200, 400); 2333 2334 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2335 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 2336 value &= ~SOR_PLL2_PORT_POWERDOWN; 2337 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2338 2339 usleep_range(20, 100); 2340 2341 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2342 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 2343 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; 2344 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2345 2346 while (true) { 2347 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2348 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) 2349 break; 2350 2351 usleep_range(250, 1000); 2352 } 2353 2354 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 2355 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5); 2356 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 2357 2358 while (true) { 2359 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2360 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 2361 break; 2362 2363 usleep_range(250, 1000); 2364 } 2365 2366 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 2367 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 2368 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 2369 2370 if (mode->clock < 340000) { 2371 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n"); 2372 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; 2373 } else { 2374 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n"); 2375 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; 2376 } 2377 2378 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 2379 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 2380 2381 /* SOR pad PLL stabilization time */ 2382 usleep_range(250, 1000); 2383 2384 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 2385 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 2386 value |= SOR_DP_LINKCTL_LANE_COUNT(4); 2387 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 2388 2389 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2390 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; 2391 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 2392 value &= ~SOR_DP_SPARE_SEQ_ENABLE; 2393 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK; 2394 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2395 2396 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | 2397 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8); 2398 tegra_sor_writel(sor, value, SOR_SEQ_CTL); 2399 2400 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | 2401 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1); 2402 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); 2403 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); 2404 2405 if (!sor->soc->has_nvdisplay) { 2406 /* program the reference clock */ 2407 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); 2408 tegra_sor_writel(sor, value, SOR_REFCLK); 2409 } 2410 2411 /* XXX not in TRM */ 2412 for (value = 0, i = 0; i < 5; i++) 2413 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | 2414 SOR_XBAR_CTRL_LINK1_XSEL(i, i); 2415 2416 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); 2417 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 2418 2419 /* switch to parent clock */ 2420 err = clk_set_parent(sor->clk, sor->clk_parent); 2421 if (err < 0) { 2422 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 2423 return; 2424 } 2425 2426 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); 2427 if (err < 0) { 2428 dev_err(sor->dev, "failed to set pad clock: %d\n", err); 2429 return; 2430 } 2431 2432 /* adjust clock rate for HDMI 2.0 modes */ 2433 rate = clk_get_rate(sor->clk_parent); 2434 2435 if (mode->clock >= 340000) 2436 rate /= 2; 2437 2438 DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk); 2439 2440 clk_set_rate(sor->clk, rate); 2441 2442 if (!sor->soc->has_nvdisplay) { 2443 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); 2444 2445 /* XXX is this the proper check? */ 2446 if (mode->clock < 75000) 2447 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; 2448 2449 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); 2450 } 2451 2452 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32; 2453 2454 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | 2455 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY); 2456 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); 2457 2458 if (!dc->soc->has_nvdisplay) { 2459 /* H_PULSE2 setup */ 2460 pulse_start = h_ref_to_sync + 2461 (mode->hsync_end - mode->hsync_start) + 2462 (mode->htotal - mode->hsync_end) - 10; 2463 2464 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | 2465 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL; 2466 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); 2467 2468 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); 2469 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); 2470 2471 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); 2472 value |= H_PULSE2_ENABLE; 2473 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); 2474 } 2475 2476 /* infoframe setup */ 2477 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); 2478 if (err < 0) 2479 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 2480 2481 /* XXX HDMI audio support not implemented yet */ 2482 tegra_sor_hdmi_disable_audio_infoframe(sor); 2483 2484 /* use single TMDS protocol */ 2485 value = tegra_sor_readl(sor, SOR_STATE1); 2486 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2487 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; 2488 tegra_sor_writel(sor, value, SOR_STATE1); 2489 2490 /* power up pad calibration */ 2491 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2492 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 2493 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2494 2495 /* production settings */ 2496 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); 2497 if (!settings) { 2498 dev_err(sor->dev, "no settings for pixel clock %d Hz\n", 2499 mode->clock * 1000); 2500 return; 2501 } 2502 2503 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2504 value &= ~SOR_PLL0_ICHPMP_MASK; 2505 value &= ~SOR_PLL0_FILTER_MASK; 2506 value &= ~SOR_PLL0_VCOCAP_MASK; 2507 value |= SOR_PLL0_ICHPMP(settings->ichpmp); 2508 value |= SOR_PLL0_FILTER(settings->filter); 2509 value |= SOR_PLL0_VCOCAP(settings->vcocap); 2510 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2511 2512 /* XXX not in TRM */ 2513 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 2514 value &= ~SOR_PLL1_LOADADJ_MASK; 2515 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 2516 value |= SOR_PLL1_LOADADJ(settings->loadadj); 2517 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); 2518 value |= SOR_PLL1_TMDS_TERM; 2519 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 2520 2521 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 2522 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK; 2523 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; 2524 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK; 2525 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK; 2526 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); 2527 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); 2528 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); 2529 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); 2530 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 2531 2532 value = settings->drive_current[3] << 24 | 2533 settings->drive_current[2] << 16 | 2534 settings->drive_current[1] << 8 | 2535 settings->drive_current[0] << 0; 2536 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); 2537 2538 value = settings->preemphasis[3] << 24 | 2539 settings->preemphasis[2] << 16 | 2540 settings->preemphasis[1] << 8 | 2541 settings->preemphasis[0] << 0; 2542 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); 2543 2544 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2545 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 2546 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 2547 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); 2548 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2549 2550 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); 2551 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK; 2552 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); 2553 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); 2554 2555 /* power down pad calibration */ 2556 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2557 value |= SOR_DP_PADCTL_PAD_CAL_PD; 2558 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2559 2560 if (!dc->soc->has_nvdisplay) { 2561 /* miscellaneous display controller settings */ 2562 value = VSYNC_H_POSITION(1); 2563 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); 2564 } 2565 2566 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); 2567 value &= ~DITHER_CONTROL_MASK; 2568 value &= ~BASE_COLOR_SIZE_MASK; 2569 2570 switch (state->bpc) { 2571 case 6: 2572 value |= BASE_COLOR_SIZE_666; 2573 break; 2574 2575 case 8: 2576 value |= BASE_COLOR_SIZE_888; 2577 break; 2578 2579 case 10: 2580 value |= BASE_COLOR_SIZE_101010; 2581 break; 2582 2583 case 12: 2584 value |= BASE_COLOR_SIZE_121212; 2585 break; 2586 2587 default: 2588 WARN(1, "%u bits-per-color not supported\n", state->bpc); 2589 value |= BASE_COLOR_SIZE_888; 2590 break; 2591 } 2592 2593 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); 2594 2595 /* XXX set display head owner */ 2596 value = tegra_sor_readl(sor, SOR_STATE1); 2597 value &= ~SOR_STATE_ASY_OWNER_MASK; 2598 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); 2599 tegra_sor_writel(sor, value, SOR_STATE1); 2600 2601 err = tegra_sor_power_up(sor, 250); 2602 if (err < 0) 2603 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 2604 2605 /* configure dynamic range of output */ 2606 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); 2607 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; 2608 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; 2609 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); 2610 2611 /* configure colorspace */ 2612 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); 2613 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; 2614 value |= SOR_HEAD_STATE_COLORSPACE_RGB; 2615 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); 2616 2617 tegra_sor_mode_set(sor, mode, state); 2618 2619 tegra_sor_update(sor); 2620 2621 /* program preamble timing in SOR (XXX) */ 2622 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2623 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; 2624 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2625 2626 err = tegra_sor_attach(sor); 2627 if (err < 0) 2628 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 2629 2630 /* enable display to SOR clock and generate HDMI preamble */ 2631 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2632 2633 if (!sor->soc->has_nvdisplay) 2634 value |= SOR_ENABLE(1) | SOR1_TIMING_CYA; 2635 else 2636 value |= SOR_ENABLE(sor->index); 2637 2638 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2639 2640 if (dc->soc->has_nvdisplay) { 2641 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); 2642 value &= ~PROTOCOL_MASK; 2643 value |= PROTOCOL_SINGLE_TMDS_A; 2644 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); 2645 } 2646 2647 tegra_dc_commit(dc); 2648 2649 err = tegra_sor_wakeup(sor); 2650 if (err < 0) 2651 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); 2652 2653 tegra_sor_hdmi_scdc_start(sor); 2654 } 2655 2656 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = { 2657 .disable = tegra_sor_hdmi_disable, 2658 .enable = tegra_sor_hdmi_enable, 2659 .atomic_check = tegra_sor_encoder_atomic_check, 2660 }; 2661 2662 static int tegra_sor_init(struct host1x_client *client) 2663 { 2664 struct drm_device *drm = dev_get_drvdata(client->parent); 2665 const struct drm_encoder_helper_funcs *helpers = NULL; 2666 struct tegra_sor *sor = host1x_client_to_sor(client); 2667 int connector = DRM_MODE_CONNECTOR_Unknown; 2668 int encoder = DRM_MODE_ENCODER_NONE; 2669 int err; 2670 2671 if (!sor->aux) { 2672 if (sor->soc->supports_hdmi) { 2673 connector = DRM_MODE_CONNECTOR_HDMIA; 2674 encoder = DRM_MODE_ENCODER_TMDS; 2675 helpers = &tegra_sor_hdmi_helpers; 2676 } else if (sor->soc->supports_lvds) { 2677 connector = DRM_MODE_CONNECTOR_LVDS; 2678 encoder = DRM_MODE_ENCODER_LVDS; 2679 } 2680 } else { 2681 if (sor->soc->supports_edp) { 2682 connector = DRM_MODE_CONNECTOR_eDP; 2683 encoder = DRM_MODE_ENCODER_TMDS; 2684 helpers = &tegra_sor_edp_helpers; 2685 } else if (sor->soc->supports_dp) { 2686 connector = DRM_MODE_CONNECTOR_DisplayPort; 2687 encoder = DRM_MODE_ENCODER_TMDS; 2688 } 2689 } 2690 2691 sor->output.dev = sor->dev; 2692 2693 drm_connector_init(drm, &sor->output.connector, 2694 &tegra_sor_connector_funcs, 2695 connector); 2696 drm_connector_helper_add(&sor->output.connector, 2697 &tegra_sor_connector_helper_funcs); 2698 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; 2699 2700 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs, 2701 encoder, NULL); 2702 drm_encoder_helper_add(&sor->output.encoder, helpers); 2703 2704 drm_connector_attach_encoder(&sor->output.connector, 2705 &sor->output.encoder); 2706 drm_connector_register(&sor->output.connector); 2707 2708 err = tegra_output_init(drm, &sor->output); 2709 if (err < 0) { 2710 dev_err(client->dev, "failed to initialize output: %d\n", err); 2711 return err; 2712 } 2713 2714 tegra_output_find_possible_crtcs(&sor->output, drm); 2715 2716 if (sor->aux) { 2717 err = drm_dp_aux_attach(sor->aux, &sor->output); 2718 if (err < 0) { 2719 dev_err(sor->dev, "failed to attach DP: %d\n", err); 2720 return err; 2721 } 2722 } 2723 2724 /* 2725 * XXX: Remove this reset once proper hand-over from firmware to 2726 * kernel is possible. 2727 */ 2728 if (sor->rst) { 2729 err = reset_control_assert(sor->rst); 2730 if (err < 0) { 2731 dev_err(sor->dev, "failed to assert SOR reset: %d\n", 2732 err); 2733 return err; 2734 } 2735 } 2736 2737 err = clk_prepare_enable(sor->clk); 2738 if (err < 0) { 2739 dev_err(sor->dev, "failed to enable clock: %d\n", err); 2740 return err; 2741 } 2742 2743 usleep_range(1000, 3000); 2744 2745 if (sor->rst) { 2746 err = reset_control_deassert(sor->rst); 2747 if (err < 0) { 2748 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", 2749 err); 2750 return err; 2751 } 2752 } 2753 2754 err = clk_prepare_enable(sor->clk_safe); 2755 if (err < 0) 2756 return err; 2757 2758 err = clk_prepare_enable(sor->clk_dp); 2759 if (err < 0) 2760 return err; 2761 2762 return 0; 2763 } 2764 2765 static int tegra_sor_exit(struct host1x_client *client) 2766 { 2767 struct tegra_sor *sor = host1x_client_to_sor(client); 2768 int err; 2769 2770 tegra_output_exit(&sor->output); 2771 2772 if (sor->aux) { 2773 err = drm_dp_aux_detach(sor->aux); 2774 if (err < 0) { 2775 dev_err(sor->dev, "failed to detach DP: %d\n", err); 2776 return err; 2777 } 2778 } 2779 2780 clk_disable_unprepare(sor->clk_safe); 2781 clk_disable_unprepare(sor->clk_dp); 2782 clk_disable_unprepare(sor->clk); 2783 2784 return 0; 2785 } 2786 2787 static const struct host1x_client_ops sor_client_ops = { 2788 .init = tegra_sor_init, 2789 .exit = tegra_sor_exit, 2790 }; 2791 2792 static const struct tegra_sor_ops tegra_sor_edp_ops = { 2793 .name = "eDP", 2794 }; 2795 2796 static int tegra_sor_hdmi_probe(struct tegra_sor *sor) 2797 { 2798 int err; 2799 2800 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io"); 2801 if (IS_ERR(sor->avdd_io_supply)) { 2802 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n", 2803 PTR_ERR(sor->avdd_io_supply)); 2804 return PTR_ERR(sor->avdd_io_supply); 2805 } 2806 2807 err = regulator_enable(sor->avdd_io_supply); 2808 if (err < 0) { 2809 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", 2810 err); 2811 return err; 2812 } 2813 2814 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll"); 2815 if (IS_ERR(sor->vdd_pll_supply)) { 2816 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n", 2817 PTR_ERR(sor->vdd_pll_supply)); 2818 return PTR_ERR(sor->vdd_pll_supply); 2819 } 2820 2821 err = regulator_enable(sor->vdd_pll_supply); 2822 if (err < 0) { 2823 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", 2824 err); 2825 return err; 2826 } 2827 2828 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); 2829 if (IS_ERR(sor->hdmi_supply)) { 2830 dev_err(sor->dev, "cannot get HDMI supply: %ld\n", 2831 PTR_ERR(sor->hdmi_supply)); 2832 return PTR_ERR(sor->hdmi_supply); 2833 } 2834 2835 err = regulator_enable(sor->hdmi_supply); 2836 if (err < 0) { 2837 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); 2838 return err; 2839 } 2840 2841 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); 2842 2843 return 0; 2844 } 2845 2846 static int tegra_sor_hdmi_remove(struct tegra_sor *sor) 2847 { 2848 regulator_disable(sor->hdmi_supply); 2849 regulator_disable(sor->vdd_pll_supply); 2850 regulator_disable(sor->avdd_io_supply); 2851 2852 return 0; 2853 } 2854 2855 static const struct tegra_sor_ops tegra_sor_hdmi_ops = { 2856 .name = "HDMI", 2857 .probe = tegra_sor_hdmi_probe, 2858 .remove = tegra_sor_hdmi_remove, 2859 }; 2860 2861 static const u8 tegra124_sor_xbar_cfg[5] = { 2862 0, 1, 2, 3, 4 2863 }; 2864 2865 static const struct tegra_sor_regs tegra124_sor_regs = { 2866 .head_state0 = 0x05, 2867 .head_state1 = 0x07, 2868 .head_state2 = 0x09, 2869 .head_state3 = 0x0b, 2870 .head_state4 = 0x0d, 2871 .head_state5 = 0x0f, 2872 .pll0 = 0x17, 2873 .pll1 = 0x18, 2874 .pll2 = 0x19, 2875 .pll3 = 0x1a, 2876 .dp_padctl0 = 0x5c, 2877 .dp_padctl2 = 0x73, 2878 }; 2879 2880 static const struct tegra_sor_soc tegra124_sor = { 2881 .supports_edp = true, 2882 .supports_lvds = true, 2883 .supports_hdmi = false, 2884 .supports_dp = false, 2885 .regs = &tegra124_sor_regs, 2886 .has_nvdisplay = false, 2887 .xbar_cfg = tegra124_sor_xbar_cfg, 2888 }; 2889 2890 static const struct tegra_sor_regs tegra210_sor_regs = { 2891 .head_state0 = 0x05, 2892 .head_state1 = 0x07, 2893 .head_state2 = 0x09, 2894 .head_state3 = 0x0b, 2895 .head_state4 = 0x0d, 2896 .head_state5 = 0x0f, 2897 .pll0 = 0x17, 2898 .pll1 = 0x18, 2899 .pll2 = 0x19, 2900 .pll3 = 0x1a, 2901 .dp_padctl0 = 0x5c, 2902 .dp_padctl2 = 0x73, 2903 }; 2904 2905 static const struct tegra_sor_soc tegra210_sor = { 2906 .supports_edp = true, 2907 .supports_lvds = false, 2908 .supports_hdmi = false, 2909 .supports_dp = false, 2910 .regs = &tegra210_sor_regs, 2911 .has_nvdisplay = false, 2912 .xbar_cfg = tegra124_sor_xbar_cfg, 2913 }; 2914 2915 static const u8 tegra210_sor_xbar_cfg[5] = { 2916 2, 1, 0, 3, 4 2917 }; 2918 2919 static const struct tegra_sor_soc tegra210_sor1 = { 2920 .supports_edp = false, 2921 .supports_lvds = false, 2922 .supports_hdmi = true, 2923 .supports_dp = true, 2924 2925 .regs = &tegra210_sor_regs, 2926 .has_nvdisplay = false, 2927 2928 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults), 2929 .settings = tegra210_sor_hdmi_defaults, 2930 2931 .xbar_cfg = tegra210_sor_xbar_cfg, 2932 }; 2933 2934 static const struct tegra_sor_regs tegra186_sor_regs = { 2935 .head_state0 = 0x151, 2936 .head_state1 = 0x154, 2937 .head_state2 = 0x157, 2938 .head_state3 = 0x15a, 2939 .head_state4 = 0x15d, 2940 .head_state5 = 0x160, 2941 .pll0 = 0x163, 2942 .pll1 = 0x164, 2943 .pll2 = 0x165, 2944 .pll3 = 0x166, 2945 .dp_padctl0 = 0x168, 2946 .dp_padctl2 = 0x16a, 2947 }; 2948 2949 static const struct tegra_sor_soc tegra186_sor = { 2950 .supports_edp = false, 2951 .supports_lvds = false, 2952 .supports_hdmi = false, 2953 .supports_dp = true, 2954 2955 .regs = &tegra186_sor_regs, 2956 .has_nvdisplay = true, 2957 2958 .xbar_cfg = tegra124_sor_xbar_cfg, 2959 }; 2960 2961 static const struct tegra_sor_soc tegra186_sor1 = { 2962 .supports_edp = false, 2963 .supports_lvds = false, 2964 .supports_hdmi = true, 2965 .supports_dp = true, 2966 2967 .regs = &tegra186_sor_regs, 2968 .has_nvdisplay = true, 2969 2970 .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults), 2971 .settings = tegra186_sor_hdmi_defaults, 2972 2973 .xbar_cfg = tegra124_sor_xbar_cfg, 2974 }; 2975 2976 static const struct tegra_sor_regs tegra194_sor_regs = { 2977 .head_state0 = 0x151, 2978 .head_state1 = 0x155, 2979 .head_state2 = 0x159, 2980 .head_state3 = 0x15d, 2981 .head_state4 = 0x161, 2982 .head_state5 = 0x165, 2983 .pll0 = 0x169, 2984 .pll1 = 0x16a, 2985 .pll2 = 0x16b, 2986 .pll3 = 0x16c, 2987 .dp_padctl0 = 0x16e, 2988 .dp_padctl2 = 0x16f, 2989 }; 2990 2991 static const struct tegra_sor_soc tegra194_sor = { 2992 .supports_edp = true, 2993 .supports_lvds = false, 2994 .supports_hdmi = true, 2995 .supports_dp = true, 2996 2997 .regs = &tegra194_sor_regs, 2998 .has_nvdisplay = true, 2999 3000 .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults), 3001 .settings = tegra194_sor_hdmi_defaults, 3002 3003 .xbar_cfg = tegra210_sor_xbar_cfg, 3004 }; 3005 3006 static const struct of_device_id tegra_sor_of_match[] = { 3007 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor }, 3008 { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 }, 3009 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor }, 3010 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 }, 3011 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor }, 3012 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor }, 3013 { }, 3014 }; 3015 MODULE_DEVICE_TABLE(of, tegra_sor_of_match); 3016 3017 static int tegra_sor_parse_dt(struct tegra_sor *sor) 3018 { 3019 struct device_node *np = sor->dev->of_node; 3020 u32 value; 3021 int err; 3022 3023 if (sor->soc->has_nvdisplay) { 3024 err = of_property_read_u32(np, "nvidia,interface", &value); 3025 if (err < 0) 3026 return err; 3027 3028 sor->index = value; 3029 3030 /* 3031 * override the default that we already set for Tegra210 and 3032 * earlier 3033 */ 3034 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; 3035 } 3036 3037 return 0; 3038 } 3039 3040 static int tegra_sor_probe(struct platform_device *pdev) 3041 { 3042 struct device_node *np; 3043 struct tegra_sor *sor; 3044 struct resource *regs; 3045 int err; 3046 3047 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); 3048 if (!sor) 3049 return -ENOMEM; 3050 3051 sor->soc = of_device_get_match_data(&pdev->dev); 3052 sor->output.dev = sor->dev = &pdev->dev; 3053 3054 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, 3055 sor->soc->num_settings * 3056 sizeof(*sor->settings), 3057 GFP_KERNEL); 3058 if (!sor->settings) 3059 return -ENOMEM; 3060 3061 sor->num_settings = sor->soc->num_settings; 3062 3063 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); 3064 if (np) { 3065 sor->aux = drm_dp_aux_find_by_of_node(np); 3066 of_node_put(np); 3067 3068 if (!sor->aux) 3069 return -EPROBE_DEFER; 3070 } 3071 3072 if (!sor->aux) { 3073 if (sor->soc->supports_hdmi) { 3074 sor->ops = &tegra_sor_hdmi_ops; 3075 sor->pad = TEGRA_IO_PAD_HDMI; 3076 } else if (sor->soc->supports_lvds) { 3077 dev_err(&pdev->dev, "LVDS not supported yet\n"); 3078 return -ENODEV; 3079 } else { 3080 dev_err(&pdev->dev, "unknown (non-DP) support\n"); 3081 return -ENODEV; 3082 } 3083 } else { 3084 if (sor->soc->supports_edp) { 3085 sor->ops = &tegra_sor_edp_ops; 3086 sor->pad = TEGRA_IO_PAD_LVDS; 3087 } else if (sor->soc->supports_dp) { 3088 dev_err(&pdev->dev, "DisplayPort not supported yet\n"); 3089 return -ENODEV; 3090 } else { 3091 dev_err(&pdev->dev, "unknown (DP) support\n"); 3092 return -ENODEV; 3093 } 3094 } 3095 3096 err = tegra_sor_parse_dt(sor); 3097 if (err < 0) 3098 return err; 3099 3100 err = tegra_output_probe(&sor->output); 3101 if (err < 0) { 3102 dev_err(&pdev->dev, "failed to probe output: %d\n", err); 3103 return err; 3104 } 3105 3106 if (sor->ops && sor->ops->probe) { 3107 err = sor->ops->probe(sor); 3108 if (err < 0) { 3109 dev_err(&pdev->dev, "failed to probe %s: %d\n", 3110 sor->ops->name, err); 3111 goto output; 3112 } 3113 } 3114 3115 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3116 sor->regs = devm_ioremap_resource(&pdev->dev, regs); 3117 if (IS_ERR(sor->regs)) { 3118 err = PTR_ERR(sor->regs); 3119 goto remove; 3120 } 3121 3122 if (!pdev->dev.pm_domain) { 3123 sor->rst = devm_reset_control_get(&pdev->dev, "sor"); 3124 if (IS_ERR(sor->rst)) { 3125 err = PTR_ERR(sor->rst); 3126 dev_err(&pdev->dev, "failed to get reset control: %d\n", 3127 err); 3128 goto remove; 3129 } 3130 } 3131 3132 sor->clk = devm_clk_get(&pdev->dev, NULL); 3133 if (IS_ERR(sor->clk)) { 3134 err = PTR_ERR(sor->clk); 3135 dev_err(&pdev->dev, "failed to get module clock: %d\n", err); 3136 goto remove; 3137 } 3138 3139 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { 3140 struct device_node *np = pdev->dev.of_node; 3141 const char *name; 3142 3143 /* 3144 * For backwards compatibility with Tegra210 device trees, 3145 * fall back to the old clock name "source" if the new "out" 3146 * clock is not available. 3147 */ 3148 if (of_property_match_string(np, "clock-names", "out") < 0) 3149 name = "source"; 3150 else 3151 name = "out"; 3152 3153 sor->clk_out = devm_clk_get(&pdev->dev, name); 3154 if (IS_ERR(sor->clk_out)) { 3155 err = PTR_ERR(sor->clk_out); 3156 dev_err(sor->dev, "failed to get %s clock: %d\n", 3157 name, err); 3158 goto remove; 3159 } 3160 } else { 3161 /* fall back to the module clock on SOR0 (eDP/LVDS only) */ 3162 sor->clk_out = sor->clk; 3163 } 3164 3165 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); 3166 if (IS_ERR(sor->clk_parent)) { 3167 err = PTR_ERR(sor->clk_parent); 3168 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err); 3169 goto remove; 3170 } 3171 3172 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); 3173 if (IS_ERR(sor->clk_safe)) { 3174 err = PTR_ERR(sor->clk_safe); 3175 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err); 3176 goto remove; 3177 } 3178 3179 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); 3180 if (IS_ERR(sor->clk_dp)) { 3181 err = PTR_ERR(sor->clk_dp); 3182 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err); 3183 goto remove; 3184 } 3185 3186 /* 3187 * Starting with Tegra186, the BPMP provides an implementation for 3188 * the pad output clock, so we have to look it up from device tree. 3189 */ 3190 sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); 3191 if (IS_ERR(sor->clk_pad)) { 3192 if (sor->clk_pad != ERR_PTR(-ENOENT)) { 3193 err = PTR_ERR(sor->clk_pad); 3194 goto remove; 3195 } 3196 3197 /* 3198 * If the pad output clock is not available, then we assume 3199 * we're on Tegra210 or earlier and have to provide our own 3200 * implementation. 3201 */ 3202 sor->clk_pad = NULL; 3203 } 3204 3205 /* 3206 * The bootloader may have set up the SOR such that it's module clock 3207 * is sourced by one of the display PLLs. However, that doesn't work 3208 * without properly having set up other bits of the SOR. 3209 */ 3210 err = clk_set_parent(sor->clk_out, sor->clk_safe); 3211 if (err < 0) { 3212 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err); 3213 goto remove; 3214 } 3215 3216 platform_set_drvdata(pdev, sor); 3217 pm_runtime_enable(&pdev->dev); 3218 3219 /* 3220 * On Tegra210 and earlier, provide our own implementation for the 3221 * pad output clock. 3222 */ 3223 if (!sor->clk_pad) { 3224 err = pm_runtime_get_sync(&pdev->dev); 3225 if (err < 0) { 3226 dev_err(&pdev->dev, "failed to get runtime PM: %d\n", 3227 err); 3228 goto remove; 3229 } 3230 3231 sor->clk_pad = tegra_clk_sor_pad_register(sor, 3232 "sor1_pad_clkout"); 3233 pm_runtime_put(&pdev->dev); 3234 } 3235 3236 if (IS_ERR(sor->clk_pad)) { 3237 err = PTR_ERR(sor->clk_pad); 3238 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n", 3239 err); 3240 goto remove; 3241 } 3242 3243 INIT_LIST_HEAD(&sor->client.list); 3244 sor->client.ops = &sor_client_ops; 3245 sor->client.dev = &pdev->dev; 3246 3247 err = host1x_client_register(&sor->client); 3248 if (err < 0) { 3249 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 3250 err); 3251 goto remove; 3252 } 3253 3254 return 0; 3255 3256 remove: 3257 if (sor->ops && sor->ops->remove) 3258 sor->ops->remove(sor); 3259 output: 3260 tegra_output_remove(&sor->output); 3261 return err; 3262 } 3263 3264 static int tegra_sor_remove(struct platform_device *pdev) 3265 { 3266 struct tegra_sor *sor = platform_get_drvdata(pdev); 3267 int err; 3268 3269 pm_runtime_disable(&pdev->dev); 3270 3271 err = host1x_client_unregister(&sor->client); 3272 if (err < 0) { 3273 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 3274 err); 3275 return err; 3276 } 3277 3278 if (sor->ops && sor->ops->remove) { 3279 err = sor->ops->remove(sor); 3280 if (err < 0) 3281 dev_err(&pdev->dev, "failed to remove SOR: %d\n", err); 3282 } 3283 3284 tegra_output_remove(&sor->output); 3285 3286 return 0; 3287 } 3288 3289 #ifdef CONFIG_PM 3290 static int tegra_sor_suspend(struct device *dev) 3291 { 3292 struct tegra_sor *sor = dev_get_drvdata(dev); 3293 int err; 3294 3295 if (sor->rst) { 3296 err = reset_control_assert(sor->rst); 3297 if (err < 0) { 3298 dev_err(dev, "failed to assert reset: %d\n", err); 3299 return err; 3300 } 3301 } 3302 3303 usleep_range(1000, 2000); 3304 3305 clk_disable_unprepare(sor->clk); 3306 3307 return 0; 3308 } 3309 3310 static int tegra_sor_resume(struct device *dev) 3311 { 3312 struct tegra_sor *sor = dev_get_drvdata(dev); 3313 int err; 3314 3315 err = clk_prepare_enable(sor->clk); 3316 if (err < 0) { 3317 dev_err(dev, "failed to enable clock: %d\n", err); 3318 return err; 3319 } 3320 3321 usleep_range(1000, 2000); 3322 3323 if (sor->rst) { 3324 err = reset_control_deassert(sor->rst); 3325 if (err < 0) { 3326 dev_err(dev, "failed to deassert reset: %d\n", err); 3327 clk_disable_unprepare(sor->clk); 3328 return err; 3329 } 3330 } 3331 3332 return 0; 3333 } 3334 #endif 3335 3336 static const struct dev_pm_ops tegra_sor_pm_ops = { 3337 SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL) 3338 }; 3339 3340 struct platform_driver tegra_sor_driver = { 3341 .driver = { 3342 .name = "tegra-sor", 3343 .of_match_table = tegra_sor_of_match, 3344 .pm = &tegra_sor_pm_ops, 3345 }, 3346 .probe = tegra_sor_probe, 3347 .remove = tegra_sor_remove, 3348 }; 3349