1 /* 2 * Copyright (C) 2013 NVIDIA Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/debugfs.h> 12 #include <linux/gpio.h> 13 #include <linux/io.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/reset.h> 19 20 #include <soc/tegra/pmc.h> 21 22 #include <sound/hda_verbs.h> 23 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_dp_helper.h> 26 #include <drm/drm_panel.h> 27 #include <drm/drm_scdc_helper.h> 28 29 #include "dc.h" 30 #include "drm.h" 31 #include "sor.h" 32 #include "trace.h" 33 34 #define SOR_REKEY 0x38 35 36 struct tegra_sor_hdmi_settings { 37 unsigned long frequency; 38 39 u8 vcocap; 40 u8 filter; 41 u8 ichpmp; 42 u8 loadadj; 43 u8 tmds_termadj; 44 u8 tx_pu_value; 45 u8 bg_temp_coef; 46 u8 bg_vref_level; 47 u8 avdd10_level; 48 u8 avdd14_level; 49 u8 sparepll; 50 51 u8 drive_current[4]; 52 u8 preemphasis[4]; 53 }; 54 55 #if 1 56 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 57 { 58 .frequency = 54000000, 59 .vcocap = 0x0, 60 .filter = 0x0, 61 .ichpmp = 0x1, 62 .loadadj = 0x3, 63 .tmds_termadj = 0x9, 64 .tx_pu_value = 0x10, 65 .bg_temp_coef = 0x3, 66 .bg_vref_level = 0x8, 67 .avdd10_level = 0x4, 68 .avdd14_level = 0x4, 69 .sparepll = 0x0, 70 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 71 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 72 }, { 73 .frequency = 75000000, 74 .vcocap = 0x3, 75 .filter = 0x0, 76 .ichpmp = 0x1, 77 .loadadj = 0x3, 78 .tmds_termadj = 0x9, 79 .tx_pu_value = 0x40, 80 .bg_temp_coef = 0x3, 81 .bg_vref_level = 0x8, 82 .avdd10_level = 0x4, 83 .avdd14_level = 0x4, 84 .sparepll = 0x0, 85 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 86 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 87 }, { 88 .frequency = 150000000, 89 .vcocap = 0x3, 90 .filter = 0x0, 91 .ichpmp = 0x1, 92 .loadadj = 0x3, 93 .tmds_termadj = 0x9, 94 .tx_pu_value = 0x66, 95 .bg_temp_coef = 0x3, 96 .bg_vref_level = 0x8, 97 .avdd10_level = 0x4, 98 .avdd14_level = 0x4, 99 .sparepll = 0x0, 100 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 101 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 102 }, { 103 .frequency = 300000000, 104 .vcocap = 0x3, 105 .filter = 0x0, 106 .ichpmp = 0x1, 107 .loadadj = 0x3, 108 .tmds_termadj = 0x9, 109 .tx_pu_value = 0x66, 110 .bg_temp_coef = 0x3, 111 .bg_vref_level = 0xa, 112 .avdd10_level = 0x4, 113 .avdd14_level = 0x4, 114 .sparepll = 0x0, 115 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 116 .preemphasis = { 0x00, 0x17, 0x17, 0x17 }, 117 }, { 118 .frequency = 600000000, 119 .vcocap = 0x3, 120 .filter = 0x0, 121 .ichpmp = 0x1, 122 .loadadj = 0x3, 123 .tmds_termadj = 0x9, 124 .tx_pu_value = 0x66, 125 .bg_temp_coef = 0x3, 126 .bg_vref_level = 0x8, 127 .avdd10_level = 0x4, 128 .avdd14_level = 0x4, 129 .sparepll = 0x0, 130 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 131 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 132 }, 133 }; 134 #else 135 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 136 { 137 .frequency = 75000000, 138 .vcocap = 0x3, 139 .filter = 0x0, 140 .ichpmp = 0x1, 141 .loadadj = 0x3, 142 .tmds_termadj = 0x9, 143 .tx_pu_value = 0x40, 144 .bg_temp_coef = 0x3, 145 .bg_vref_level = 0x8, 146 .avdd10_level = 0x4, 147 .avdd14_level = 0x4, 148 .sparepll = 0x0, 149 .drive_current = { 0x29, 0x29, 0x29, 0x29 }, 150 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 151 }, { 152 .frequency = 150000000, 153 .vcocap = 0x3, 154 .filter = 0x0, 155 .ichpmp = 0x1, 156 .loadadj = 0x3, 157 .tmds_termadj = 0x9, 158 .tx_pu_value = 0x66, 159 .bg_temp_coef = 0x3, 160 .bg_vref_level = 0x8, 161 .avdd10_level = 0x4, 162 .avdd14_level = 0x4, 163 .sparepll = 0x0, 164 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 165 .preemphasis = { 0x01, 0x02, 0x02, 0x02 }, 166 }, { 167 .frequency = 300000000, 168 .vcocap = 0x3, 169 .filter = 0x0, 170 .ichpmp = 0x6, 171 .loadadj = 0x3, 172 .tmds_termadj = 0x9, 173 .tx_pu_value = 0x66, 174 .bg_temp_coef = 0x3, 175 .bg_vref_level = 0xf, 176 .avdd10_level = 0x4, 177 .avdd14_level = 0x4, 178 .sparepll = 0x0, 179 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 180 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e }, 181 }, { 182 .frequency = 600000000, 183 .vcocap = 0x3, 184 .filter = 0x0, 185 .ichpmp = 0xa, 186 .loadadj = 0x3, 187 .tmds_termadj = 0xb, 188 .tx_pu_value = 0x66, 189 .bg_temp_coef = 0x3, 190 .bg_vref_level = 0xe, 191 .avdd10_level = 0x4, 192 .avdd14_level = 0x4, 193 .sparepll = 0x0, 194 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e }, 195 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f }, 196 }, 197 }; 198 #endif 199 200 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = { 201 { 202 .frequency = 54000000, 203 .vcocap = 0, 204 .filter = 5, 205 .ichpmp = 5, 206 .loadadj = 3, 207 .tmds_termadj = 0xf, 208 .tx_pu_value = 0, 209 .bg_temp_coef = 3, 210 .bg_vref_level = 8, 211 .avdd10_level = 4, 212 .avdd14_level = 4, 213 .sparepll = 0x54, 214 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 215 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 216 }, { 217 .frequency = 75000000, 218 .vcocap = 1, 219 .filter = 5, 220 .ichpmp = 5, 221 .loadadj = 3, 222 .tmds_termadj = 0xf, 223 .tx_pu_value = 0, 224 .bg_temp_coef = 3, 225 .bg_vref_level = 8, 226 .avdd10_level = 4, 227 .avdd14_level = 4, 228 .sparepll = 0x44, 229 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 230 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 231 }, { 232 .frequency = 150000000, 233 .vcocap = 3, 234 .filter = 5, 235 .ichpmp = 5, 236 .loadadj = 3, 237 .tmds_termadj = 15, 238 .tx_pu_value = 0x66 /* 0 */, 239 .bg_temp_coef = 3, 240 .bg_vref_level = 8, 241 .avdd10_level = 4, 242 .avdd14_level = 4, 243 .sparepll = 0x00, /* 0x34 */ 244 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 }, 245 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 246 }, { 247 .frequency = 300000000, 248 .vcocap = 3, 249 .filter = 5, 250 .ichpmp = 5, 251 .loadadj = 3, 252 .tmds_termadj = 15, 253 .tx_pu_value = 64, 254 .bg_temp_coef = 3, 255 .bg_vref_level = 8, 256 .avdd10_level = 4, 257 .avdd14_level = 4, 258 .sparepll = 0x34, 259 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 260 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 261 }, { 262 .frequency = 600000000, 263 .vcocap = 3, 264 .filter = 5, 265 .ichpmp = 5, 266 .loadadj = 3, 267 .tmds_termadj = 12, 268 .tx_pu_value = 96, 269 .bg_temp_coef = 3, 270 .bg_vref_level = 8, 271 .avdd10_level = 4, 272 .avdd14_level = 4, 273 .sparepll = 0x34, 274 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 275 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 276 } 277 }; 278 279 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = { 280 { 281 .frequency = 54000000, 282 .vcocap = 0, 283 .filter = 5, 284 .ichpmp = 5, 285 .loadadj = 3, 286 .tmds_termadj = 0xf, 287 .tx_pu_value = 0, 288 .bg_temp_coef = 3, 289 .bg_vref_level = 8, 290 .avdd10_level = 4, 291 .avdd14_level = 4, 292 .sparepll = 0x54, 293 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 294 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 295 }, { 296 .frequency = 75000000, 297 .vcocap = 1, 298 .filter = 5, 299 .ichpmp = 5, 300 .loadadj = 3, 301 .tmds_termadj = 0xf, 302 .tx_pu_value = 0, 303 .bg_temp_coef = 3, 304 .bg_vref_level = 8, 305 .avdd10_level = 4, 306 .avdd14_level = 4, 307 .sparepll = 0x44, 308 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 309 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 310 }, { 311 .frequency = 150000000, 312 .vcocap = 3, 313 .filter = 5, 314 .ichpmp = 5, 315 .loadadj = 3, 316 .tmds_termadj = 15, 317 .tx_pu_value = 0x66 /* 0 */, 318 .bg_temp_coef = 3, 319 .bg_vref_level = 8, 320 .avdd10_level = 4, 321 .avdd14_level = 4, 322 .sparepll = 0x00, /* 0x34 */ 323 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 }, 324 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 325 }, { 326 .frequency = 300000000, 327 .vcocap = 3, 328 .filter = 5, 329 .ichpmp = 5, 330 .loadadj = 3, 331 .tmds_termadj = 15, 332 .tx_pu_value = 64, 333 .bg_temp_coef = 3, 334 .bg_vref_level = 8, 335 .avdd10_level = 4, 336 .avdd14_level = 4, 337 .sparepll = 0x34, 338 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 339 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 340 }, { 341 .frequency = 600000000, 342 .vcocap = 3, 343 .filter = 5, 344 .ichpmp = 5, 345 .loadadj = 3, 346 .tmds_termadj = 12, 347 .tx_pu_value = 96, 348 .bg_temp_coef = 3, 349 .bg_vref_level = 8, 350 .avdd10_level = 4, 351 .avdd14_level = 4, 352 .sparepll = 0x34, 353 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 354 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 355 } 356 }; 357 358 struct tegra_sor_regs { 359 unsigned int head_state0; 360 unsigned int head_state1; 361 unsigned int head_state2; 362 unsigned int head_state3; 363 unsigned int head_state4; 364 unsigned int head_state5; 365 unsigned int pll0; 366 unsigned int pll1; 367 unsigned int pll2; 368 unsigned int pll3; 369 unsigned int dp_padctl0; 370 unsigned int dp_padctl2; 371 }; 372 373 struct tegra_sor_soc { 374 bool supports_edp; 375 bool supports_lvds; 376 bool supports_hdmi; 377 bool supports_dp; 378 379 const struct tegra_sor_regs *regs; 380 bool has_nvdisplay; 381 382 const struct tegra_sor_hdmi_settings *settings; 383 unsigned int num_settings; 384 385 const u8 *xbar_cfg; 386 }; 387 388 struct tegra_sor; 389 390 struct tegra_sor_ops { 391 const char *name; 392 int (*probe)(struct tegra_sor *sor); 393 int (*remove)(struct tegra_sor *sor); 394 }; 395 396 struct tegra_sor { 397 struct host1x_client client; 398 struct tegra_output output; 399 struct device *dev; 400 401 const struct tegra_sor_soc *soc; 402 void __iomem *regs; 403 unsigned int index; 404 unsigned int irq; 405 406 struct reset_control *rst; 407 struct clk *clk_parent; 408 struct clk *clk_safe; 409 struct clk *clk_out; 410 struct clk *clk_pad; 411 struct clk *clk_dp; 412 struct clk *clk; 413 414 struct drm_dp_aux *aux; 415 416 struct drm_info_list *debugfs_files; 417 418 const struct tegra_sor_ops *ops; 419 enum tegra_io_pad pad; 420 421 /* for HDMI 2.0 */ 422 struct tegra_sor_hdmi_settings *settings; 423 unsigned int num_settings; 424 425 struct regulator *avdd_io_supply; 426 struct regulator *vdd_pll_supply; 427 struct regulator *hdmi_supply; 428 429 struct delayed_work scdc; 430 bool scdc_enabled; 431 432 struct { 433 unsigned int sample_rate; 434 unsigned int channels; 435 } audio; 436 }; 437 438 struct tegra_sor_state { 439 struct drm_connector_state base; 440 441 unsigned int link_speed; 442 unsigned long pclk; 443 unsigned int bpc; 444 }; 445 446 static inline struct tegra_sor_state * 447 to_sor_state(struct drm_connector_state *state) 448 { 449 return container_of(state, struct tegra_sor_state, base); 450 } 451 452 struct tegra_sor_config { 453 u32 bits_per_pixel; 454 455 u32 active_polarity; 456 u32 active_count; 457 u32 tu_size; 458 u32 active_frac; 459 u32 watermark; 460 461 u32 hblank_symbols; 462 u32 vblank_symbols; 463 }; 464 465 static inline struct tegra_sor * 466 host1x_client_to_sor(struct host1x_client *client) 467 { 468 return container_of(client, struct tegra_sor, client); 469 } 470 471 static inline struct tegra_sor *to_sor(struct tegra_output *output) 472 { 473 return container_of(output, struct tegra_sor, output); 474 } 475 476 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) 477 { 478 u32 value = readl(sor->regs + (offset << 2)); 479 480 trace_sor_readl(sor->dev, offset, value); 481 482 return value; 483 } 484 485 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, 486 unsigned int offset) 487 { 488 trace_sor_writel(sor->dev, offset, value); 489 writel(value, sor->regs + (offset << 2)); 490 } 491 492 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) 493 { 494 int err; 495 496 clk_disable_unprepare(sor->clk); 497 498 err = clk_set_parent(sor->clk_out, parent); 499 if (err < 0) 500 return err; 501 502 err = clk_prepare_enable(sor->clk); 503 if (err < 0) 504 return err; 505 506 return 0; 507 } 508 509 struct tegra_clk_sor_pad { 510 struct clk_hw hw; 511 struct tegra_sor *sor; 512 }; 513 514 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw) 515 { 516 return container_of(hw, struct tegra_clk_sor_pad, hw); 517 } 518 519 static const char * const tegra_clk_sor_pad_parents[] = { 520 "pll_d2_out0", "pll_dp" 521 }; 522 523 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index) 524 { 525 struct tegra_clk_sor_pad *pad = to_pad(hw); 526 struct tegra_sor *sor = pad->sor; 527 u32 value; 528 529 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 530 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 531 532 switch (index) { 533 case 0: 534 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 535 break; 536 537 case 1: 538 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 539 break; 540 } 541 542 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 543 544 return 0; 545 } 546 547 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw) 548 { 549 struct tegra_clk_sor_pad *pad = to_pad(hw); 550 struct tegra_sor *sor = pad->sor; 551 u8 parent = U8_MAX; 552 u32 value; 553 554 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 555 556 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) { 557 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK: 558 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK: 559 parent = 0; 560 break; 561 562 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK: 563 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK: 564 parent = 1; 565 break; 566 } 567 568 return parent; 569 } 570 571 static const struct clk_ops tegra_clk_sor_pad_ops = { 572 .set_parent = tegra_clk_sor_pad_set_parent, 573 .get_parent = tegra_clk_sor_pad_get_parent, 574 }; 575 576 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, 577 const char *name) 578 { 579 struct tegra_clk_sor_pad *pad; 580 struct clk_init_data init; 581 struct clk *clk; 582 583 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); 584 if (!pad) 585 return ERR_PTR(-ENOMEM); 586 587 pad->sor = sor; 588 589 init.name = name; 590 init.flags = 0; 591 init.parent_names = tegra_clk_sor_pad_parents; 592 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents); 593 init.ops = &tegra_clk_sor_pad_ops; 594 595 pad->hw.init = &init; 596 597 clk = devm_clk_register(sor->dev, &pad->hw); 598 599 return clk; 600 } 601 602 static int tegra_sor_dp_train_fast(struct tegra_sor *sor, 603 struct drm_dp_link *link) 604 { 605 unsigned int i; 606 u8 pattern; 607 u32 value; 608 int err; 609 610 /* setup lane parameters */ 611 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | 612 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) | 613 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) | 614 SOR_LANE_DRIVE_CURRENT_LANE0(0x40); 615 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); 616 617 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | 618 SOR_LANE_PREEMPHASIS_LANE2(0x0f) | 619 SOR_LANE_PREEMPHASIS_LANE1(0x0f) | 620 SOR_LANE_PREEMPHASIS_LANE0(0x0f); 621 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); 622 623 value = SOR_LANE_POSTCURSOR_LANE3(0x00) | 624 SOR_LANE_POSTCURSOR_LANE2(0x00) | 625 SOR_LANE_POSTCURSOR_LANE1(0x00) | 626 SOR_LANE_POSTCURSOR_LANE0(0x00); 627 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); 628 629 /* disable LVDS mode */ 630 tegra_sor_writel(sor, 0, SOR_LVDS); 631 632 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 633 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 634 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 635 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ 636 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 637 638 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 639 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 640 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0; 641 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 642 643 usleep_range(10, 100); 644 645 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 646 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 647 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); 648 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 649 650 err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B); 651 if (err < 0) 652 return err; 653 654 for (i = 0, value = 0; i < link->num_lanes; i++) { 655 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 656 SOR_DP_TPG_SCRAMBLER_NONE | 657 SOR_DP_TPG_PATTERN_TRAIN1; 658 value = (value << 8) | lane; 659 } 660 661 tegra_sor_writel(sor, value, SOR_DP_TPG); 662 663 pattern = DP_TRAINING_PATTERN_1; 664 665 err = drm_dp_aux_train(sor->aux, link, pattern); 666 if (err < 0) 667 return err; 668 669 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 670 value |= SOR_DP_SPARE_SEQ_ENABLE; 671 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 672 value |= SOR_DP_SPARE_MACRO_SOR_CLK; 673 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 674 675 for (i = 0, value = 0; i < link->num_lanes; i++) { 676 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 677 SOR_DP_TPG_SCRAMBLER_NONE | 678 SOR_DP_TPG_PATTERN_TRAIN2; 679 value = (value << 8) | lane; 680 } 681 682 tegra_sor_writel(sor, value, SOR_DP_TPG); 683 684 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2; 685 686 err = drm_dp_aux_train(sor->aux, link, pattern); 687 if (err < 0) 688 return err; 689 690 for (i = 0, value = 0; i < link->num_lanes; i++) { 691 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 692 SOR_DP_TPG_SCRAMBLER_GALIOS | 693 SOR_DP_TPG_PATTERN_NONE; 694 value = (value << 8) | lane; 695 } 696 697 tegra_sor_writel(sor, value, SOR_DP_TPG); 698 699 pattern = DP_TRAINING_PATTERN_DISABLE; 700 701 err = drm_dp_aux_train(sor->aux, link, pattern); 702 if (err < 0) 703 return err; 704 705 return 0; 706 } 707 708 static void tegra_sor_super_update(struct tegra_sor *sor) 709 { 710 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 711 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); 712 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 713 } 714 715 static void tegra_sor_update(struct tegra_sor *sor) 716 { 717 tegra_sor_writel(sor, 0, SOR_STATE0); 718 tegra_sor_writel(sor, 1, SOR_STATE0); 719 tegra_sor_writel(sor, 0, SOR_STATE0); 720 } 721 722 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) 723 { 724 u32 value; 725 726 value = tegra_sor_readl(sor, SOR_PWM_DIV); 727 value &= ~SOR_PWM_DIV_MASK; 728 value |= 0x400; /* period */ 729 tegra_sor_writel(sor, value, SOR_PWM_DIV); 730 731 value = tegra_sor_readl(sor, SOR_PWM_CTL); 732 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; 733 value |= 0x400; /* duty cycle */ 734 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ 735 value |= SOR_PWM_CTL_TRIGGER; 736 tegra_sor_writel(sor, value, SOR_PWM_CTL); 737 738 timeout = jiffies + msecs_to_jiffies(timeout); 739 740 while (time_before(jiffies, timeout)) { 741 value = tegra_sor_readl(sor, SOR_PWM_CTL); 742 if ((value & SOR_PWM_CTL_TRIGGER) == 0) 743 return 0; 744 745 usleep_range(25, 100); 746 } 747 748 return -ETIMEDOUT; 749 } 750 751 static int tegra_sor_attach(struct tegra_sor *sor) 752 { 753 unsigned long value, timeout; 754 755 /* wake up in normal mode */ 756 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 757 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; 758 value |= SOR_SUPER_STATE_MODE_NORMAL; 759 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 760 tegra_sor_super_update(sor); 761 762 /* attach */ 763 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 764 value |= SOR_SUPER_STATE_ATTACHED; 765 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 766 tegra_sor_super_update(sor); 767 768 timeout = jiffies + msecs_to_jiffies(250); 769 770 while (time_before(jiffies, timeout)) { 771 value = tegra_sor_readl(sor, SOR_TEST); 772 if ((value & SOR_TEST_ATTACHED) != 0) 773 return 0; 774 775 usleep_range(25, 100); 776 } 777 778 return -ETIMEDOUT; 779 } 780 781 static int tegra_sor_wakeup(struct tegra_sor *sor) 782 { 783 unsigned long value, timeout; 784 785 timeout = jiffies + msecs_to_jiffies(250); 786 787 /* wait for head to wake up */ 788 while (time_before(jiffies, timeout)) { 789 value = tegra_sor_readl(sor, SOR_TEST); 790 value &= SOR_TEST_HEAD_MODE_MASK; 791 792 if (value == SOR_TEST_HEAD_MODE_AWAKE) 793 return 0; 794 795 usleep_range(25, 100); 796 } 797 798 return -ETIMEDOUT; 799 } 800 801 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) 802 { 803 u32 value; 804 805 value = tegra_sor_readl(sor, SOR_PWR); 806 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; 807 tegra_sor_writel(sor, value, SOR_PWR); 808 809 timeout = jiffies + msecs_to_jiffies(timeout); 810 811 while (time_before(jiffies, timeout)) { 812 value = tegra_sor_readl(sor, SOR_PWR); 813 if ((value & SOR_PWR_TRIGGER) == 0) 814 return 0; 815 816 usleep_range(25, 100); 817 } 818 819 return -ETIMEDOUT; 820 } 821 822 struct tegra_sor_params { 823 /* number of link clocks per line */ 824 unsigned int num_clocks; 825 /* ratio between input and output */ 826 u64 ratio; 827 /* precision factor */ 828 u64 precision; 829 830 unsigned int active_polarity; 831 unsigned int active_count; 832 unsigned int active_frac; 833 unsigned int tu_size; 834 unsigned int error; 835 }; 836 837 static int tegra_sor_compute_params(struct tegra_sor *sor, 838 struct tegra_sor_params *params, 839 unsigned int tu_size) 840 { 841 u64 active_sym, active_count, frac, approx; 842 u32 active_polarity, active_frac = 0; 843 const u64 f = params->precision; 844 s64 error; 845 846 active_sym = params->ratio * tu_size; 847 active_count = div_u64(active_sym, f) * f; 848 frac = active_sym - active_count; 849 850 /* fraction < 0.5 */ 851 if (frac >= (f / 2)) { 852 active_polarity = 1; 853 frac = f - frac; 854 } else { 855 active_polarity = 0; 856 } 857 858 if (frac != 0) { 859 frac = div_u64(f * f, frac); /* 1/fraction */ 860 if (frac <= (15 * f)) { 861 active_frac = div_u64(frac, f); 862 863 /* round up */ 864 if (active_polarity) 865 active_frac++; 866 } else { 867 active_frac = active_polarity ? 1 : 15; 868 } 869 } 870 871 if (active_frac == 1) 872 active_polarity = 0; 873 874 if (active_polarity == 1) { 875 if (active_frac) { 876 approx = active_count + (active_frac * (f - 1)) * f; 877 approx = div_u64(approx, active_frac * f); 878 } else { 879 approx = active_count + f; 880 } 881 } else { 882 if (active_frac) 883 approx = active_count + div_u64(f, active_frac); 884 else 885 approx = active_count; 886 } 887 888 error = div_s64(active_sym - approx, tu_size); 889 error *= params->num_clocks; 890 891 if (error <= 0 && abs(error) < params->error) { 892 params->active_count = div_u64(active_count, f); 893 params->active_polarity = active_polarity; 894 params->active_frac = active_frac; 895 params->error = abs(error); 896 params->tu_size = tu_size; 897 898 if (error == 0) 899 return true; 900 } 901 902 return false; 903 } 904 905 static int tegra_sor_compute_config(struct tegra_sor *sor, 906 const struct drm_display_mode *mode, 907 struct tegra_sor_config *config, 908 struct drm_dp_link *link) 909 { 910 const u64 f = 100000, link_rate = link->rate * 1000; 911 const u64 pclk = mode->clock * 1000; 912 u64 input, output, watermark, num; 913 struct tegra_sor_params params; 914 u32 num_syms_per_line; 915 unsigned int i; 916 917 if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel) 918 return -EINVAL; 919 920 output = link_rate * 8 * link->num_lanes; 921 input = pclk * config->bits_per_pixel; 922 923 if (input >= output) 924 return -ERANGE; 925 926 memset(¶ms, 0, sizeof(params)); 927 params.ratio = div64_u64(input * f, output); 928 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); 929 params.precision = f; 930 params.error = 64 * f; 931 params.tu_size = 64; 932 933 for (i = params.tu_size; i >= 32; i--) 934 if (tegra_sor_compute_params(sor, ¶ms, i)) 935 break; 936 937 if (params.active_frac == 0) { 938 config->active_polarity = 0; 939 config->active_count = params.active_count; 940 941 if (!params.active_polarity) 942 config->active_count--; 943 944 config->tu_size = params.tu_size; 945 config->active_frac = 1; 946 } else { 947 config->active_polarity = params.active_polarity; 948 config->active_count = params.active_count; 949 config->active_frac = params.active_frac; 950 config->tu_size = params.tu_size; 951 } 952 953 dev_dbg(sor->dev, 954 "polarity: %d active count: %d tu size: %d active frac: %d\n", 955 config->active_polarity, config->active_count, 956 config->tu_size, config->active_frac); 957 958 watermark = params.ratio * config->tu_size * (f - params.ratio); 959 watermark = div_u64(watermark, f); 960 961 watermark = div_u64(watermark + params.error, f); 962 config->watermark = watermark + (config->bits_per_pixel / 8) + 2; 963 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * 964 (link->num_lanes * 8); 965 966 if (config->watermark > 30) { 967 config->watermark = 30; 968 dev_err(sor->dev, 969 "unable to compute TU size, forcing watermark to %u\n", 970 config->watermark); 971 } else if (config->watermark > num_syms_per_line) { 972 config->watermark = num_syms_per_line; 973 dev_err(sor->dev, "watermark too high, forcing to %u\n", 974 config->watermark); 975 } 976 977 /* compute the number of symbols per horizontal blanking interval */ 978 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; 979 config->hblank_symbols = div_u64(num, pclk); 980 981 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 982 config->hblank_symbols -= 3; 983 984 config->hblank_symbols -= 12 / link->num_lanes; 985 986 /* compute the number of symbols per vertical blanking interval */ 987 num = (mode->hdisplay - 25) * link_rate; 988 config->vblank_symbols = div_u64(num, pclk); 989 config->vblank_symbols -= 36 / link->num_lanes + 4; 990 991 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, 992 config->vblank_symbols); 993 994 return 0; 995 } 996 997 static void tegra_sor_apply_config(struct tegra_sor *sor, 998 const struct tegra_sor_config *config) 999 { 1000 u32 value; 1001 1002 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1003 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; 1004 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); 1005 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1006 1007 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); 1008 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; 1009 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); 1010 1011 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; 1012 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); 1013 1014 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; 1015 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); 1016 1017 if (config->active_polarity) 1018 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 1019 else 1020 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 1021 1022 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; 1023 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; 1024 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); 1025 1026 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); 1027 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; 1028 value |= config->hblank_symbols & 0xffff; 1029 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); 1030 1031 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); 1032 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; 1033 value |= config->vblank_symbols & 0xffff; 1034 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); 1035 } 1036 1037 static void tegra_sor_mode_set(struct tegra_sor *sor, 1038 const struct drm_display_mode *mode, 1039 struct tegra_sor_state *state) 1040 { 1041 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); 1042 unsigned int vbe, vse, hbe, hse, vbs, hbs; 1043 u32 value; 1044 1045 value = tegra_sor_readl(sor, SOR_STATE1); 1046 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; 1047 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 1048 value &= ~SOR_STATE_ASY_OWNER_MASK; 1049 1050 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | 1051 SOR_STATE_ASY_OWNER(dc->pipe + 1); 1052 1053 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1054 value &= ~SOR_STATE_ASY_HSYNCPOL; 1055 1056 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1057 value |= SOR_STATE_ASY_HSYNCPOL; 1058 1059 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1060 value &= ~SOR_STATE_ASY_VSYNCPOL; 1061 1062 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1063 value |= SOR_STATE_ASY_VSYNCPOL; 1064 1065 switch (state->bpc) { 1066 case 16: 1067 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444; 1068 break; 1069 1070 case 12: 1071 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444; 1072 break; 1073 1074 case 10: 1075 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444; 1076 break; 1077 1078 case 8: 1079 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 1080 break; 1081 1082 case 6: 1083 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; 1084 break; 1085 1086 default: 1087 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 1088 break; 1089 } 1090 1091 tegra_sor_writel(sor, value, SOR_STATE1); 1092 1093 /* 1094 * TODO: The video timing programming below doesn't seem to match the 1095 * register definitions. 1096 */ 1097 1098 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); 1099 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); 1100 1101 /* sync end = sync width - 1 */ 1102 vse = mode->vsync_end - mode->vsync_start - 1; 1103 hse = mode->hsync_end - mode->hsync_start - 1; 1104 1105 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); 1106 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); 1107 1108 /* blank end = sync end + back porch */ 1109 vbe = vse + (mode->vtotal - mode->vsync_end); 1110 hbe = hse + (mode->htotal - mode->hsync_end); 1111 1112 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); 1113 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); 1114 1115 /* blank start = blank end + active */ 1116 vbs = vbe + mode->vdisplay; 1117 hbs = hbe + mode->hdisplay; 1118 1119 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); 1120 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); 1121 1122 /* XXX interlacing support */ 1123 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); 1124 } 1125 1126 static int tegra_sor_detach(struct tegra_sor *sor) 1127 { 1128 unsigned long value, timeout; 1129 1130 /* switch to safe mode */ 1131 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1132 value &= ~SOR_SUPER_STATE_MODE_NORMAL; 1133 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1134 tegra_sor_super_update(sor); 1135 1136 timeout = jiffies + msecs_to_jiffies(250); 1137 1138 while (time_before(jiffies, timeout)) { 1139 value = tegra_sor_readl(sor, SOR_PWR); 1140 if (value & SOR_PWR_MODE_SAFE) 1141 break; 1142 } 1143 1144 if ((value & SOR_PWR_MODE_SAFE) == 0) 1145 return -ETIMEDOUT; 1146 1147 /* go to sleep */ 1148 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1149 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; 1150 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1151 tegra_sor_super_update(sor); 1152 1153 /* detach */ 1154 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1155 value &= ~SOR_SUPER_STATE_ATTACHED; 1156 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1157 tegra_sor_super_update(sor); 1158 1159 timeout = jiffies + msecs_to_jiffies(250); 1160 1161 while (time_before(jiffies, timeout)) { 1162 value = tegra_sor_readl(sor, SOR_TEST); 1163 if ((value & SOR_TEST_ATTACHED) == 0) 1164 break; 1165 1166 usleep_range(25, 100); 1167 } 1168 1169 if ((value & SOR_TEST_ATTACHED) != 0) 1170 return -ETIMEDOUT; 1171 1172 return 0; 1173 } 1174 1175 static int tegra_sor_power_down(struct tegra_sor *sor) 1176 { 1177 unsigned long value, timeout; 1178 int err; 1179 1180 value = tegra_sor_readl(sor, SOR_PWR); 1181 value &= ~SOR_PWR_NORMAL_STATE_PU; 1182 value |= SOR_PWR_TRIGGER; 1183 tegra_sor_writel(sor, value, SOR_PWR); 1184 1185 timeout = jiffies + msecs_to_jiffies(250); 1186 1187 while (time_before(jiffies, timeout)) { 1188 value = tegra_sor_readl(sor, SOR_PWR); 1189 if ((value & SOR_PWR_TRIGGER) == 0) 1190 return 0; 1191 1192 usleep_range(25, 100); 1193 } 1194 1195 if ((value & SOR_PWR_TRIGGER) != 0) 1196 return -ETIMEDOUT; 1197 1198 /* switch to safe parent clock */ 1199 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 1200 if (err < 0) { 1201 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 1202 return err; 1203 } 1204 1205 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 1206 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 1207 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); 1208 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 1209 1210 /* stop lane sequencer */ 1211 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | 1212 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; 1213 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 1214 1215 timeout = jiffies + msecs_to_jiffies(250); 1216 1217 while (time_before(jiffies, timeout)) { 1218 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 1219 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 1220 break; 1221 1222 usleep_range(25, 100); 1223 } 1224 1225 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 1226 return -ETIMEDOUT; 1227 1228 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1229 value |= SOR_PLL2_PORT_POWERDOWN; 1230 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1231 1232 usleep_range(20, 100); 1233 1234 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 1235 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; 1236 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 1237 1238 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1239 value |= SOR_PLL2_SEQ_PLLCAPPD; 1240 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1241 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1242 1243 usleep_range(20, 100); 1244 1245 return 0; 1246 } 1247 1248 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) 1249 { 1250 u32 value; 1251 1252 timeout = jiffies + msecs_to_jiffies(timeout); 1253 1254 while (time_before(jiffies, timeout)) { 1255 value = tegra_sor_readl(sor, SOR_CRCA); 1256 if (value & SOR_CRCA_VALID) 1257 return 0; 1258 1259 usleep_range(100, 200); 1260 } 1261 1262 return -ETIMEDOUT; 1263 } 1264 1265 static int tegra_sor_show_crc(struct seq_file *s, void *data) 1266 { 1267 struct drm_info_node *node = s->private; 1268 struct tegra_sor *sor = node->info_ent->data; 1269 struct drm_crtc *crtc = sor->output.encoder.crtc; 1270 struct drm_device *drm = node->minor->dev; 1271 int err = 0; 1272 u32 value; 1273 1274 drm_modeset_lock_all(drm); 1275 1276 if (!crtc || !crtc->state->active) { 1277 err = -EBUSY; 1278 goto unlock; 1279 } 1280 1281 value = tegra_sor_readl(sor, SOR_STATE1); 1282 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 1283 tegra_sor_writel(sor, value, SOR_STATE1); 1284 1285 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); 1286 value |= SOR_CRC_CNTRL_ENABLE; 1287 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); 1288 1289 value = tegra_sor_readl(sor, SOR_TEST); 1290 value &= ~SOR_TEST_CRC_POST_SERIALIZE; 1291 tegra_sor_writel(sor, value, SOR_TEST); 1292 1293 err = tegra_sor_crc_wait(sor, 100); 1294 if (err < 0) 1295 goto unlock; 1296 1297 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); 1298 value = tegra_sor_readl(sor, SOR_CRCB); 1299 1300 seq_printf(s, "%08x\n", value); 1301 1302 unlock: 1303 drm_modeset_unlock_all(drm); 1304 return err; 1305 } 1306 1307 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 1308 1309 static const struct debugfs_reg32 tegra_sor_regs[] = { 1310 DEBUGFS_REG32(SOR_CTXSW), 1311 DEBUGFS_REG32(SOR_SUPER_STATE0), 1312 DEBUGFS_REG32(SOR_SUPER_STATE1), 1313 DEBUGFS_REG32(SOR_STATE0), 1314 DEBUGFS_REG32(SOR_STATE1), 1315 DEBUGFS_REG32(SOR_HEAD_STATE0(0)), 1316 DEBUGFS_REG32(SOR_HEAD_STATE0(1)), 1317 DEBUGFS_REG32(SOR_HEAD_STATE1(0)), 1318 DEBUGFS_REG32(SOR_HEAD_STATE1(1)), 1319 DEBUGFS_REG32(SOR_HEAD_STATE2(0)), 1320 DEBUGFS_REG32(SOR_HEAD_STATE2(1)), 1321 DEBUGFS_REG32(SOR_HEAD_STATE3(0)), 1322 DEBUGFS_REG32(SOR_HEAD_STATE3(1)), 1323 DEBUGFS_REG32(SOR_HEAD_STATE4(0)), 1324 DEBUGFS_REG32(SOR_HEAD_STATE4(1)), 1325 DEBUGFS_REG32(SOR_HEAD_STATE5(0)), 1326 DEBUGFS_REG32(SOR_HEAD_STATE5(1)), 1327 DEBUGFS_REG32(SOR_CRC_CNTRL), 1328 DEBUGFS_REG32(SOR_DP_DEBUG_MVID), 1329 DEBUGFS_REG32(SOR_CLK_CNTRL), 1330 DEBUGFS_REG32(SOR_CAP), 1331 DEBUGFS_REG32(SOR_PWR), 1332 DEBUGFS_REG32(SOR_TEST), 1333 DEBUGFS_REG32(SOR_PLL0), 1334 DEBUGFS_REG32(SOR_PLL1), 1335 DEBUGFS_REG32(SOR_PLL2), 1336 DEBUGFS_REG32(SOR_PLL3), 1337 DEBUGFS_REG32(SOR_CSTM), 1338 DEBUGFS_REG32(SOR_LVDS), 1339 DEBUGFS_REG32(SOR_CRCA), 1340 DEBUGFS_REG32(SOR_CRCB), 1341 DEBUGFS_REG32(SOR_BLANK), 1342 DEBUGFS_REG32(SOR_SEQ_CTL), 1343 DEBUGFS_REG32(SOR_LANE_SEQ_CTL), 1344 DEBUGFS_REG32(SOR_SEQ_INST(0)), 1345 DEBUGFS_REG32(SOR_SEQ_INST(1)), 1346 DEBUGFS_REG32(SOR_SEQ_INST(2)), 1347 DEBUGFS_REG32(SOR_SEQ_INST(3)), 1348 DEBUGFS_REG32(SOR_SEQ_INST(4)), 1349 DEBUGFS_REG32(SOR_SEQ_INST(5)), 1350 DEBUGFS_REG32(SOR_SEQ_INST(6)), 1351 DEBUGFS_REG32(SOR_SEQ_INST(7)), 1352 DEBUGFS_REG32(SOR_SEQ_INST(8)), 1353 DEBUGFS_REG32(SOR_SEQ_INST(9)), 1354 DEBUGFS_REG32(SOR_SEQ_INST(10)), 1355 DEBUGFS_REG32(SOR_SEQ_INST(11)), 1356 DEBUGFS_REG32(SOR_SEQ_INST(12)), 1357 DEBUGFS_REG32(SOR_SEQ_INST(13)), 1358 DEBUGFS_REG32(SOR_SEQ_INST(14)), 1359 DEBUGFS_REG32(SOR_SEQ_INST(15)), 1360 DEBUGFS_REG32(SOR_PWM_DIV), 1361 DEBUGFS_REG32(SOR_PWM_CTL), 1362 DEBUGFS_REG32(SOR_VCRC_A0), 1363 DEBUGFS_REG32(SOR_VCRC_A1), 1364 DEBUGFS_REG32(SOR_VCRC_B0), 1365 DEBUGFS_REG32(SOR_VCRC_B1), 1366 DEBUGFS_REG32(SOR_CCRC_A0), 1367 DEBUGFS_REG32(SOR_CCRC_A1), 1368 DEBUGFS_REG32(SOR_CCRC_B0), 1369 DEBUGFS_REG32(SOR_CCRC_B1), 1370 DEBUGFS_REG32(SOR_EDATA_A0), 1371 DEBUGFS_REG32(SOR_EDATA_A1), 1372 DEBUGFS_REG32(SOR_EDATA_B0), 1373 DEBUGFS_REG32(SOR_EDATA_B1), 1374 DEBUGFS_REG32(SOR_COUNT_A0), 1375 DEBUGFS_REG32(SOR_COUNT_A1), 1376 DEBUGFS_REG32(SOR_COUNT_B0), 1377 DEBUGFS_REG32(SOR_COUNT_B1), 1378 DEBUGFS_REG32(SOR_DEBUG_A0), 1379 DEBUGFS_REG32(SOR_DEBUG_A1), 1380 DEBUGFS_REG32(SOR_DEBUG_B0), 1381 DEBUGFS_REG32(SOR_DEBUG_B1), 1382 DEBUGFS_REG32(SOR_TRIG), 1383 DEBUGFS_REG32(SOR_MSCHECK), 1384 DEBUGFS_REG32(SOR_XBAR_CTRL), 1385 DEBUGFS_REG32(SOR_XBAR_POL), 1386 DEBUGFS_REG32(SOR_DP_LINKCTL0), 1387 DEBUGFS_REG32(SOR_DP_LINKCTL1), 1388 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0), 1389 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1), 1390 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0), 1391 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1), 1392 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0), 1393 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1), 1394 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0), 1395 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1), 1396 DEBUGFS_REG32(SOR_LANE_POSTCURSOR0), 1397 DEBUGFS_REG32(SOR_LANE_POSTCURSOR1), 1398 DEBUGFS_REG32(SOR_DP_CONFIG0), 1399 DEBUGFS_REG32(SOR_DP_CONFIG1), 1400 DEBUGFS_REG32(SOR_DP_MN0), 1401 DEBUGFS_REG32(SOR_DP_MN1), 1402 DEBUGFS_REG32(SOR_DP_PADCTL0), 1403 DEBUGFS_REG32(SOR_DP_PADCTL1), 1404 DEBUGFS_REG32(SOR_DP_PADCTL2), 1405 DEBUGFS_REG32(SOR_DP_DEBUG0), 1406 DEBUGFS_REG32(SOR_DP_DEBUG1), 1407 DEBUGFS_REG32(SOR_DP_SPARE0), 1408 DEBUGFS_REG32(SOR_DP_SPARE1), 1409 DEBUGFS_REG32(SOR_DP_AUDIO_CTRL), 1410 DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS), 1411 DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS), 1412 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER), 1413 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0), 1414 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1), 1415 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2), 1416 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3), 1417 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4), 1418 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5), 1419 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6), 1420 DEBUGFS_REG32(SOR_DP_TPG), 1421 DEBUGFS_REG32(SOR_DP_TPG_CONFIG), 1422 DEBUGFS_REG32(SOR_DP_LQ_CSTM0), 1423 DEBUGFS_REG32(SOR_DP_LQ_CSTM1), 1424 DEBUGFS_REG32(SOR_DP_LQ_CSTM2), 1425 }; 1426 1427 static int tegra_sor_show_regs(struct seq_file *s, void *data) 1428 { 1429 struct drm_info_node *node = s->private; 1430 struct tegra_sor *sor = node->info_ent->data; 1431 struct drm_crtc *crtc = sor->output.encoder.crtc; 1432 struct drm_device *drm = node->minor->dev; 1433 unsigned int i; 1434 int err = 0; 1435 1436 drm_modeset_lock_all(drm); 1437 1438 if (!crtc || !crtc->state->active) { 1439 err = -EBUSY; 1440 goto unlock; 1441 } 1442 1443 for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) { 1444 unsigned int offset = tegra_sor_regs[i].offset; 1445 1446 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name, 1447 offset, tegra_sor_readl(sor, offset)); 1448 } 1449 1450 unlock: 1451 drm_modeset_unlock_all(drm); 1452 return err; 1453 } 1454 1455 static const struct drm_info_list debugfs_files[] = { 1456 { "crc", tegra_sor_show_crc, 0, NULL }, 1457 { "regs", tegra_sor_show_regs, 0, NULL }, 1458 }; 1459 1460 static int tegra_sor_late_register(struct drm_connector *connector) 1461 { 1462 struct tegra_output *output = connector_to_output(connector); 1463 unsigned int i, count = ARRAY_SIZE(debugfs_files); 1464 struct drm_minor *minor = connector->dev->primary; 1465 struct dentry *root = connector->debugfs_entry; 1466 struct tegra_sor *sor = to_sor(output); 1467 int err; 1468 1469 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1470 GFP_KERNEL); 1471 if (!sor->debugfs_files) 1472 return -ENOMEM; 1473 1474 for (i = 0; i < count; i++) 1475 sor->debugfs_files[i].data = sor; 1476 1477 err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor); 1478 if (err < 0) 1479 goto free; 1480 1481 return 0; 1482 1483 free: 1484 kfree(sor->debugfs_files); 1485 sor->debugfs_files = NULL; 1486 1487 return err; 1488 } 1489 1490 static void tegra_sor_early_unregister(struct drm_connector *connector) 1491 { 1492 struct tegra_output *output = connector_to_output(connector); 1493 unsigned int count = ARRAY_SIZE(debugfs_files); 1494 struct tegra_sor *sor = to_sor(output); 1495 1496 drm_debugfs_remove_files(sor->debugfs_files, count, 1497 connector->dev->primary); 1498 kfree(sor->debugfs_files); 1499 sor->debugfs_files = NULL; 1500 } 1501 1502 static void tegra_sor_connector_reset(struct drm_connector *connector) 1503 { 1504 struct tegra_sor_state *state; 1505 1506 state = kzalloc(sizeof(*state), GFP_KERNEL); 1507 if (!state) 1508 return; 1509 1510 if (connector->state) { 1511 __drm_atomic_helper_connector_destroy_state(connector->state); 1512 kfree(connector->state); 1513 } 1514 1515 __drm_atomic_helper_connector_reset(connector, &state->base); 1516 } 1517 1518 static enum drm_connector_status 1519 tegra_sor_connector_detect(struct drm_connector *connector, bool force) 1520 { 1521 struct tegra_output *output = connector_to_output(connector); 1522 struct tegra_sor *sor = to_sor(output); 1523 1524 if (sor->aux) 1525 return drm_dp_aux_detect(sor->aux); 1526 1527 return tegra_output_connector_detect(connector, force); 1528 } 1529 1530 static struct drm_connector_state * 1531 tegra_sor_connector_duplicate_state(struct drm_connector *connector) 1532 { 1533 struct tegra_sor_state *state = to_sor_state(connector->state); 1534 struct tegra_sor_state *copy; 1535 1536 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); 1537 if (!copy) 1538 return NULL; 1539 1540 __drm_atomic_helper_connector_duplicate_state(connector, ©->base); 1541 1542 return ©->base; 1543 } 1544 1545 static const struct drm_connector_funcs tegra_sor_connector_funcs = { 1546 .reset = tegra_sor_connector_reset, 1547 .detect = tegra_sor_connector_detect, 1548 .fill_modes = drm_helper_probe_single_connector_modes, 1549 .destroy = tegra_output_connector_destroy, 1550 .atomic_duplicate_state = tegra_sor_connector_duplicate_state, 1551 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1552 .late_register = tegra_sor_late_register, 1553 .early_unregister = tegra_sor_early_unregister, 1554 }; 1555 1556 static int tegra_sor_connector_get_modes(struct drm_connector *connector) 1557 { 1558 struct tegra_output *output = connector_to_output(connector); 1559 struct tegra_sor *sor = to_sor(output); 1560 int err; 1561 1562 if (sor->aux) 1563 drm_dp_aux_enable(sor->aux); 1564 1565 err = tegra_output_connector_get_modes(connector); 1566 1567 if (sor->aux) 1568 drm_dp_aux_disable(sor->aux); 1569 1570 return err; 1571 } 1572 1573 static enum drm_mode_status 1574 tegra_sor_connector_mode_valid(struct drm_connector *connector, 1575 struct drm_display_mode *mode) 1576 { 1577 return MODE_OK; 1578 } 1579 1580 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = { 1581 .get_modes = tegra_sor_connector_get_modes, 1582 .mode_valid = tegra_sor_connector_mode_valid, 1583 }; 1584 1585 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = { 1586 .destroy = tegra_output_encoder_destroy, 1587 }; 1588 1589 static void tegra_sor_edp_disable(struct drm_encoder *encoder) 1590 { 1591 struct tegra_output *output = encoder_to_output(encoder); 1592 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1593 struct tegra_sor *sor = to_sor(output); 1594 u32 value; 1595 int err; 1596 1597 if (output->panel) 1598 drm_panel_disable(output->panel); 1599 1600 err = tegra_sor_detach(sor); 1601 if (err < 0) 1602 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 1603 1604 tegra_sor_writel(sor, 0, SOR_STATE1); 1605 tegra_sor_update(sor); 1606 1607 /* 1608 * The following accesses registers of the display controller, so make 1609 * sure it's only executed when the output is attached to one. 1610 */ 1611 if (dc) { 1612 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1613 value &= ~SOR_ENABLE(0); 1614 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1615 1616 tegra_dc_commit(dc); 1617 } 1618 1619 err = tegra_sor_power_down(sor); 1620 if (err < 0) 1621 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 1622 1623 if (sor->aux) { 1624 err = drm_dp_aux_disable(sor->aux); 1625 if (err < 0) 1626 dev_err(sor->dev, "failed to disable DP: %d\n", err); 1627 } 1628 1629 err = tegra_io_pad_power_disable(sor->pad); 1630 if (err < 0) 1631 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); 1632 1633 if (output->panel) 1634 drm_panel_unprepare(output->panel); 1635 1636 pm_runtime_put(sor->dev); 1637 } 1638 1639 #if 0 1640 static int calc_h_ref_to_sync(const struct drm_display_mode *mode, 1641 unsigned int *value) 1642 { 1643 unsigned int hfp, hsw, hbp, a = 0, b; 1644 1645 hfp = mode->hsync_start - mode->hdisplay; 1646 hsw = mode->hsync_end - mode->hsync_start; 1647 hbp = mode->htotal - mode->hsync_end; 1648 1649 pr_info("hfp: %u, hsw: %u, hbp: %u\n", hfp, hsw, hbp); 1650 1651 b = hfp - 1; 1652 1653 pr_info("a: %u, b: %u\n", a, b); 1654 pr_info("a + hsw + hbp = %u\n", a + hsw + hbp); 1655 1656 if (a + hsw + hbp <= 11) { 1657 a = 1 + 11 - hsw - hbp; 1658 pr_info("a: %u\n", a); 1659 } 1660 1661 if (a > b) 1662 return -EINVAL; 1663 1664 if (hsw < 1) 1665 return -EINVAL; 1666 1667 if (mode->hdisplay < 16) 1668 return -EINVAL; 1669 1670 if (value) { 1671 if (b > a && a % 2) 1672 *value = a + 1; 1673 else 1674 *value = a; 1675 } 1676 1677 return 0; 1678 } 1679 #endif 1680 1681 static void tegra_sor_edp_enable(struct drm_encoder *encoder) 1682 { 1683 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 1684 struct tegra_output *output = encoder_to_output(encoder); 1685 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1686 struct tegra_sor *sor = to_sor(output); 1687 struct tegra_sor_config config; 1688 struct tegra_sor_state *state; 1689 struct drm_dp_link link; 1690 u8 rate, lanes; 1691 unsigned int i; 1692 int err = 0; 1693 u32 value; 1694 1695 state = to_sor_state(output->connector.state); 1696 1697 pm_runtime_get_sync(sor->dev); 1698 1699 if (output->panel) 1700 drm_panel_prepare(output->panel); 1701 1702 err = drm_dp_aux_enable(sor->aux); 1703 if (err < 0) 1704 dev_err(sor->dev, "failed to enable DP: %d\n", err); 1705 1706 err = drm_dp_link_probe(sor->aux, &link); 1707 if (err < 0) { 1708 dev_err(sor->dev, "failed to probe eDP link: %d\n", err); 1709 return; 1710 } 1711 1712 /* switch to safe parent clock */ 1713 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 1714 if (err < 0) 1715 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 1716 1717 memset(&config, 0, sizeof(config)); 1718 config.bits_per_pixel = state->bpc * 3; 1719 1720 err = tegra_sor_compute_config(sor, mode, &config, &link); 1721 if (err < 0) 1722 dev_err(sor->dev, "failed to compute configuration: %d\n", err); 1723 1724 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1725 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 1726 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 1727 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1728 1729 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1730 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 1731 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1732 usleep_range(20, 100); 1733 1734 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 1735 value |= SOR_PLL3_PLL_VDD_MODE_3V3; 1736 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 1737 1738 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST | 1739 SOR_PLL0_PLLREG_LEVEL_V45 | SOR_PLL0_RESISTOR_EXT; 1740 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 1741 1742 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1743 value |= SOR_PLL2_SEQ_PLLCAPPD; 1744 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1745 value |= SOR_PLL2_LVDS_ENABLE; 1746 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1747 1748 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM; 1749 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 1750 1751 while (true) { 1752 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1753 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0) 1754 break; 1755 1756 usleep_range(250, 1000); 1757 } 1758 1759 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1760 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 1761 value &= ~SOR_PLL2_PORT_POWERDOWN; 1762 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1763 1764 /* 1765 * power up 1766 */ 1767 1768 /* set safe link bandwidth (1.62 Gbps) */ 1769 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1770 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 1771 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; 1772 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1773 1774 /* step 1 */ 1775 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1776 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN | 1777 SOR_PLL2_BANDGAP_POWERDOWN; 1778 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1779 1780 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 1781 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; 1782 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 1783 1784 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 1785 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 1786 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 1787 1788 /* step 2 */ 1789 err = tegra_io_pad_power_enable(sor->pad); 1790 if (err < 0) 1791 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); 1792 1793 usleep_range(5, 100); 1794 1795 /* step 3 */ 1796 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1797 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 1798 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1799 1800 usleep_range(20, 100); 1801 1802 /* step 4 */ 1803 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 1804 value &= ~SOR_PLL0_VCOPD; 1805 value &= ~SOR_PLL0_PWR; 1806 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 1807 1808 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1809 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1810 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1811 1812 usleep_range(200, 1000); 1813 1814 /* step 5 */ 1815 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1816 value &= ~SOR_PLL2_PORT_POWERDOWN; 1817 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1818 1819 /* XXX not in TRM */ 1820 for (value = 0, i = 0; i < 5; i++) 1821 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | 1822 SOR_XBAR_CTRL_LINK1_XSEL(i, i); 1823 1824 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); 1825 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 1826 1827 /* switch to DP parent clock */ 1828 err = tegra_sor_set_parent_clock(sor, sor->clk_dp); 1829 if (err < 0) 1830 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 1831 1832 /* power DP lanes */ 1833 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 1834 1835 if (link.num_lanes <= 2) 1836 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); 1837 else 1838 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2; 1839 1840 if (link.num_lanes <= 1) 1841 value &= ~SOR_DP_PADCTL_PD_TXD_1; 1842 else 1843 value |= SOR_DP_PADCTL_PD_TXD_1; 1844 1845 if (link.num_lanes == 0) 1846 value &= ~SOR_DP_PADCTL_PD_TXD_0; 1847 else 1848 value |= SOR_DP_PADCTL_PD_TXD_0; 1849 1850 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 1851 1852 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1853 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 1854 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes); 1855 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1856 1857 /* start lane sequencer */ 1858 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 1859 SOR_LANE_SEQ_CTL_POWER_STATE_UP; 1860 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 1861 1862 while (true) { 1863 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 1864 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 1865 break; 1866 1867 usleep_range(250, 1000); 1868 } 1869 1870 /* set link bandwidth */ 1871 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1872 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 1873 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; 1874 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1875 1876 tegra_sor_apply_config(sor, &config); 1877 1878 /* enable link */ 1879 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1880 value |= SOR_DP_LINKCTL_ENABLE; 1881 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 1882 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1883 1884 for (i = 0, value = 0; i < 4; i++) { 1885 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 1886 SOR_DP_TPG_SCRAMBLER_GALIOS | 1887 SOR_DP_TPG_PATTERN_NONE; 1888 value = (value << 8) | lane; 1889 } 1890 1891 tegra_sor_writel(sor, value, SOR_DP_TPG); 1892 1893 /* enable pad calibration logic */ 1894 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 1895 value |= SOR_DP_PADCTL_PAD_CAL_PD; 1896 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 1897 1898 err = drm_dp_link_probe(sor->aux, &link); 1899 if (err < 0) 1900 dev_err(sor->dev, "failed to probe eDP link: %d\n", err); 1901 1902 err = drm_dp_link_power_up(sor->aux, &link); 1903 if (err < 0) 1904 dev_err(sor->dev, "failed to power up eDP link: %d\n", err); 1905 1906 err = drm_dp_link_configure(sor->aux, &link); 1907 if (err < 0) 1908 dev_err(sor->dev, "failed to configure eDP link: %d\n", err); 1909 1910 rate = drm_dp_link_rate_to_bw_code(link.rate); 1911 lanes = link.num_lanes; 1912 1913 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 1914 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 1915 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); 1916 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 1917 1918 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1919 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 1920 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); 1921 1922 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) 1923 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 1924 1925 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1926 1927 /* disable training pattern generator */ 1928 1929 for (i = 0; i < link.num_lanes; i++) { 1930 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | 1931 SOR_DP_TPG_SCRAMBLER_GALIOS | 1932 SOR_DP_TPG_PATTERN_NONE; 1933 value = (value << 8) | lane; 1934 } 1935 1936 tegra_sor_writel(sor, value, SOR_DP_TPG); 1937 1938 err = tegra_sor_dp_train_fast(sor, &link); 1939 if (err < 0) 1940 dev_err(sor->dev, "DP fast link training failed: %d\n", err); 1941 1942 dev_dbg(sor->dev, "fast link training succeeded\n"); 1943 1944 err = tegra_sor_power_up(sor, 250); 1945 if (err < 0) 1946 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 1947 1948 /* CSTM (LVDS, link A/B, upper) */ 1949 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | 1950 SOR_CSTM_UPPER; 1951 tegra_sor_writel(sor, value, SOR_CSTM); 1952 1953 /* use DP-A protocol */ 1954 value = tegra_sor_readl(sor, SOR_STATE1); 1955 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 1956 value |= SOR_STATE_ASY_PROTOCOL_DP_A; 1957 tegra_sor_writel(sor, value, SOR_STATE1); 1958 1959 tegra_sor_mode_set(sor, mode, state); 1960 1961 /* PWM setup */ 1962 err = tegra_sor_setup_pwm(sor, 250); 1963 if (err < 0) 1964 dev_err(sor->dev, "failed to setup PWM: %d\n", err); 1965 1966 tegra_sor_update(sor); 1967 1968 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1969 value |= SOR_ENABLE(0); 1970 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1971 1972 tegra_dc_commit(dc); 1973 1974 err = tegra_sor_attach(sor); 1975 if (err < 0) 1976 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 1977 1978 err = tegra_sor_wakeup(sor); 1979 if (err < 0) 1980 dev_err(sor->dev, "failed to enable DC: %d\n", err); 1981 1982 if (output->panel) 1983 drm_panel_enable(output->panel); 1984 } 1985 1986 static int 1987 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder, 1988 struct drm_crtc_state *crtc_state, 1989 struct drm_connector_state *conn_state) 1990 { 1991 struct tegra_output *output = encoder_to_output(encoder); 1992 struct tegra_sor_state *state = to_sor_state(conn_state); 1993 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 1994 unsigned long pclk = crtc_state->mode.clock * 1000; 1995 struct tegra_sor *sor = to_sor(output); 1996 struct drm_display_info *info; 1997 int err; 1998 1999 info = &output->connector.display_info; 2000 2001 /* 2002 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so 2003 * the pixel clock must be corrected accordingly. 2004 */ 2005 if (pclk >= 340000000) { 2006 state->link_speed = 20; 2007 state->pclk = pclk / 2; 2008 } else { 2009 state->link_speed = 10; 2010 state->pclk = pclk; 2011 } 2012 2013 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, 2014 pclk, 0); 2015 if (err < 0) { 2016 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 2017 return err; 2018 } 2019 2020 switch (info->bpc) { 2021 case 8: 2022 case 6: 2023 state->bpc = info->bpc; 2024 break; 2025 2026 default: 2027 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc); 2028 state->bpc = 8; 2029 break; 2030 } 2031 2032 return 0; 2033 } 2034 2035 static const struct drm_encoder_helper_funcs tegra_sor_edp_helpers = { 2036 .disable = tegra_sor_edp_disable, 2037 .enable = tegra_sor_edp_enable, 2038 .atomic_check = tegra_sor_encoder_atomic_check, 2039 }; 2040 2041 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size) 2042 { 2043 u32 value = 0; 2044 size_t i; 2045 2046 for (i = size; i > 0; i--) 2047 value = (value << 8) | ptr[i - 1]; 2048 2049 return value; 2050 } 2051 2052 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, 2053 const void *data, size_t size) 2054 { 2055 const u8 *ptr = data; 2056 unsigned long offset; 2057 size_t i, j; 2058 u32 value; 2059 2060 switch (ptr[0]) { 2061 case HDMI_INFOFRAME_TYPE_AVI: 2062 offset = SOR_HDMI_AVI_INFOFRAME_HEADER; 2063 break; 2064 2065 case HDMI_INFOFRAME_TYPE_AUDIO: 2066 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER; 2067 break; 2068 2069 case HDMI_INFOFRAME_TYPE_VENDOR: 2070 offset = SOR_HDMI_VSI_INFOFRAME_HEADER; 2071 break; 2072 2073 default: 2074 dev_err(sor->dev, "unsupported infoframe type: %02x\n", 2075 ptr[0]); 2076 return; 2077 } 2078 2079 value = INFOFRAME_HEADER_TYPE(ptr[0]) | 2080 INFOFRAME_HEADER_VERSION(ptr[1]) | 2081 INFOFRAME_HEADER_LEN(ptr[2]); 2082 tegra_sor_writel(sor, value, offset); 2083 offset++; 2084 2085 /* 2086 * Each subpack contains 7 bytes, divided into: 2087 * - subpack_low: bytes 0 - 3 2088 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) 2089 */ 2090 for (i = 3, j = 0; i < size; i += 7, j += 8) { 2091 size_t rem = size - i, num = min_t(size_t, rem, 4); 2092 2093 value = tegra_sor_hdmi_subpack(&ptr[i], num); 2094 tegra_sor_writel(sor, value, offset++); 2095 2096 num = min_t(size_t, rem - num, 3); 2097 2098 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); 2099 tegra_sor_writel(sor, value, offset++); 2100 } 2101 } 2102 2103 static int 2104 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, 2105 const struct drm_display_mode *mode) 2106 { 2107 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; 2108 struct hdmi_avi_infoframe frame; 2109 u32 value; 2110 int err; 2111 2112 /* disable AVI infoframe */ 2113 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 2114 value &= ~INFOFRAME_CTRL_SINGLE; 2115 value &= ~INFOFRAME_CTRL_OTHER; 2116 value &= ~INFOFRAME_CTRL_ENABLE; 2117 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 2118 2119 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); 2120 if (err < 0) { 2121 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 2122 return err; 2123 } 2124 2125 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 2126 if (err < 0) { 2127 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); 2128 return err; 2129 } 2130 2131 tegra_sor_hdmi_write_infopack(sor, buffer, err); 2132 2133 /* enable AVI infoframe */ 2134 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 2135 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; 2136 value |= INFOFRAME_CTRL_ENABLE; 2137 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 2138 2139 return 0; 2140 } 2141 2142 static void tegra_sor_write_eld(struct tegra_sor *sor) 2143 { 2144 size_t length = drm_eld_size(sor->output.connector.eld), i; 2145 2146 for (i = 0; i < length; i++) 2147 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i], 2148 SOR_AUDIO_HDA_ELD_BUFWR); 2149 2150 /* 2151 * The HDA codec will always report an ELD buffer size of 96 bytes and 2152 * the HDA codec driver will check that each byte read from the buffer 2153 * is valid. Therefore every byte must be written, even if no 96 bytes 2154 * were parsed from EDID. 2155 */ 2156 for (i = length; i < 96; i++) 2157 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR); 2158 } 2159 2160 static void tegra_sor_audio_prepare(struct tegra_sor *sor) 2161 { 2162 u32 value; 2163 2164 tegra_sor_write_eld(sor); 2165 2166 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD; 2167 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); 2168 } 2169 2170 static void tegra_sor_audio_unprepare(struct tegra_sor *sor) 2171 { 2172 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE); 2173 } 2174 2175 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor) 2176 { 2177 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)]; 2178 struct hdmi_audio_infoframe frame; 2179 u32 value; 2180 int err; 2181 2182 err = hdmi_audio_infoframe_init(&frame); 2183 if (err < 0) { 2184 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err); 2185 return err; 2186 } 2187 2188 frame.channels = sor->audio.channels; 2189 2190 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 2191 if (err < 0) { 2192 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err); 2193 return err; 2194 } 2195 2196 tegra_sor_hdmi_write_infopack(sor, buffer, err); 2197 2198 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2199 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; 2200 value |= INFOFRAME_CTRL_ENABLE; 2201 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2202 2203 return 0; 2204 } 2205 2206 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor) 2207 { 2208 u32 value; 2209 2210 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); 2211 2212 /* select HDA audio input */ 2213 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK); 2214 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA); 2215 2216 /* inject null samples */ 2217 if (sor->audio.channels != 2) 2218 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL; 2219 else 2220 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL; 2221 2222 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH; 2223 2224 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); 2225 2226 /* enable advertising HBR capability */ 2227 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE); 2228 2229 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL); 2230 2231 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH | 2232 SOR_HDMI_SPARE_CTS_RESET(1) | 2233 SOR_HDMI_SPARE_HW_CTS_ENABLE; 2234 tegra_sor_writel(sor, value, SOR_HDMI_SPARE); 2235 2236 /* enable HW CTS */ 2237 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0); 2238 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); 2239 2240 /* allow packet to be sent */ 2241 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE; 2242 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); 2243 2244 /* reset N counter and enable lookup */ 2245 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP; 2246 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); 2247 2248 value = (24000 * 4096) / (128 * sor->audio.sample_rate / 1000); 2249 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); 2250 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320); 2251 2252 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441); 2253 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441); 2254 2255 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882); 2256 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882); 2257 2258 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764); 2259 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764); 2260 2261 value = (24000 * 6144) / (128 * sor->audio.sample_rate / 1000); 2262 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); 2263 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480); 2264 2265 value = (24000 * 12288) / (128 * sor->audio.sample_rate / 1000); 2266 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); 2267 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960); 2268 2269 value = (24000 * 24576) / (128 * sor->audio.sample_rate / 1000); 2270 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); 2271 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920); 2272 2273 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); 2274 value &= ~SOR_HDMI_AUDIO_N_RESET; 2275 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); 2276 2277 tegra_sor_hdmi_enable_audio_infoframe(sor); 2278 } 2279 2280 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) 2281 { 2282 u32 value; 2283 2284 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2285 value &= ~INFOFRAME_CTRL_ENABLE; 2286 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2287 } 2288 2289 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor) 2290 { 2291 tegra_sor_hdmi_disable_audio_infoframe(sor); 2292 } 2293 2294 static struct tegra_sor_hdmi_settings * 2295 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) 2296 { 2297 unsigned int i; 2298 2299 for (i = 0; i < sor->num_settings; i++) 2300 if (frequency <= sor->settings[i].frequency) 2301 return &sor->settings[i]; 2302 2303 return NULL; 2304 } 2305 2306 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor) 2307 { 2308 u32 value; 2309 2310 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); 2311 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; 2312 value &= ~SOR_HDMI2_CTRL_SCRAMBLE; 2313 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); 2314 } 2315 2316 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor) 2317 { 2318 struct i2c_adapter *ddc = sor->output.ddc; 2319 2320 drm_scdc_set_high_tmds_clock_ratio(ddc, false); 2321 drm_scdc_set_scrambling(ddc, false); 2322 2323 tegra_sor_hdmi_disable_scrambling(sor); 2324 } 2325 2326 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor) 2327 { 2328 if (sor->scdc_enabled) { 2329 cancel_delayed_work_sync(&sor->scdc); 2330 tegra_sor_hdmi_scdc_disable(sor); 2331 } 2332 } 2333 2334 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor) 2335 { 2336 u32 value; 2337 2338 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); 2339 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; 2340 value |= SOR_HDMI2_CTRL_SCRAMBLE; 2341 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); 2342 } 2343 2344 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor) 2345 { 2346 struct i2c_adapter *ddc = sor->output.ddc; 2347 2348 drm_scdc_set_high_tmds_clock_ratio(ddc, true); 2349 drm_scdc_set_scrambling(ddc, true); 2350 2351 tegra_sor_hdmi_enable_scrambling(sor); 2352 } 2353 2354 static void tegra_sor_hdmi_scdc_work(struct work_struct *work) 2355 { 2356 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work); 2357 struct i2c_adapter *ddc = sor->output.ddc; 2358 2359 if (!drm_scdc_get_scrambling_status(ddc)) { 2360 DRM_DEBUG_KMS("SCDC not scrambled\n"); 2361 tegra_sor_hdmi_scdc_enable(sor); 2362 } 2363 2364 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); 2365 } 2366 2367 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor) 2368 { 2369 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; 2370 struct drm_display_mode *mode; 2371 2372 mode = &sor->output.encoder.crtc->state->adjusted_mode; 2373 2374 if (mode->clock >= 340000 && scdc->supported) { 2375 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); 2376 tegra_sor_hdmi_scdc_enable(sor); 2377 sor->scdc_enabled = true; 2378 } 2379 } 2380 2381 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) 2382 { 2383 struct tegra_output *output = encoder_to_output(encoder); 2384 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2385 struct tegra_sor *sor = to_sor(output); 2386 u32 value; 2387 int err; 2388 2389 tegra_sor_audio_unprepare(sor); 2390 tegra_sor_hdmi_scdc_stop(sor); 2391 2392 err = tegra_sor_detach(sor); 2393 if (err < 0) 2394 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 2395 2396 tegra_sor_writel(sor, 0, SOR_STATE1); 2397 tegra_sor_update(sor); 2398 2399 /* disable display to SOR clock */ 2400 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2401 2402 if (!sor->soc->has_nvdisplay) 2403 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1)); 2404 else 2405 value &= ~SOR_ENABLE(sor->index); 2406 2407 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2408 2409 tegra_dc_commit(dc); 2410 2411 err = tegra_sor_power_down(sor); 2412 if (err < 0) 2413 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 2414 2415 err = tegra_io_pad_power_disable(sor->pad); 2416 if (err < 0) 2417 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); 2418 2419 pm_runtime_put(sor->dev); 2420 } 2421 2422 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) 2423 { 2424 struct tegra_output *output = encoder_to_output(encoder); 2425 unsigned int h_ref_to_sync = 1, pulse_start, max_ac; 2426 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2427 struct tegra_sor_hdmi_settings *settings; 2428 struct tegra_sor *sor = to_sor(output); 2429 struct tegra_sor_state *state; 2430 struct drm_display_mode *mode; 2431 unsigned long rate, pclk; 2432 unsigned int div, i; 2433 u32 value; 2434 int err; 2435 2436 state = to_sor_state(output->connector.state); 2437 mode = &encoder->crtc->state->adjusted_mode; 2438 pclk = mode->clock * 1000; 2439 2440 pm_runtime_get_sync(sor->dev); 2441 2442 /* switch to safe parent clock */ 2443 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 2444 if (err < 0) { 2445 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 2446 return; 2447 } 2448 2449 div = clk_get_rate(sor->clk) / 1000000 * 4; 2450 2451 err = tegra_io_pad_power_enable(sor->pad); 2452 if (err < 0) 2453 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); 2454 2455 usleep_range(20, 100); 2456 2457 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2458 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 2459 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2460 2461 usleep_range(20, 100); 2462 2463 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 2464 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; 2465 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 2466 2467 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2468 value &= ~SOR_PLL0_VCOPD; 2469 value &= ~SOR_PLL0_PWR; 2470 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2471 2472 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2473 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 2474 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2475 2476 usleep_range(200, 400); 2477 2478 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2479 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 2480 value &= ~SOR_PLL2_PORT_POWERDOWN; 2481 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2482 2483 usleep_range(20, 100); 2484 2485 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2486 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 2487 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; 2488 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2489 2490 while (true) { 2491 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2492 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) 2493 break; 2494 2495 usleep_range(250, 1000); 2496 } 2497 2498 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 2499 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5); 2500 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 2501 2502 while (true) { 2503 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2504 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 2505 break; 2506 2507 usleep_range(250, 1000); 2508 } 2509 2510 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 2511 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 2512 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 2513 2514 if (mode->clock < 340000) { 2515 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n"); 2516 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; 2517 } else { 2518 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n"); 2519 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; 2520 } 2521 2522 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 2523 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 2524 2525 /* SOR pad PLL stabilization time */ 2526 usleep_range(250, 1000); 2527 2528 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 2529 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 2530 value |= SOR_DP_LINKCTL_LANE_COUNT(4); 2531 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 2532 2533 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2534 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; 2535 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 2536 value &= ~SOR_DP_SPARE_SEQ_ENABLE; 2537 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK; 2538 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2539 2540 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | 2541 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8); 2542 tegra_sor_writel(sor, value, SOR_SEQ_CTL); 2543 2544 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | 2545 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1); 2546 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); 2547 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); 2548 2549 if (!sor->soc->has_nvdisplay) { 2550 /* program the reference clock */ 2551 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); 2552 tegra_sor_writel(sor, value, SOR_REFCLK); 2553 } 2554 2555 /* XXX not in TRM */ 2556 for (value = 0, i = 0; i < 5; i++) 2557 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | 2558 SOR_XBAR_CTRL_LINK1_XSEL(i, i); 2559 2560 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); 2561 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 2562 2563 /* switch to parent clock */ 2564 err = clk_set_parent(sor->clk, sor->clk_parent); 2565 if (err < 0) { 2566 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 2567 return; 2568 } 2569 2570 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); 2571 if (err < 0) { 2572 dev_err(sor->dev, "failed to set pad clock: %d\n", err); 2573 return; 2574 } 2575 2576 /* adjust clock rate for HDMI 2.0 modes */ 2577 rate = clk_get_rate(sor->clk_parent); 2578 2579 if (mode->clock >= 340000) 2580 rate /= 2; 2581 2582 DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk); 2583 2584 clk_set_rate(sor->clk, rate); 2585 2586 if (!sor->soc->has_nvdisplay) { 2587 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); 2588 2589 /* XXX is this the proper check? */ 2590 if (mode->clock < 75000) 2591 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; 2592 2593 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); 2594 } 2595 2596 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32; 2597 2598 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | 2599 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY); 2600 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); 2601 2602 if (!dc->soc->has_nvdisplay) { 2603 /* H_PULSE2 setup */ 2604 pulse_start = h_ref_to_sync + 2605 (mode->hsync_end - mode->hsync_start) + 2606 (mode->htotal - mode->hsync_end) - 10; 2607 2608 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | 2609 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL; 2610 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); 2611 2612 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); 2613 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); 2614 2615 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); 2616 value |= H_PULSE2_ENABLE; 2617 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); 2618 } 2619 2620 /* infoframe setup */ 2621 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); 2622 if (err < 0) 2623 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 2624 2625 /* XXX HDMI audio support not implemented yet */ 2626 tegra_sor_hdmi_disable_audio_infoframe(sor); 2627 2628 /* use single TMDS protocol */ 2629 value = tegra_sor_readl(sor, SOR_STATE1); 2630 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2631 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; 2632 tegra_sor_writel(sor, value, SOR_STATE1); 2633 2634 /* power up pad calibration */ 2635 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2636 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 2637 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2638 2639 /* production settings */ 2640 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); 2641 if (!settings) { 2642 dev_err(sor->dev, "no settings for pixel clock %d Hz\n", 2643 mode->clock * 1000); 2644 return; 2645 } 2646 2647 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2648 value &= ~SOR_PLL0_ICHPMP_MASK; 2649 value &= ~SOR_PLL0_FILTER_MASK; 2650 value &= ~SOR_PLL0_VCOCAP_MASK; 2651 value |= SOR_PLL0_ICHPMP(settings->ichpmp); 2652 value |= SOR_PLL0_FILTER(settings->filter); 2653 value |= SOR_PLL0_VCOCAP(settings->vcocap); 2654 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2655 2656 /* XXX not in TRM */ 2657 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 2658 value &= ~SOR_PLL1_LOADADJ_MASK; 2659 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 2660 value |= SOR_PLL1_LOADADJ(settings->loadadj); 2661 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); 2662 value |= SOR_PLL1_TMDS_TERM; 2663 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 2664 2665 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 2666 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK; 2667 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; 2668 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK; 2669 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK; 2670 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); 2671 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); 2672 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); 2673 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); 2674 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 2675 2676 value = settings->drive_current[3] << 24 | 2677 settings->drive_current[2] << 16 | 2678 settings->drive_current[1] << 8 | 2679 settings->drive_current[0] << 0; 2680 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); 2681 2682 value = settings->preemphasis[3] << 24 | 2683 settings->preemphasis[2] << 16 | 2684 settings->preemphasis[1] << 8 | 2685 settings->preemphasis[0] << 0; 2686 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); 2687 2688 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2689 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 2690 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 2691 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); 2692 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2693 2694 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); 2695 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK; 2696 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); 2697 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); 2698 2699 /* power down pad calibration */ 2700 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2701 value |= SOR_DP_PADCTL_PAD_CAL_PD; 2702 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2703 2704 if (!dc->soc->has_nvdisplay) { 2705 /* miscellaneous display controller settings */ 2706 value = VSYNC_H_POSITION(1); 2707 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); 2708 } 2709 2710 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); 2711 value &= ~DITHER_CONTROL_MASK; 2712 value &= ~BASE_COLOR_SIZE_MASK; 2713 2714 switch (state->bpc) { 2715 case 6: 2716 value |= BASE_COLOR_SIZE_666; 2717 break; 2718 2719 case 8: 2720 value |= BASE_COLOR_SIZE_888; 2721 break; 2722 2723 case 10: 2724 value |= BASE_COLOR_SIZE_101010; 2725 break; 2726 2727 case 12: 2728 value |= BASE_COLOR_SIZE_121212; 2729 break; 2730 2731 default: 2732 WARN(1, "%u bits-per-color not supported\n", state->bpc); 2733 value |= BASE_COLOR_SIZE_888; 2734 break; 2735 } 2736 2737 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); 2738 2739 /* XXX set display head owner */ 2740 value = tegra_sor_readl(sor, SOR_STATE1); 2741 value &= ~SOR_STATE_ASY_OWNER_MASK; 2742 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); 2743 tegra_sor_writel(sor, value, SOR_STATE1); 2744 2745 err = tegra_sor_power_up(sor, 250); 2746 if (err < 0) 2747 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 2748 2749 /* configure dynamic range of output */ 2750 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); 2751 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; 2752 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; 2753 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); 2754 2755 /* configure colorspace */ 2756 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); 2757 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; 2758 value |= SOR_HEAD_STATE_COLORSPACE_RGB; 2759 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); 2760 2761 tegra_sor_mode_set(sor, mode, state); 2762 2763 tegra_sor_update(sor); 2764 2765 /* program preamble timing in SOR (XXX) */ 2766 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2767 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; 2768 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2769 2770 err = tegra_sor_attach(sor); 2771 if (err < 0) 2772 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 2773 2774 /* enable display to SOR clock and generate HDMI preamble */ 2775 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2776 2777 if (!sor->soc->has_nvdisplay) 2778 value |= SOR_ENABLE(1) | SOR1_TIMING_CYA; 2779 else 2780 value |= SOR_ENABLE(sor->index); 2781 2782 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2783 2784 if (dc->soc->has_nvdisplay) { 2785 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); 2786 value &= ~PROTOCOL_MASK; 2787 value |= PROTOCOL_SINGLE_TMDS_A; 2788 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); 2789 } 2790 2791 tegra_dc_commit(dc); 2792 2793 err = tegra_sor_wakeup(sor); 2794 if (err < 0) 2795 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); 2796 2797 tegra_sor_hdmi_scdc_start(sor); 2798 tegra_sor_audio_prepare(sor); 2799 } 2800 2801 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = { 2802 .disable = tegra_sor_hdmi_disable, 2803 .enable = tegra_sor_hdmi_enable, 2804 .atomic_check = tegra_sor_encoder_atomic_check, 2805 }; 2806 2807 static int tegra_sor_init(struct host1x_client *client) 2808 { 2809 struct drm_device *drm = dev_get_drvdata(client->parent); 2810 const struct drm_encoder_helper_funcs *helpers = NULL; 2811 struct tegra_sor *sor = host1x_client_to_sor(client); 2812 int connector = DRM_MODE_CONNECTOR_Unknown; 2813 int encoder = DRM_MODE_ENCODER_NONE; 2814 u32 value; 2815 int err; 2816 2817 if (!sor->aux) { 2818 if (sor->soc->supports_hdmi) { 2819 connector = DRM_MODE_CONNECTOR_HDMIA; 2820 encoder = DRM_MODE_ENCODER_TMDS; 2821 helpers = &tegra_sor_hdmi_helpers; 2822 } else if (sor->soc->supports_lvds) { 2823 connector = DRM_MODE_CONNECTOR_LVDS; 2824 encoder = DRM_MODE_ENCODER_LVDS; 2825 } 2826 } else { 2827 if (sor->soc->supports_edp) { 2828 connector = DRM_MODE_CONNECTOR_eDP; 2829 encoder = DRM_MODE_ENCODER_TMDS; 2830 helpers = &tegra_sor_edp_helpers; 2831 } else if (sor->soc->supports_dp) { 2832 connector = DRM_MODE_CONNECTOR_DisplayPort; 2833 encoder = DRM_MODE_ENCODER_TMDS; 2834 } 2835 } 2836 2837 sor->output.dev = sor->dev; 2838 2839 drm_connector_init(drm, &sor->output.connector, 2840 &tegra_sor_connector_funcs, 2841 connector); 2842 drm_connector_helper_add(&sor->output.connector, 2843 &tegra_sor_connector_helper_funcs); 2844 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; 2845 2846 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs, 2847 encoder, NULL); 2848 drm_encoder_helper_add(&sor->output.encoder, helpers); 2849 2850 drm_connector_attach_encoder(&sor->output.connector, 2851 &sor->output.encoder); 2852 drm_connector_register(&sor->output.connector); 2853 2854 err = tegra_output_init(drm, &sor->output); 2855 if (err < 0) { 2856 dev_err(client->dev, "failed to initialize output: %d\n", err); 2857 return err; 2858 } 2859 2860 tegra_output_find_possible_crtcs(&sor->output, drm); 2861 2862 if (sor->aux) { 2863 err = drm_dp_aux_attach(sor->aux, &sor->output); 2864 if (err < 0) { 2865 dev_err(sor->dev, "failed to attach DP: %d\n", err); 2866 return err; 2867 } 2868 } 2869 2870 /* 2871 * XXX: Remove this reset once proper hand-over from firmware to 2872 * kernel is possible. 2873 */ 2874 if (sor->rst) { 2875 err = reset_control_assert(sor->rst); 2876 if (err < 0) { 2877 dev_err(sor->dev, "failed to assert SOR reset: %d\n", 2878 err); 2879 return err; 2880 } 2881 } 2882 2883 err = clk_prepare_enable(sor->clk); 2884 if (err < 0) { 2885 dev_err(sor->dev, "failed to enable clock: %d\n", err); 2886 return err; 2887 } 2888 2889 usleep_range(1000, 3000); 2890 2891 if (sor->rst) { 2892 err = reset_control_deassert(sor->rst); 2893 if (err < 0) { 2894 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", 2895 err); 2896 return err; 2897 } 2898 } 2899 2900 err = clk_prepare_enable(sor->clk_safe); 2901 if (err < 0) 2902 return err; 2903 2904 err = clk_prepare_enable(sor->clk_dp); 2905 if (err < 0) 2906 return err; 2907 2908 /* 2909 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This 2910 * is used for interoperability between the HDA codec driver and the 2911 * HDMI/DP driver. 2912 */ 2913 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0; 2914 tegra_sor_writel(sor, value, SOR_INT_ENABLE); 2915 tegra_sor_writel(sor, value, SOR_INT_MASK); 2916 2917 return 0; 2918 } 2919 2920 static int tegra_sor_exit(struct host1x_client *client) 2921 { 2922 struct tegra_sor *sor = host1x_client_to_sor(client); 2923 int err; 2924 2925 tegra_sor_writel(sor, 0, SOR_INT_MASK); 2926 tegra_sor_writel(sor, 0, SOR_INT_ENABLE); 2927 2928 tegra_output_exit(&sor->output); 2929 2930 if (sor->aux) { 2931 err = drm_dp_aux_detach(sor->aux); 2932 if (err < 0) { 2933 dev_err(sor->dev, "failed to detach DP: %d\n", err); 2934 return err; 2935 } 2936 } 2937 2938 clk_disable_unprepare(sor->clk_safe); 2939 clk_disable_unprepare(sor->clk_dp); 2940 clk_disable_unprepare(sor->clk); 2941 2942 return 0; 2943 } 2944 2945 static const struct host1x_client_ops sor_client_ops = { 2946 .init = tegra_sor_init, 2947 .exit = tegra_sor_exit, 2948 }; 2949 2950 static const struct tegra_sor_ops tegra_sor_edp_ops = { 2951 .name = "eDP", 2952 }; 2953 2954 static int tegra_sor_hdmi_probe(struct tegra_sor *sor) 2955 { 2956 int err; 2957 2958 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io"); 2959 if (IS_ERR(sor->avdd_io_supply)) { 2960 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n", 2961 PTR_ERR(sor->avdd_io_supply)); 2962 return PTR_ERR(sor->avdd_io_supply); 2963 } 2964 2965 err = regulator_enable(sor->avdd_io_supply); 2966 if (err < 0) { 2967 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", 2968 err); 2969 return err; 2970 } 2971 2972 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll"); 2973 if (IS_ERR(sor->vdd_pll_supply)) { 2974 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n", 2975 PTR_ERR(sor->vdd_pll_supply)); 2976 return PTR_ERR(sor->vdd_pll_supply); 2977 } 2978 2979 err = regulator_enable(sor->vdd_pll_supply); 2980 if (err < 0) { 2981 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", 2982 err); 2983 return err; 2984 } 2985 2986 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); 2987 if (IS_ERR(sor->hdmi_supply)) { 2988 dev_err(sor->dev, "cannot get HDMI supply: %ld\n", 2989 PTR_ERR(sor->hdmi_supply)); 2990 return PTR_ERR(sor->hdmi_supply); 2991 } 2992 2993 err = regulator_enable(sor->hdmi_supply); 2994 if (err < 0) { 2995 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); 2996 return err; 2997 } 2998 2999 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); 3000 3001 return 0; 3002 } 3003 3004 static int tegra_sor_hdmi_remove(struct tegra_sor *sor) 3005 { 3006 regulator_disable(sor->hdmi_supply); 3007 regulator_disable(sor->vdd_pll_supply); 3008 regulator_disable(sor->avdd_io_supply); 3009 3010 return 0; 3011 } 3012 3013 static const struct tegra_sor_ops tegra_sor_hdmi_ops = { 3014 .name = "HDMI", 3015 .probe = tegra_sor_hdmi_probe, 3016 .remove = tegra_sor_hdmi_remove, 3017 }; 3018 3019 static const u8 tegra124_sor_xbar_cfg[5] = { 3020 0, 1, 2, 3, 4 3021 }; 3022 3023 static const struct tegra_sor_regs tegra124_sor_regs = { 3024 .head_state0 = 0x05, 3025 .head_state1 = 0x07, 3026 .head_state2 = 0x09, 3027 .head_state3 = 0x0b, 3028 .head_state4 = 0x0d, 3029 .head_state5 = 0x0f, 3030 .pll0 = 0x17, 3031 .pll1 = 0x18, 3032 .pll2 = 0x19, 3033 .pll3 = 0x1a, 3034 .dp_padctl0 = 0x5c, 3035 .dp_padctl2 = 0x73, 3036 }; 3037 3038 static const struct tegra_sor_soc tegra124_sor = { 3039 .supports_edp = true, 3040 .supports_lvds = true, 3041 .supports_hdmi = false, 3042 .supports_dp = false, 3043 .regs = &tegra124_sor_regs, 3044 .has_nvdisplay = false, 3045 .xbar_cfg = tegra124_sor_xbar_cfg, 3046 }; 3047 3048 static const struct tegra_sor_regs tegra210_sor_regs = { 3049 .head_state0 = 0x05, 3050 .head_state1 = 0x07, 3051 .head_state2 = 0x09, 3052 .head_state3 = 0x0b, 3053 .head_state4 = 0x0d, 3054 .head_state5 = 0x0f, 3055 .pll0 = 0x17, 3056 .pll1 = 0x18, 3057 .pll2 = 0x19, 3058 .pll3 = 0x1a, 3059 .dp_padctl0 = 0x5c, 3060 .dp_padctl2 = 0x73, 3061 }; 3062 3063 static const struct tegra_sor_soc tegra210_sor = { 3064 .supports_edp = true, 3065 .supports_lvds = false, 3066 .supports_hdmi = false, 3067 .supports_dp = false, 3068 .regs = &tegra210_sor_regs, 3069 .has_nvdisplay = false, 3070 .xbar_cfg = tegra124_sor_xbar_cfg, 3071 }; 3072 3073 static const u8 tegra210_sor_xbar_cfg[5] = { 3074 2, 1, 0, 3, 4 3075 }; 3076 3077 static const struct tegra_sor_soc tegra210_sor1 = { 3078 .supports_edp = false, 3079 .supports_lvds = false, 3080 .supports_hdmi = true, 3081 .supports_dp = true, 3082 3083 .regs = &tegra210_sor_regs, 3084 .has_nvdisplay = false, 3085 3086 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults), 3087 .settings = tegra210_sor_hdmi_defaults, 3088 3089 .xbar_cfg = tegra210_sor_xbar_cfg, 3090 }; 3091 3092 static const struct tegra_sor_regs tegra186_sor_regs = { 3093 .head_state0 = 0x151, 3094 .head_state1 = 0x154, 3095 .head_state2 = 0x157, 3096 .head_state3 = 0x15a, 3097 .head_state4 = 0x15d, 3098 .head_state5 = 0x160, 3099 .pll0 = 0x163, 3100 .pll1 = 0x164, 3101 .pll2 = 0x165, 3102 .pll3 = 0x166, 3103 .dp_padctl0 = 0x168, 3104 .dp_padctl2 = 0x16a, 3105 }; 3106 3107 static const struct tegra_sor_soc tegra186_sor = { 3108 .supports_edp = false, 3109 .supports_lvds = false, 3110 .supports_hdmi = false, 3111 .supports_dp = true, 3112 3113 .regs = &tegra186_sor_regs, 3114 .has_nvdisplay = true, 3115 3116 .xbar_cfg = tegra124_sor_xbar_cfg, 3117 }; 3118 3119 static const struct tegra_sor_soc tegra186_sor1 = { 3120 .supports_edp = false, 3121 .supports_lvds = false, 3122 .supports_hdmi = true, 3123 .supports_dp = true, 3124 3125 .regs = &tegra186_sor_regs, 3126 .has_nvdisplay = true, 3127 3128 .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults), 3129 .settings = tegra186_sor_hdmi_defaults, 3130 3131 .xbar_cfg = tegra124_sor_xbar_cfg, 3132 }; 3133 3134 static const struct tegra_sor_regs tegra194_sor_regs = { 3135 .head_state0 = 0x151, 3136 .head_state1 = 0x155, 3137 .head_state2 = 0x159, 3138 .head_state3 = 0x15d, 3139 .head_state4 = 0x161, 3140 .head_state5 = 0x165, 3141 .pll0 = 0x169, 3142 .pll1 = 0x16a, 3143 .pll2 = 0x16b, 3144 .pll3 = 0x16c, 3145 .dp_padctl0 = 0x16e, 3146 .dp_padctl2 = 0x16f, 3147 }; 3148 3149 static const struct tegra_sor_soc tegra194_sor = { 3150 .supports_edp = true, 3151 .supports_lvds = false, 3152 .supports_hdmi = true, 3153 .supports_dp = true, 3154 3155 .regs = &tegra194_sor_regs, 3156 .has_nvdisplay = true, 3157 3158 .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults), 3159 .settings = tegra194_sor_hdmi_defaults, 3160 3161 .xbar_cfg = tegra210_sor_xbar_cfg, 3162 }; 3163 3164 static const struct of_device_id tegra_sor_of_match[] = { 3165 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor }, 3166 { .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 }, 3167 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor }, 3168 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 }, 3169 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor }, 3170 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor }, 3171 { }, 3172 }; 3173 MODULE_DEVICE_TABLE(of, tegra_sor_of_match); 3174 3175 static int tegra_sor_parse_dt(struct tegra_sor *sor) 3176 { 3177 struct device_node *np = sor->dev->of_node; 3178 u32 value; 3179 int err; 3180 3181 if (sor->soc->has_nvdisplay) { 3182 err = of_property_read_u32(np, "nvidia,interface", &value); 3183 if (err < 0) 3184 return err; 3185 3186 sor->index = value; 3187 3188 /* 3189 * override the default that we already set for Tegra210 and 3190 * earlier 3191 */ 3192 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; 3193 } 3194 3195 return 0; 3196 } 3197 3198 static void tegra_hda_parse_format(unsigned int format, unsigned int *rate, 3199 unsigned int *channels) 3200 { 3201 unsigned int mul, div; 3202 3203 if (format & AC_FMT_BASE_44K) 3204 *rate = 44100; 3205 else 3206 *rate = 48000; 3207 3208 mul = (format & AC_FMT_MULT_MASK) >> AC_FMT_MULT_SHIFT; 3209 div = (format & AC_FMT_DIV_MASK) >> AC_FMT_DIV_SHIFT; 3210 3211 *rate = *rate * (mul + 1) / (div + 1); 3212 3213 *channels = (format & AC_FMT_CHAN_MASK) >> AC_FMT_CHAN_SHIFT; 3214 } 3215 3216 static irqreturn_t tegra_sor_irq(int irq, void *data) 3217 { 3218 struct tegra_sor *sor = data; 3219 u32 value; 3220 3221 value = tegra_sor_readl(sor, SOR_INT_STATUS); 3222 tegra_sor_writel(sor, value, SOR_INT_STATUS); 3223 3224 if (value & SOR_INT_CODEC_SCRATCH0) { 3225 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); 3226 3227 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) { 3228 unsigned int format, sample_rate, channels; 3229 3230 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK; 3231 3232 tegra_hda_parse_format(format, &sample_rate, &channels); 3233 3234 sor->audio.sample_rate = sample_rate; 3235 sor->audio.channels = channels; 3236 3237 tegra_sor_hdmi_audio_enable(sor); 3238 } else { 3239 tegra_sor_hdmi_audio_disable(sor); 3240 } 3241 } 3242 3243 return IRQ_HANDLED; 3244 } 3245 3246 static int tegra_sor_probe(struct platform_device *pdev) 3247 { 3248 struct device_node *np; 3249 struct tegra_sor *sor; 3250 struct resource *regs; 3251 int err; 3252 3253 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); 3254 if (!sor) 3255 return -ENOMEM; 3256 3257 sor->soc = of_device_get_match_data(&pdev->dev); 3258 sor->output.dev = sor->dev = &pdev->dev; 3259 3260 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, 3261 sor->soc->num_settings * 3262 sizeof(*sor->settings), 3263 GFP_KERNEL); 3264 if (!sor->settings) 3265 return -ENOMEM; 3266 3267 sor->num_settings = sor->soc->num_settings; 3268 3269 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); 3270 if (np) { 3271 sor->aux = drm_dp_aux_find_by_of_node(np); 3272 of_node_put(np); 3273 3274 if (!sor->aux) 3275 return -EPROBE_DEFER; 3276 } 3277 3278 if (!sor->aux) { 3279 if (sor->soc->supports_hdmi) { 3280 sor->ops = &tegra_sor_hdmi_ops; 3281 sor->pad = TEGRA_IO_PAD_HDMI; 3282 } else if (sor->soc->supports_lvds) { 3283 dev_err(&pdev->dev, "LVDS not supported yet\n"); 3284 return -ENODEV; 3285 } else { 3286 dev_err(&pdev->dev, "unknown (non-DP) support\n"); 3287 return -ENODEV; 3288 } 3289 } else { 3290 if (sor->soc->supports_edp) { 3291 sor->ops = &tegra_sor_edp_ops; 3292 sor->pad = TEGRA_IO_PAD_LVDS; 3293 } else if (sor->soc->supports_dp) { 3294 dev_err(&pdev->dev, "DisplayPort not supported yet\n"); 3295 return -ENODEV; 3296 } else { 3297 dev_err(&pdev->dev, "unknown (DP) support\n"); 3298 return -ENODEV; 3299 } 3300 } 3301 3302 err = tegra_sor_parse_dt(sor); 3303 if (err < 0) 3304 return err; 3305 3306 err = tegra_output_probe(&sor->output); 3307 if (err < 0) { 3308 dev_err(&pdev->dev, "failed to probe output: %d\n", err); 3309 return err; 3310 } 3311 3312 if (sor->ops && sor->ops->probe) { 3313 err = sor->ops->probe(sor); 3314 if (err < 0) { 3315 dev_err(&pdev->dev, "failed to probe %s: %d\n", 3316 sor->ops->name, err); 3317 goto output; 3318 } 3319 } 3320 3321 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3322 sor->regs = devm_ioremap_resource(&pdev->dev, regs); 3323 if (IS_ERR(sor->regs)) { 3324 err = PTR_ERR(sor->regs); 3325 goto remove; 3326 } 3327 3328 err = platform_get_irq(pdev, 0); 3329 if (err < 0) { 3330 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err); 3331 goto remove; 3332 } 3333 3334 sor->irq = err; 3335 3336 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0, 3337 dev_name(sor->dev), sor); 3338 if (err < 0) { 3339 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); 3340 goto remove; 3341 } 3342 3343 sor->rst = devm_reset_control_get(&pdev->dev, "sor"); 3344 if (IS_ERR(sor->rst)) { 3345 err = PTR_ERR(sor->rst); 3346 3347 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) { 3348 dev_err(&pdev->dev, "failed to get reset control: %d\n", 3349 err); 3350 goto remove; 3351 } 3352 3353 /* 3354 * At this point, the reset control is most likely being used 3355 * by the generic power domain implementation. With any luck 3356 * the power domain will have taken care of resetting the SOR 3357 * and we don't have to do anything. 3358 */ 3359 sor->rst = NULL; 3360 } 3361 3362 sor->clk = devm_clk_get(&pdev->dev, NULL); 3363 if (IS_ERR(sor->clk)) { 3364 err = PTR_ERR(sor->clk); 3365 dev_err(&pdev->dev, "failed to get module clock: %d\n", err); 3366 goto remove; 3367 } 3368 3369 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { 3370 struct device_node *np = pdev->dev.of_node; 3371 const char *name; 3372 3373 /* 3374 * For backwards compatibility with Tegra210 device trees, 3375 * fall back to the old clock name "source" if the new "out" 3376 * clock is not available. 3377 */ 3378 if (of_property_match_string(np, "clock-names", "out") < 0) 3379 name = "source"; 3380 else 3381 name = "out"; 3382 3383 sor->clk_out = devm_clk_get(&pdev->dev, name); 3384 if (IS_ERR(sor->clk_out)) { 3385 err = PTR_ERR(sor->clk_out); 3386 dev_err(sor->dev, "failed to get %s clock: %d\n", 3387 name, err); 3388 goto remove; 3389 } 3390 } else { 3391 /* fall back to the module clock on SOR0 (eDP/LVDS only) */ 3392 sor->clk_out = sor->clk; 3393 } 3394 3395 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); 3396 if (IS_ERR(sor->clk_parent)) { 3397 err = PTR_ERR(sor->clk_parent); 3398 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err); 3399 goto remove; 3400 } 3401 3402 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); 3403 if (IS_ERR(sor->clk_safe)) { 3404 err = PTR_ERR(sor->clk_safe); 3405 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err); 3406 goto remove; 3407 } 3408 3409 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); 3410 if (IS_ERR(sor->clk_dp)) { 3411 err = PTR_ERR(sor->clk_dp); 3412 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err); 3413 goto remove; 3414 } 3415 3416 /* 3417 * Starting with Tegra186, the BPMP provides an implementation for 3418 * the pad output clock, so we have to look it up from device tree. 3419 */ 3420 sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); 3421 if (IS_ERR(sor->clk_pad)) { 3422 if (sor->clk_pad != ERR_PTR(-ENOENT)) { 3423 err = PTR_ERR(sor->clk_pad); 3424 goto remove; 3425 } 3426 3427 /* 3428 * If the pad output clock is not available, then we assume 3429 * we're on Tegra210 or earlier and have to provide our own 3430 * implementation. 3431 */ 3432 sor->clk_pad = NULL; 3433 } 3434 3435 /* 3436 * The bootloader may have set up the SOR such that it's module clock 3437 * is sourced by one of the display PLLs. However, that doesn't work 3438 * without properly having set up other bits of the SOR. 3439 */ 3440 err = clk_set_parent(sor->clk_out, sor->clk_safe); 3441 if (err < 0) { 3442 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err); 3443 goto remove; 3444 } 3445 3446 platform_set_drvdata(pdev, sor); 3447 pm_runtime_enable(&pdev->dev); 3448 3449 /* 3450 * On Tegra210 and earlier, provide our own implementation for the 3451 * pad output clock. 3452 */ 3453 if (!sor->clk_pad) { 3454 err = pm_runtime_get_sync(&pdev->dev); 3455 if (err < 0) { 3456 dev_err(&pdev->dev, "failed to get runtime PM: %d\n", 3457 err); 3458 goto remove; 3459 } 3460 3461 sor->clk_pad = tegra_clk_sor_pad_register(sor, 3462 "sor1_pad_clkout"); 3463 pm_runtime_put(&pdev->dev); 3464 } 3465 3466 if (IS_ERR(sor->clk_pad)) { 3467 err = PTR_ERR(sor->clk_pad); 3468 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n", 3469 err); 3470 goto remove; 3471 } 3472 3473 INIT_LIST_HEAD(&sor->client.list); 3474 sor->client.ops = &sor_client_ops; 3475 sor->client.dev = &pdev->dev; 3476 3477 err = host1x_client_register(&sor->client); 3478 if (err < 0) { 3479 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 3480 err); 3481 goto remove; 3482 } 3483 3484 return 0; 3485 3486 remove: 3487 if (sor->ops && sor->ops->remove) 3488 sor->ops->remove(sor); 3489 output: 3490 tegra_output_remove(&sor->output); 3491 return err; 3492 } 3493 3494 static int tegra_sor_remove(struct platform_device *pdev) 3495 { 3496 struct tegra_sor *sor = platform_get_drvdata(pdev); 3497 int err; 3498 3499 pm_runtime_disable(&pdev->dev); 3500 3501 err = host1x_client_unregister(&sor->client); 3502 if (err < 0) { 3503 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 3504 err); 3505 return err; 3506 } 3507 3508 if (sor->ops && sor->ops->remove) { 3509 err = sor->ops->remove(sor); 3510 if (err < 0) 3511 dev_err(&pdev->dev, "failed to remove SOR: %d\n", err); 3512 } 3513 3514 tegra_output_remove(&sor->output); 3515 3516 return 0; 3517 } 3518 3519 #ifdef CONFIG_PM 3520 static int tegra_sor_suspend(struct device *dev) 3521 { 3522 struct tegra_sor *sor = dev_get_drvdata(dev); 3523 int err; 3524 3525 if (sor->rst) { 3526 err = reset_control_assert(sor->rst); 3527 if (err < 0) { 3528 dev_err(dev, "failed to assert reset: %d\n", err); 3529 return err; 3530 } 3531 } 3532 3533 usleep_range(1000, 2000); 3534 3535 clk_disable_unprepare(sor->clk); 3536 3537 return 0; 3538 } 3539 3540 static int tegra_sor_resume(struct device *dev) 3541 { 3542 struct tegra_sor *sor = dev_get_drvdata(dev); 3543 int err; 3544 3545 err = clk_prepare_enable(sor->clk); 3546 if (err < 0) { 3547 dev_err(dev, "failed to enable clock: %d\n", err); 3548 return err; 3549 } 3550 3551 usleep_range(1000, 2000); 3552 3553 if (sor->rst) { 3554 err = reset_control_deassert(sor->rst); 3555 if (err < 0) { 3556 dev_err(dev, "failed to deassert reset: %d\n", err); 3557 clk_disable_unprepare(sor->clk); 3558 return err; 3559 } 3560 } 3561 3562 return 0; 3563 } 3564 #endif 3565 3566 static const struct dev_pm_ops tegra_sor_pm_ops = { 3567 SET_RUNTIME_PM_OPS(tegra_sor_suspend, tegra_sor_resume, NULL) 3568 }; 3569 3570 struct platform_driver tegra_sor_driver = { 3571 .driver = { 3572 .name = "tegra-sor", 3573 .of_match_table = tegra_sor_of_match, 3574 .pm = &tegra_sor_pm_ops, 3575 }, 3576 .probe = tegra_sor_probe, 3577 .remove = tegra_sor_remove, 3578 }; 3579