1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022, NVIDIA Corporation. 4 */ 5 6 #ifndef DRM_TEGRA_RISCV_H 7 #define DRM_TEGRA_RISCV_H 8 9 struct tegra_drm_riscv_descriptor { 10 u32 manifest_offset; 11 u32 code_offset; 12 u32 code_size; 13 u32 data_offset; 14 u32 data_size; 15 }; 16 17 struct tegra_drm_riscv { 18 /* User initializes */ 19 struct device *dev; 20 void __iomem *regs; 21 22 struct tegra_drm_riscv_descriptor bl_desc; 23 struct tegra_drm_riscv_descriptor os_desc; 24 }; 25 26 int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv); 27 int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address, 28 u32 gscid, const struct tegra_drm_riscv_descriptor *desc); 29 30 #endif 31