1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Avionic Design GmbH 4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/of.h> 9 10 #include <drm/drm_atomic_helper.h> 11 #include <drm/drm_bridge_connector.h> 12 #include <drm/drm_simple_kms_helper.h> 13 14 #include "drm.h" 15 #include "dc.h" 16 17 struct tegra_rgb { 18 struct tegra_output output; 19 struct tegra_dc *dc; 20 21 struct clk *pll_d_out0; 22 struct clk *pll_d2_out0; 23 struct clk *clk_parent; 24 struct clk *clk; 25 }; 26 27 static inline struct tegra_rgb *to_rgb(struct tegra_output *output) 28 { 29 return container_of(output, struct tegra_rgb, output); 30 } 31 32 struct reg_entry { 33 unsigned long offset; 34 unsigned long value; 35 }; 36 37 static const struct reg_entry rgb_enable[] = { 38 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 }, 39 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 }, 40 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 }, 41 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 }, 42 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 }, 43 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 }, 44 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 }, 45 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 }, 46 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 }, 47 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 }, 48 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 }, 49 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 }, 50 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 }, 51 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 }, 52 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 }, 53 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 }, 54 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 }, 55 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 }, 56 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 }, 57 }; 58 59 static const struct reg_entry rgb_disable[] = { 60 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 }, 61 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 }, 62 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 }, 63 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 }, 64 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 }, 65 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 }, 66 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 }, 67 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa }, 68 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa }, 69 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa }, 70 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa }, 71 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 }, 72 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 }, 73 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 }, 74 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 }, 75 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 }, 76 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 }, 77 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 }, 78 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 }, 79 }; 80 81 static void tegra_dc_write_regs(struct tegra_dc *dc, 82 const struct reg_entry *table, 83 unsigned int num) 84 { 85 unsigned int i; 86 87 for (i = 0; i < num; i++) 88 tegra_dc_writel(dc, table[i].value, table[i].offset); 89 } 90 91 static void tegra_rgb_encoder_disable(struct drm_encoder *encoder) 92 { 93 struct tegra_output *output = encoder_to_output(encoder); 94 struct tegra_rgb *rgb = to_rgb(output); 95 96 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable)); 97 tegra_dc_commit(rgb->dc); 98 } 99 100 static void tegra_rgb_encoder_enable(struct drm_encoder *encoder) 101 { 102 struct tegra_output *output = encoder_to_output(encoder); 103 struct tegra_rgb *rgb = to_rgb(output); 104 u32 value; 105 106 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable)); 107 108 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL; 109 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); 110 111 /* XXX: parameterize? */ 112 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); 113 value &= ~LVS_OUTPUT_POLARITY_LOW; 114 value &= ~LHS_OUTPUT_POLARITY_LOW; 115 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); 116 117 /* XXX: parameterize? */ 118 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB | 119 DISP_ORDER_RED_BLUE; 120 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL); 121 122 tegra_dc_commit(rgb->dc); 123 } 124 125 static bool tegra_rgb_pll_rate_change_allowed(struct tegra_rgb *rgb) 126 { 127 if (!rgb->pll_d2_out0) 128 return false; 129 130 if (!clk_is_match(rgb->clk_parent, rgb->pll_d_out0) && 131 !clk_is_match(rgb->clk_parent, rgb->pll_d2_out0)) 132 return false; 133 134 return true; 135 } 136 137 static int 138 tegra_rgb_encoder_atomic_check(struct drm_encoder *encoder, 139 struct drm_crtc_state *crtc_state, 140 struct drm_connector_state *conn_state) 141 { 142 struct tegra_output *output = encoder_to_output(encoder); 143 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 144 unsigned long pclk = crtc_state->mode.clock * 1000; 145 struct tegra_rgb *rgb = to_rgb(output); 146 unsigned int div; 147 int err; 148 149 /* 150 * We may not want to change the frequency of the parent clock, since 151 * it may be a parent for other peripherals. This is due to the fact 152 * that on Tegra20 there's only a single clock dedicated to display 153 * (pll_d_out0), whereas later generations have a second one that can 154 * be used to independently drive a second output (pll_d2_out0). 155 * 156 * As a way to support multiple outputs on Tegra20 as well, pll_p is 157 * typically used as the parent clock for the display controllers. 158 * But this comes at a cost: pll_p is the parent of several other 159 * peripherals, so its frequency shouldn't change out of the blue. 160 * 161 * The best we can do at this point is to use the shift clock divider 162 * and hope that the desired frequency can be matched (or at least 163 * matched sufficiently close that the panel will still work). 164 */ 165 if (tegra_rgb_pll_rate_change_allowed(rgb)) { 166 /* 167 * Set display controller clock to x2 of PCLK in order to 168 * produce higher resolution pulse positions. 169 */ 170 div = 2; 171 pclk *= 2; 172 } else { 173 div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2; 174 pclk = 0; 175 } 176 177 err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent, 178 pclk, div); 179 if (err < 0) { 180 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 181 return err; 182 } 183 184 return err; 185 } 186 187 static const struct drm_encoder_helper_funcs tegra_rgb_encoder_helper_funcs = { 188 .disable = tegra_rgb_encoder_disable, 189 .enable = tegra_rgb_encoder_enable, 190 .atomic_check = tegra_rgb_encoder_atomic_check, 191 }; 192 193 int tegra_dc_rgb_probe(struct tegra_dc *dc) 194 { 195 struct device_node *np; 196 struct tegra_rgb *rgb; 197 int err; 198 199 np = of_get_child_by_name(dc->dev->of_node, "rgb"); 200 if (!np || !of_device_is_available(np)) 201 return -ENODEV; 202 203 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL); 204 if (!rgb) 205 return -ENOMEM; 206 207 rgb->output.dev = dc->dev; 208 rgb->output.of_node = np; 209 rgb->dc = dc; 210 211 err = tegra_output_probe(&rgb->output); 212 if (err < 0) 213 return err; 214 215 rgb->clk = devm_clk_get(dc->dev, NULL); 216 if (IS_ERR(rgb->clk)) { 217 dev_err(dc->dev, "failed to get clock\n"); 218 return PTR_ERR(rgb->clk); 219 } 220 221 rgb->clk_parent = devm_clk_get(dc->dev, "parent"); 222 if (IS_ERR(rgb->clk_parent)) { 223 dev_err(dc->dev, "failed to get parent clock\n"); 224 return PTR_ERR(rgb->clk_parent); 225 } 226 227 err = clk_set_parent(rgb->clk, rgb->clk_parent); 228 if (err < 0) { 229 dev_err(dc->dev, "failed to set parent clock: %d\n", err); 230 return err; 231 } 232 233 rgb->pll_d_out0 = clk_get_sys(NULL, "pll_d_out0"); 234 if (IS_ERR(rgb->pll_d_out0)) { 235 err = PTR_ERR(rgb->pll_d_out0); 236 dev_err(dc->dev, "failed to get pll_d_out0: %d\n", err); 237 return err; 238 } 239 240 if (dc->soc->has_pll_d2_out0) { 241 rgb->pll_d2_out0 = clk_get_sys(NULL, "pll_d2_out0"); 242 if (IS_ERR(rgb->pll_d2_out0)) { 243 err = PTR_ERR(rgb->pll_d2_out0); 244 dev_err(dc->dev, "failed to get pll_d2_out0: %d\n", err); 245 return err; 246 } 247 } 248 249 dc->rgb = &rgb->output; 250 251 return 0; 252 } 253 254 void tegra_dc_rgb_remove(struct tegra_dc *dc) 255 { 256 struct tegra_rgb *rgb; 257 258 if (!dc->rgb) 259 return; 260 261 rgb = to_rgb(dc->rgb); 262 clk_put(rgb->pll_d2_out0); 263 clk_put(rgb->pll_d_out0); 264 265 tegra_output_remove(dc->rgb); 266 dc->rgb = NULL; 267 } 268 269 int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc) 270 { 271 struct tegra_output *output = dc->rgb; 272 struct drm_connector *connector; 273 int err; 274 275 if (!dc->rgb) 276 return -ENODEV; 277 278 drm_simple_encoder_init(drm, &output->encoder, DRM_MODE_ENCODER_LVDS); 279 drm_encoder_helper_add(&output->encoder, 280 &tegra_rgb_encoder_helper_funcs); 281 282 /* 283 * Wrap directly-connected panel into DRM bridge in order to let 284 * DRM core to handle panel for us. 285 */ 286 if (output->panel) { 287 output->bridge = devm_drm_panel_bridge_add(output->dev, 288 output->panel); 289 if (IS_ERR(output->bridge)) { 290 dev_err(output->dev, 291 "failed to wrap panel into bridge: %pe\n", 292 output->bridge); 293 return PTR_ERR(output->bridge); 294 } 295 296 output->panel = NULL; 297 } 298 299 /* 300 * Tegra devices that have LVDS panel utilize LVDS encoder bridge 301 * for converting up to 28 LCD LVTTL lanes into 5/4 LVDS lanes that 302 * go to display panel's receiver. 303 * 304 * Encoder usually have a power-down control which needs to be enabled 305 * in order to transmit data to the panel. Historically devices that 306 * use an older device-tree version didn't model the bridge, assuming 307 * that encoder is turned ON by default, while today's DRM allows us 308 * to model LVDS encoder properly. 309 * 310 * Newer device-trees utilize LVDS encoder bridge, which provides 311 * us with a connector and handles the display panel. 312 * 313 * For older device-trees we wrapped panel into the panel-bridge. 314 */ 315 if (output->bridge) { 316 err = drm_bridge_attach(&output->encoder, output->bridge, 317 NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); 318 if (err) 319 return err; 320 321 connector = drm_bridge_connector_init(drm, &output->encoder); 322 if (IS_ERR(connector)) { 323 dev_err(output->dev, 324 "failed to initialize bridge connector: %pe\n", 325 connector); 326 return PTR_ERR(connector); 327 } 328 329 drm_connector_attach_encoder(connector, &output->encoder); 330 } 331 332 err = tegra_output_init(drm, output); 333 if (err < 0) { 334 dev_err(output->dev, "failed to initialize output: %d\n", err); 335 return err; 336 } 337 338 /* 339 * Other outputs can be attached to either display controller. The RGB 340 * outputs are an exception and work only with their parent display 341 * controller. 342 */ 343 output->encoder.possible_crtcs = drm_crtc_mask(&dc->base); 344 345 return 0; 346 } 347 348 int tegra_dc_rgb_exit(struct tegra_dc *dc) 349 { 350 if (dc->rgb) 351 tegra_output_exit(dc->rgb); 352 353 return 0; 354 } 355