1 /* 2 * Copyright (C) 2012 Avionic Design GmbH 3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #include <linux/clk.h> 11 12 #include "drm.h" 13 #include "dc.h" 14 15 struct tegra_rgb { 16 struct tegra_output output; 17 struct clk *clk_parent; 18 struct clk *clk; 19 }; 20 21 static inline struct tegra_rgb *to_rgb(struct tegra_output *output) 22 { 23 return container_of(output, struct tegra_rgb, output); 24 } 25 26 struct reg_entry { 27 unsigned long offset; 28 unsigned long value; 29 }; 30 31 static const struct reg_entry rgb_enable[] = { 32 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 }, 33 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 }, 34 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 }, 35 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 }, 36 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 }, 37 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 }, 38 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 }, 39 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 }, 40 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 }, 41 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 }, 42 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 }, 43 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 }, 44 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 }, 45 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 }, 46 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 }, 47 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 }, 48 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 }, 49 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 }, 50 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 }, 51 }; 52 53 static const struct reg_entry rgb_disable[] = { 54 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 }, 55 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 }, 56 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 }, 57 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 }, 58 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 }, 59 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 }, 60 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 }, 61 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa }, 62 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa }, 63 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa }, 64 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa }, 65 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 }, 66 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 }, 67 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 }, 68 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 }, 69 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 }, 70 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 }, 71 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 }, 72 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 }, 73 }; 74 75 static void tegra_dc_write_regs(struct tegra_dc *dc, 76 const struct reg_entry *table, 77 unsigned int num) 78 { 79 unsigned int i; 80 81 for (i = 0; i < num; i++) 82 tegra_dc_writel(dc, table[i].value, table[i].offset); 83 } 84 85 static int tegra_output_rgb_enable(struct tegra_output *output) 86 { 87 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); 88 89 tegra_dc_write_regs(dc, rgb_enable, ARRAY_SIZE(rgb_enable)); 90 91 return 0; 92 } 93 94 static int tegra_output_rgb_disable(struct tegra_output *output) 95 { 96 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); 97 98 tegra_dc_write_regs(dc, rgb_disable, ARRAY_SIZE(rgb_disable)); 99 100 return 0; 101 } 102 103 static int tegra_output_rgb_setup_clock(struct tegra_output *output, 104 struct clk *clk, unsigned long pclk) 105 { 106 struct tegra_rgb *rgb = to_rgb(output); 107 108 return clk_set_parent(clk, rgb->clk_parent); 109 } 110 111 static int tegra_output_rgb_check_mode(struct tegra_output *output, 112 struct drm_display_mode *mode, 113 enum drm_mode_status *status) 114 { 115 /* 116 * FIXME: For now, always assume that the mode is okay. There are 117 * unresolved issues with clk_round_rate(), which doesn't always 118 * reliably report whether a frequency can be set or not. 119 */ 120 121 *status = MODE_OK; 122 123 return 0; 124 } 125 126 static const struct tegra_output_ops rgb_ops = { 127 .enable = tegra_output_rgb_enable, 128 .disable = tegra_output_rgb_disable, 129 .setup_clock = tegra_output_rgb_setup_clock, 130 .check_mode = tegra_output_rgb_check_mode, 131 }; 132 133 int tegra_dc_rgb_probe(struct tegra_dc *dc) 134 { 135 struct device_node *np; 136 struct tegra_rgb *rgb; 137 int err; 138 139 np = of_get_child_by_name(dc->dev->of_node, "rgb"); 140 if (!np || !of_device_is_available(np)) 141 return -ENODEV; 142 143 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL); 144 if (!rgb) 145 return -ENOMEM; 146 147 rgb->output.dev = dc->dev; 148 rgb->output.of_node = np; 149 150 err = tegra_output_probe(&rgb->output); 151 if (err < 0) 152 return err; 153 154 rgb->clk = devm_clk_get(dc->dev, NULL); 155 if (IS_ERR(rgb->clk)) { 156 dev_err(dc->dev, "failed to get clock\n"); 157 return PTR_ERR(rgb->clk); 158 } 159 160 rgb->clk_parent = devm_clk_get(dc->dev, "parent"); 161 if (IS_ERR(rgb->clk_parent)) { 162 dev_err(dc->dev, "failed to get parent clock\n"); 163 return PTR_ERR(rgb->clk_parent); 164 } 165 166 err = clk_set_parent(rgb->clk, rgb->clk_parent); 167 if (err < 0) { 168 dev_err(dc->dev, "failed to set parent clock: %d\n", err); 169 return err; 170 } 171 172 dc->rgb = &rgb->output; 173 174 return 0; 175 } 176 177 int tegra_dc_rgb_remove(struct tegra_dc *dc) 178 { 179 int err; 180 181 if (!dc->rgb) 182 return 0; 183 184 err = tegra_output_remove(dc->rgb); 185 if (err < 0) 186 return err; 187 188 return 0; 189 } 190 191 int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc) 192 { 193 struct tegra_rgb *rgb = to_rgb(dc->rgb); 194 int err; 195 196 if (!dc->rgb) 197 return -ENODEV; 198 199 rgb->output.type = TEGRA_OUTPUT_RGB; 200 rgb->output.ops = &rgb_ops; 201 202 err = tegra_output_init(dc->base.dev, &rgb->output); 203 if (err < 0) { 204 dev_err(dc->dev, "output setup failed: %d\n", err); 205 return err; 206 } 207 208 /* 209 * By default, outputs can be associated with each display controller. 210 * RGB outputs are an exception, so we make sure they can be attached 211 * to only their parent display controller. 212 */ 213 rgb->output.encoder.possible_crtcs = 1 << dc->pipe; 214 215 return 0; 216 } 217 218 int tegra_dc_rgb_exit(struct tegra_dc *dc) 219 { 220 if (dc->rgb) { 221 int err; 222 223 err = tegra_output_disable(dc->rgb); 224 if (err < 0) { 225 dev_err(dc->dev, "output failed to disable: %d\n", err); 226 return err; 227 } 228 229 err = tegra_output_exit(dc->rgb); 230 if (err < 0) { 231 dev_err(dc->dev, "output cleanup failed: %d\n", err); 232 return err; 233 } 234 235 dc->rgb = NULL; 236 } 237 238 return 0; 239 } 240