1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Avionic Design GmbH 4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 9 #include <drm/drm_atomic_helper.h> 10 #include <drm/drm_bridge_connector.h> 11 #include <drm/drm_simple_kms_helper.h> 12 13 #include "drm.h" 14 #include "dc.h" 15 16 struct tegra_rgb { 17 struct tegra_output output; 18 struct tegra_dc *dc; 19 20 struct clk *pll_d_out0; 21 struct clk *pll_d2_out0; 22 struct clk *clk_parent; 23 struct clk *clk; 24 }; 25 26 static inline struct tegra_rgb *to_rgb(struct tegra_output *output) 27 { 28 return container_of(output, struct tegra_rgb, output); 29 } 30 31 struct reg_entry { 32 unsigned long offset; 33 unsigned long value; 34 }; 35 36 static const struct reg_entry rgb_enable[] = { 37 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 }, 38 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 }, 39 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 }, 40 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 }, 41 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 }, 42 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 }, 43 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 }, 44 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 }, 45 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 }, 46 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 }, 47 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 }, 48 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 }, 49 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 }, 50 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 }, 51 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 }, 52 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 }, 53 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 }, 54 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 }, 55 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 }, 56 }; 57 58 static const struct reg_entry rgb_disable[] = { 59 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 }, 60 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 }, 61 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 }, 62 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 }, 63 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 }, 64 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 }, 65 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 }, 66 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa }, 67 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa }, 68 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa }, 69 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa }, 70 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 }, 71 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 }, 72 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 }, 73 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 }, 74 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 }, 75 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 }, 76 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 }, 77 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 }, 78 }; 79 80 static void tegra_dc_write_regs(struct tegra_dc *dc, 81 const struct reg_entry *table, 82 unsigned int num) 83 { 84 unsigned int i; 85 86 for (i = 0; i < num; i++) 87 tegra_dc_writel(dc, table[i].value, table[i].offset); 88 } 89 90 static void tegra_rgb_encoder_disable(struct drm_encoder *encoder) 91 { 92 struct tegra_output *output = encoder_to_output(encoder); 93 struct tegra_rgb *rgb = to_rgb(output); 94 95 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable)); 96 tegra_dc_commit(rgb->dc); 97 } 98 99 static void tegra_rgb_encoder_enable(struct drm_encoder *encoder) 100 { 101 struct tegra_output *output = encoder_to_output(encoder); 102 struct tegra_rgb *rgb = to_rgb(output); 103 u32 value; 104 105 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable)); 106 107 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL; 108 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); 109 110 /* XXX: parameterize? */ 111 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); 112 value &= ~LVS_OUTPUT_POLARITY_LOW; 113 value &= ~LHS_OUTPUT_POLARITY_LOW; 114 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); 115 116 /* XXX: parameterize? */ 117 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB | 118 DISP_ORDER_RED_BLUE; 119 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL); 120 121 tegra_dc_commit(rgb->dc); 122 } 123 124 static bool tegra_rgb_pll_rate_change_allowed(struct tegra_rgb *rgb) 125 { 126 if (!rgb->pll_d2_out0) 127 return false; 128 129 if (!clk_is_match(rgb->clk_parent, rgb->pll_d_out0) && 130 !clk_is_match(rgb->clk_parent, rgb->pll_d2_out0)) 131 return false; 132 133 return true; 134 } 135 136 static int 137 tegra_rgb_encoder_atomic_check(struct drm_encoder *encoder, 138 struct drm_crtc_state *crtc_state, 139 struct drm_connector_state *conn_state) 140 { 141 struct tegra_output *output = encoder_to_output(encoder); 142 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 143 unsigned long pclk = crtc_state->mode.clock * 1000; 144 struct tegra_rgb *rgb = to_rgb(output); 145 unsigned int div; 146 int err; 147 148 /* 149 * We may not want to change the frequency of the parent clock, since 150 * it may be a parent for other peripherals. This is due to the fact 151 * that on Tegra20 there's only a single clock dedicated to display 152 * (pll_d_out0), whereas later generations have a second one that can 153 * be used to independently drive a second output (pll_d2_out0). 154 * 155 * As a way to support multiple outputs on Tegra20 as well, pll_p is 156 * typically used as the parent clock for the display controllers. 157 * But this comes at a cost: pll_p is the parent of several other 158 * peripherals, so its frequency shouldn't change out of the blue. 159 * 160 * The best we can do at this point is to use the shift clock divider 161 * and hope that the desired frequency can be matched (or at least 162 * matched sufficiently close that the panel will still work). 163 */ 164 if (tegra_rgb_pll_rate_change_allowed(rgb)) { 165 /* 166 * Set display controller clock to x2 of PCLK in order to 167 * produce higher resolution pulse positions. 168 */ 169 div = 2; 170 pclk *= 2; 171 } else { 172 div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2; 173 pclk = 0; 174 } 175 176 err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent, 177 pclk, div); 178 if (err < 0) { 179 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 180 return err; 181 } 182 183 return err; 184 } 185 186 static const struct drm_encoder_helper_funcs tegra_rgb_encoder_helper_funcs = { 187 .disable = tegra_rgb_encoder_disable, 188 .enable = tegra_rgb_encoder_enable, 189 .atomic_check = tegra_rgb_encoder_atomic_check, 190 }; 191 192 int tegra_dc_rgb_probe(struct tegra_dc *dc) 193 { 194 struct device_node *np; 195 struct tegra_rgb *rgb; 196 int err; 197 198 np = of_get_child_by_name(dc->dev->of_node, "rgb"); 199 if (!np || !of_device_is_available(np)) 200 return -ENODEV; 201 202 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL); 203 if (!rgb) 204 return -ENOMEM; 205 206 rgb->output.dev = dc->dev; 207 rgb->output.of_node = np; 208 rgb->dc = dc; 209 210 err = tegra_output_probe(&rgb->output); 211 if (err < 0) 212 return err; 213 214 rgb->clk = devm_clk_get(dc->dev, NULL); 215 if (IS_ERR(rgb->clk)) { 216 dev_err(dc->dev, "failed to get clock\n"); 217 return PTR_ERR(rgb->clk); 218 } 219 220 rgb->clk_parent = devm_clk_get(dc->dev, "parent"); 221 if (IS_ERR(rgb->clk_parent)) { 222 dev_err(dc->dev, "failed to get parent clock\n"); 223 return PTR_ERR(rgb->clk_parent); 224 } 225 226 err = clk_set_parent(rgb->clk, rgb->clk_parent); 227 if (err < 0) { 228 dev_err(dc->dev, "failed to set parent clock: %d\n", err); 229 return err; 230 } 231 232 rgb->pll_d_out0 = clk_get_sys(NULL, "pll_d_out0"); 233 if (IS_ERR(rgb->pll_d_out0)) { 234 err = PTR_ERR(rgb->pll_d_out0); 235 dev_err(dc->dev, "failed to get pll_d_out0: %d\n", err); 236 return err; 237 } 238 239 if (dc->soc->has_pll_d2_out0) { 240 rgb->pll_d2_out0 = clk_get_sys(NULL, "pll_d2_out0"); 241 if (IS_ERR(rgb->pll_d2_out0)) { 242 err = PTR_ERR(rgb->pll_d2_out0); 243 dev_err(dc->dev, "failed to get pll_d2_out0: %d\n", err); 244 return err; 245 } 246 } 247 248 dc->rgb = &rgb->output; 249 250 return 0; 251 } 252 253 int tegra_dc_rgb_remove(struct tegra_dc *dc) 254 { 255 struct tegra_rgb *rgb; 256 257 if (!dc->rgb) 258 return 0; 259 260 rgb = to_rgb(dc->rgb); 261 clk_put(rgb->pll_d2_out0); 262 clk_put(rgb->pll_d_out0); 263 264 tegra_output_remove(dc->rgb); 265 dc->rgb = NULL; 266 267 return 0; 268 } 269 270 int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc) 271 { 272 struct tegra_output *output = dc->rgb; 273 struct drm_connector *connector; 274 int err; 275 276 if (!dc->rgb) 277 return -ENODEV; 278 279 drm_simple_encoder_init(drm, &output->encoder, DRM_MODE_ENCODER_LVDS); 280 drm_encoder_helper_add(&output->encoder, 281 &tegra_rgb_encoder_helper_funcs); 282 283 /* 284 * Wrap directly-connected panel into DRM bridge in order to let 285 * DRM core to handle panel for us. 286 */ 287 if (output->panel) { 288 output->bridge = devm_drm_panel_bridge_add(output->dev, 289 output->panel); 290 if (IS_ERR(output->bridge)) { 291 dev_err(output->dev, 292 "failed to wrap panel into bridge: %pe\n", 293 output->bridge); 294 return PTR_ERR(output->bridge); 295 } 296 297 output->panel = NULL; 298 } 299 300 /* 301 * Tegra devices that have LVDS panel utilize LVDS encoder bridge 302 * for converting up to 28 LCD LVTTL lanes into 5/4 LVDS lanes that 303 * go to display panel's receiver. 304 * 305 * Encoder usually have a power-down control which needs to be enabled 306 * in order to transmit data to the panel. Historically devices that 307 * use an older device-tree version didn't model the bridge, assuming 308 * that encoder is turned ON by default, while today's DRM allows us 309 * to model LVDS encoder properly. 310 * 311 * Newer device-trees utilize LVDS encoder bridge, which provides 312 * us with a connector and handles the display panel. 313 * 314 * For older device-trees we wrapped panel into the panel-bridge. 315 */ 316 if (output->bridge) { 317 err = drm_bridge_attach(&output->encoder, output->bridge, 318 NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); 319 if (err) 320 return err; 321 322 connector = drm_bridge_connector_init(drm, &output->encoder); 323 if (IS_ERR(connector)) { 324 dev_err(output->dev, 325 "failed to initialize bridge connector: %pe\n", 326 connector); 327 return PTR_ERR(connector); 328 } 329 330 drm_connector_attach_encoder(connector, &output->encoder); 331 } 332 333 err = tegra_output_init(drm, output); 334 if (err < 0) { 335 dev_err(output->dev, "failed to initialize output: %d\n", err); 336 return err; 337 } 338 339 /* 340 * Other outputs can be attached to either display controller. The RGB 341 * outputs are an exception and work only with their parent display 342 * controller. 343 */ 344 output->encoder.possible_crtcs = drm_crtc_mask(&dc->base); 345 346 return 0; 347 } 348 349 int tegra_dc_rgb_exit(struct tegra_dc *dc) 350 { 351 if (dc->rgb) 352 tegra_output_exit(dc->rgb); 353 354 return 0; 355 } 356