1 /* 2 * Copyright (C) 2012 Avionic Design GmbH 3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #include <linux/clk.h> 11 12 #include "drm.h" 13 #include "dc.h" 14 15 struct tegra_rgb { 16 struct tegra_output output; 17 struct tegra_dc *dc; 18 19 struct clk *clk_parent; 20 struct clk *clk; 21 }; 22 23 static inline struct tegra_rgb *to_rgb(struct tegra_output *output) 24 { 25 return container_of(output, struct tegra_rgb, output); 26 } 27 28 struct reg_entry { 29 unsigned long offset; 30 unsigned long value; 31 }; 32 33 static const struct reg_entry rgb_enable[] = { 34 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 }, 35 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 }, 36 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 }, 37 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 }, 38 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 }, 39 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 }, 40 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 }, 41 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 }, 42 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 }, 43 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 }, 44 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 }, 45 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 }, 46 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 }, 47 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 }, 48 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 }, 49 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 }, 50 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 }, 51 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 }, 52 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 }, 53 }; 54 55 static const struct reg_entry rgb_disable[] = { 56 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 }, 57 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 }, 58 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 }, 59 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 }, 60 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 }, 61 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 }, 62 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 }, 63 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa }, 64 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa }, 65 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa }, 66 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa }, 67 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 }, 68 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 }, 69 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 }, 70 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 }, 71 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 }, 72 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 }, 73 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 }, 74 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 }, 75 }; 76 77 static void tegra_dc_write_regs(struct tegra_dc *dc, 78 const struct reg_entry *table, 79 unsigned int num) 80 { 81 unsigned int i; 82 83 for (i = 0; i < num; i++) 84 tegra_dc_writel(dc, table[i].value, table[i].offset); 85 } 86 87 static int tegra_output_rgb_enable(struct tegra_output *output) 88 { 89 struct tegra_rgb *rgb = to_rgb(output); 90 unsigned long value; 91 92 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable)); 93 94 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL; 95 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); 96 97 /* XXX: parameterize? */ 98 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); 99 value &= ~LVS_OUTPUT_POLARITY_LOW; 100 value &= ~LHS_OUTPUT_POLARITY_LOW; 101 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); 102 103 /* XXX: parameterize? */ 104 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB | 105 DISP_ORDER_RED_BLUE; 106 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL); 107 108 /* XXX: parameterize? */ 109 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE; 110 tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS); 111 112 value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_COMMAND); 113 value &= ~DISP_CTRL_MODE_MASK; 114 value |= DISP_CTRL_MODE_C_DISPLAY; 115 tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_COMMAND); 116 117 value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_POWER_CONTROL); 118 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 119 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; 120 tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 121 122 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); 123 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 124 125 return 0; 126 } 127 128 static int tegra_output_rgb_disable(struct tegra_output *output) 129 { 130 struct tegra_rgb *rgb = to_rgb(output); 131 unsigned long value; 132 133 value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_POWER_CONTROL); 134 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 135 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); 136 tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 137 138 value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_COMMAND); 139 value &= ~DISP_CTRL_MODE_MASK; 140 tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_COMMAND); 141 142 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); 143 tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 144 145 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable)); 146 147 return 0; 148 } 149 150 static int tegra_output_rgb_setup_clock(struct tegra_output *output, 151 struct clk *clk, unsigned long pclk) 152 { 153 struct tegra_rgb *rgb = to_rgb(output); 154 155 return clk_set_parent(clk, rgb->clk_parent); 156 } 157 158 static int tegra_output_rgb_check_mode(struct tegra_output *output, 159 struct drm_display_mode *mode, 160 enum drm_mode_status *status) 161 { 162 /* 163 * FIXME: For now, always assume that the mode is okay. There are 164 * unresolved issues with clk_round_rate(), which doesn't always 165 * reliably report whether a frequency can be set or not. 166 */ 167 168 *status = MODE_OK; 169 170 return 0; 171 } 172 173 static const struct tegra_output_ops rgb_ops = { 174 .enable = tegra_output_rgb_enable, 175 .disable = tegra_output_rgb_disable, 176 .setup_clock = tegra_output_rgb_setup_clock, 177 .check_mode = tegra_output_rgb_check_mode, 178 }; 179 180 int tegra_dc_rgb_probe(struct tegra_dc *dc) 181 { 182 struct device_node *np; 183 struct tegra_rgb *rgb; 184 int err; 185 186 np = of_get_child_by_name(dc->dev->of_node, "rgb"); 187 if (!np || !of_device_is_available(np)) 188 return -ENODEV; 189 190 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL); 191 if (!rgb) 192 return -ENOMEM; 193 194 rgb->output.dev = dc->dev; 195 rgb->output.of_node = np; 196 rgb->dc = dc; 197 198 err = tegra_output_probe(&rgb->output); 199 if (err < 0) 200 return err; 201 202 rgb->clk = devm_clk_get(dc->dev, NULL); 203 if (IS_ERR(rgb->clk)) { 204 dev_err(dc->dev, "failed to get clock\n"); 205 return PTR_ERR(rgb->clk); 206 } 207 208 rgb->clk_parent = devm_clk_get(dc->dev, "parent"); 209 if (IS_ERR(rgb->clk_parent)) { 210 dev_err(dc->dev, "failed to get parent clock\n"); 211 return PTR_ERR(rgb->clk_parent); 212 } 213 214 err = clk_set_parent(rgb->clk, rgb->clk_parent); 215 if (err < 0) { 216 dev_err(dc->dev, "failed to set parent clock: %d\n", err); 217 return err; 218 } 219 220 dc->rgb = &rgb->output; 221 222 return 0; 223 } 224 225 int tegra_dc_rgb_remove(struct tegra_dc *dc) 226 { 227 int err; 228 229 if (!dc->rgb) 230 return 0; 231 232 err = tegra_output_remove(dc->rgb); 233 if (err < 0) 234 return err; 235 236 return 0; 237 } 238 239 int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc) 240 { 241 struct tegra_rgb *rgb = to_rgb(dc->rgb); 242 int err; 243 244 if (!dc->rgb) 245 return -ENODEV; 246 247 rgb->output.type = TEGRA_OUTPUT_RGB; 248 rgb->output.ops = &rgb_ops; 249 250 err = tegra_output_init(dc->base.dev, &rgb->output); 251 if (err < 0) { 252 dev_err(dc->dev, "output setup failed: %d\n", err); 253 return err; 254 } 255 256 /* 257 * By default, outputs can be associated with each display controller. 258 * RGB outputs are an exception, so we make sure they can be attached 259 * to only their parent display controller. 260 */ 261 rgb->output.encoder.possible_crtcs = drm_crtc_mask(&dc->base); 262 263 return 0; 264 } 265 266 int tegra_dc_rgb_exit(struct tegra_dc *dc) 267 { 268 if (dc->rgb) { 269 int err; 270 271 err = tegra_output_disable(dc->rgb); 272 if (err < 0) { 273 dev_err(dc->dev, "output failed to disable: %d\n", err); 274 return err; 275 } 276 277 err = tegra_output_exit(dc->rgb); 278 if (err < 0) { 279 dev_err(dc->dev, "output cleanup failed: %d\n", err); 280 return err; 281 } 282 283 dc->rgb = NULL; 284 } 285 286 return 0; 287 } 288