1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Avionic Design GmbH 4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 9 #include <drm/drm_atomic_helper.h> 10 #include <drm/drm_panel.h> 11 #include <drm/drm_simple_kms_helper.h> 12 13 #include "drm.h" 14 #include "dc.h" 15 16 struct tegra_rgb { 17 struct tegra_output output; 18 struct tegra_dc *dc; 19 20 struct clk *clk_parent; 21 struct clk *clk; 22 }; 23 24 static inline struct tegra_rgb *to_rgb(struct tegra_output *output) 25 { 26 return container_of(output, struct tegra_rgb, output); 27 } 28 29 struct reg_entry { 30 unsigned long offset; 31 unsigned long value; 32 }; 33 34 static const struct reg_entry rgb_enable[] = { 35 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 }, 36 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 }, 37 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 }, 38 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 }, 39 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 }, 40 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 }, 41 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 }, 42 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 }, 43 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 }, 44 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 }, 45 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 }, 46 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 }, 47 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 }, 48 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 }, 49 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 }, 50 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 }, 51 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 }, 52 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 }, 53 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 }, 54 }; 55 56 static const struct reg_entry rgb_disable[] = { 57 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 }, 58 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 }, 59 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 }, 60 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 }, 61 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 }, 62 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 }, 63 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 }, 64 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa }, 65 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa }, 66 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa }, 67 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa }, 68 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 }, 69 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 }, 70 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 }, 71 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 }, 72 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 }, 73 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 }, 74 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 }, 75 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 }, 76 }; 77 78 static void tegra_dc_write_regs(struct tegra_dc *dc, 79 const struct reg_entry *table, 80 unsigned int num) 81 { 82 unsigned int i; 83 84 for (i = 0; i < num; i++) 85 tegra_dc_writel(dc, table[i].value, table[i].offset); 86 } 87 88 static const struct drm_connector_funcs tegra_rgb_connector_funcs = { 89 .reset = drm_atomic_helper_connector_reset, 90 .detect = tegra_output_connector_detect, 91 .fill_modes = drm_helper_probe_single_connector_modes, 92 .destroy = tegra_output_connector_destroy, 93 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 94 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 95 }; 96 97 static enum drm_mode_status 98 tegra_rgb_connector_mode_valid(struct drm_connector *connector, 99 struct drm_display_mode *mode) 100 { 101 /* 102 * FIXME: For now, always assume that the mode is okay. There are 103 * unresolved issues with clk_round_rate(), which doesn't always 104 * reliably report whether a frequency can be set or not. 105 */ 106 return MODE_OK; 107 } 108 109 static const struct drm_connector_helper_funcs tegra_rgb_connector_helper_funcs = { 110 .get_modes = tegra_output_connector_get_modes, 111 .mode_valid = tegra_rgb_connector_mode_valid, 112 }; 113 114 static void tegra_rgb_encoder_disable(struct drm_encoder *encoder) 115 { 116 struct tegra_output *output = encoder_to_output(encoder); 117 struct tegra_rgb *rgb = to_rgb(output); 118 119 if (output->panel) 120 drm_panel_disable(output->panel); 121 122 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable)); 123 tegra_dc_commit(rgb->dc); 124 125 if (output->panel) 126 drm_panel_unprepare(output->panel); 127 } 128 129 static void tegra_rgb_encoder_enable(struct drm_encoder *encoder) 130 { 131 struct tegra_output *output = encoder_to_output(encoder); 132 struct tegra_rgb *rgb = to_rgb(output); 133 u32 value; 134 135 if (output->panel) 136 drm_panel_prepare(output->panel); 137 138 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable)); 139 140 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL; 141 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); 142 143 /* XXX: parameterize? */ 144 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1)); 145 value &= ~LVS_OUTPUT_POLARITY_LOW; 146 value &= ~LHS_OUTPUT_POLARITY_LOW; 147 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); 148 149 /* XXX: parameterize? */ 150 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB | 151 DISP_ORDER_RED_BLUE; 152 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL); 153 154 /* XXX: parameterize? */ 155 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE; 156 tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS); 157 158 tegra_dc_commit(rgb->dc); 159 160 if (output->panel) 161 drm_panel_enable(output->panel); 162 } 163 164 static int 165 tegra_rgb_encoder_atomic_check(struct drm_encoder *encoder, 166 struct drm_crtc_state *crtc_state, 167 struct drm_connector_state *conn_state) 168 { 169 struct tegra_output *output = encoder_to_output(encoder); 170 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 171 unsigned long pclk = crtc_state->mode.clock * 1000; 172 struct tegra_rgb *rgb = to_rgb(output); 173 unsigned int div; 174 int err; 175 176 /* 177 * We may not want to change the frequency of the parent clock, since 178 * it may be a parent for other peripherals. This is due to the fact 179 * that on Tegra20 there's only a single clock dedicated to display 180 * (pll_d_out0), whereas later generations have a second one that can 181 * be used to independently drive a second output (pll_d2_out0). 182 * 183 * As a way to support multiple outputs on Tegra20 as well, pll_p is 184 * typically used as the parent clock for the display controllers. 185 * But this comes at a cost: pll_p is the parent of several other 186 * peripherals, so its frequency shouldn't change out of the blue. 187 * 188 * The best we can do at this point is to use the shift clock divider 189 * and hope that the desired frequency can be matched (or at least 190 * matched sufficiently close that the panel will still work). 191 */ 192 div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2; 193 pclk = 0; 194 195 err = tegra_dc_state_setup_clock(dc, crtc_state, rgb->clk_parent, 196 pclk, div); 197 if (err < 0) { 198 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 199 return err; 200 } 201 202 return err; 203 } 204 205 static const struct drm_encoder_helper_funcs tegra_rgb_encoder_helper_funcs = { 206 .disable = tegra_rgb_encoder_disable, 207 .enable = tegra_rgb_encoder_enable, 208 .atomic_check = tegra_rgb_encoder_atomic_check, 209 }; 210 211 int tegra_dc_rgb_probe(struct tegra_dc *dc) 212 { 213 struct device_node *np; 214 struct tegra_rgb *rgb; 215 int err; 216 217 np = of_get_child_by_name(dc->dev->of_node, "rgb"); 218 if (!np || !of_device_is_available(np)) 219 return -ENODEV; 220 221 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL); 222 if (!rgb) 223 return -ENOMEM; 224 225 rgb->output.dev = dc->dev; 226 rgb->output.of_node = np; 227 rgb->dc = dc; 228 229 err = tegra_output_probe(&rgb->output); 230 if (err < 0) 231 return err; 232 233 rgb->clk = devm_clk_get(dc->dev, NULL); 234 if (IS_ERR(rgb->clk)) { 235 dev_err(dc->dev, "failed to get clock\n"); 236 return PTR_ERR(rgb->clk); 237 } 238 239 rgb->clk_parent = devm_clk_get(dc->dev, "parent"); 240 if (IS_ERR(rgb->clk_parent)) { 241 dev_err(dc->dev, "failed to get parent clock\n"); 242 return PTR_ERR(rgb->clk_parent); 243 } 244 245 err = clk_set_parent(rgb->clk, rgb->clk_parent); 246 if (err < 0) { 247 dev_err(dc->dev, "failed to set parent clock: %d\n", err); 248 return err; 249 } 250 251 dc->rgb = &rgb->output; 252 253 return 0; 254 } 255 256 int tegra_dc_rgb_remove(struct tegra_dc *dc) 257 { 258 if (!dc->rgb) 259 return 0; 260 261 tegra_output_remove(dc->rgb); 262 dc->rgb = NULL; 263 264 return 0; 265 } 266 267 int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc) 268 { 269 struct tegra_output *output = dc->rgb; 270 int err; 271 272 if (!dc->rgb) 273 return -ENODEV; 274 275 drm_connector_init(drm, &output->connector, &tegra_rgb_connector_funcs, 276 DRM_MODE_CONNECTOR_LVDS); 277 drm_connector_helper_add(&output->connector, 278 &tegra_rgb_connector_helper_funcs); 279 output->connector.dpms = DRM_MODE_DPMS_OFF; 280 281 drm_simple_encoder_init(drm, &output->encoder, DRM_MODE_ENCODER_LVDS); 282 drm_encoder_helper_add(&output->encoder, 283 &tegra_rgb_encoder_helper_funcs); 284 285 drm_connector_attach_encoder(&output->connector, 286 &output->encoder); 287 drm_connector_register(&output->connector); 288 289 err = tegra_output_init(drm, output); 290 if (err < 0) { 291 dev_err(output->dev, "failed to initialize output: %d\n", err); 292 return err; 293 } 294 295 /* 296 * Other outputs can be attached to either display controller. The RGB 297 * outputs are an exception and work only with their parent display 298 * controller. 299 */ 300 output->encoder.possible_crtcs = drm_crtc_mask(&dc->base); 301 302 return 0; 303 } 304 305 int tegra_dc_rgb_exit(struct tegra_dc *dc) 306 { 307 if (dc->rgb) 308 tegra_output_exit(dc->rgb); 309 310 return 0; 311 } 312