1 /* 2 * Copyright (C) 2012 Avionic Design GmbH 3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #include <linux/clk.h> 11 12 #include "drm.h" 13 #include "dc.h" 14 15 struct tegra_rgb { 16 struct tegra_output output; 17 struct tegra_dc *dc; 18 19 struct clk *clk_parent; 20 struct clk *clk; 21 }; 22 23 static inline struct tegra_rgb *to_rgb(struct tegra_output *output) 24 { 25 return container_of(output, struct tegra_rgb, output); 26 } 27 28 struct reg_entry { 29 unsigned long offset; 30 unsigned long value; 31 }; 32 33 static const struct reg_entry rgb_enable[] = { 34 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 }, 35 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 }, 36 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 }, 37 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 }, 38 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 }, 39 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 }, 40 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 }, 41 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 }, 42 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 }, 43 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 }, 44 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 }, 45 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 }, 46 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 }, 47 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 }, 48 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 }, 49 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 }, 50 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 }, 51 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 }, 52 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 }, 53 }; 54 55 static const struct reg_entry rgb_disable[] = { 56 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 }, 57 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 }, 58 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 }, 59 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 }, 60 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 }, 61 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 }, 62 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 }, 63 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa }, 64 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa }, 65 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa }, 66 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa }, 67 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 }, 68 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 }, 69 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 }, 70 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 }, 71 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 }, 72 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 }, 73 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 }, 74 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 }, 75 }; 76 77 static void tegra_dc_write_regs(struct tegra_dc *dc, 78 const struct reg_entry *table, 79 unsigned int num) 80 { 81 unsigned int i; 82 83 for (i = 0; i < num; i++) 84 tegra_dc_writel(dc, table[i].value, table[i].offset); 85 } 86 87 static int tegra_output_rgb_enable(struct tegra_output *output) 88 { 89 struct tegra_rgb *rgb = to_rgb(output); 90 91 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable)); 92 93 return 0; 94 } 95 96 static int tegra_output_rgb_disable(struct tegra_output *output) 97 { 98 struct tegra_rgb *rgb = to_rgb(output); 99 100 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable)); 101 102 return 0; 103 } 104 105 static int tegra_output_rgb_setup_clock(struct tegra_output *output, 106 struct clk *clk, unsigned long pclk) 107 { 108 struct tegra_rgb *rgb = to_rgb(output); 109 110 return clk_set_parent(clk, rgb->clk_parent); 111 } 112 113 static int tegra_output_rgb_check_mode(struct tegra_output *output, 114 struct drm_display_mode *mode, 115 enum drm_mode_status *status) 116 { 117 /* 118 * FIXME: For now, always assume that the mode is okay. There are 119 * unresolved issues with clk_round_rate(), which doesn't always 120 * reliably report whether a frequency can be set or not. 121 */ 122 123 *status = MODE_OK; 124 125 return 0; 126 } 127 128 static const struct tegra_output_ops rgb_ops = { 129 .enable = tegra_output_rgb_enable, 130 .disable = tegra_output_rgb_disable, 131 .setup_clock = tegra_output_rgb_setup_clock, 132 .check_mode = tegra_output_rgb_check_mode, 133 }; 134 135 int tegra_dc_rgb_probe(struct tegra_dc *dc) 136 { 137 struct device_node *np; 138 struct tegra_rgb *rgb; 139 int err; 140 141 np = of_get_child_by_name(dc->dev->of_node, "rgb"); 142 if (!np || !of_device_is_available(np)) 143 return -ENODEV; 144 145 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL); 146 if (!rgb) 147 return -ENOMEM; 148 149 rgb->output.dev = dc->dev; 150 rgb->output.of_node = np; 151 rgb->dc = dc; 152 153 err = tegra_output_probe(&rgb->output); 154 if (err < 0) 155 return err; 156 157 rgb->clk = devm_clk_get(dc->dev, NULL); 158 if (IS_ERR(rgb->clk)) { 159 dev_err(dc->dev, "failed to get clock\n"); 160 return PTR_ERR(rgb->clk); 161 } 162 163 rgb->clk_parent = devm_clk_get(dc->dev, "parent"); 164 if (IS_ERR(rgb->clk_parent)) { 165 dev_err(dc->dev, "failed to get parent clock\n"); 166 return PTR_ERR(rgb->clk_parent); 167 } 168 169 err = clk_set_parent(rgb->clk, rgb->clk_parent); 170 if (err < 0) { 171 dev_err(dc->dev, "failed to set parent clock: %d\n", err); 172 return err; 173 } 174 175 dc->rgb = &rgb->output; 176 177 return 0; 178 } 179 180 int tegra_dc_rgb_remove(struct tegra_dc *dc) 181 { 182 int err; 183 184 if (!dc->rgb) 185 return 0; 186 187 err = tegra_output_remove(dc->rgb); 188 if (err < 0) 189 return err; 190 191 return 0; 192 } 193 194 int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc) 195 { 196 struct tegra_rgb *rgb = to_rgb(dc->rgb); 197 int err; 198 199 if (!dc->rgb) 200 return -ENODEV; 201 202 rgb->output.type = TEGRA_OUTPUT_RGB; 203 rgb->output.ops = &rgb_ops; 204 205 err = tegra_output_init(dc->base.dev, &rgb->output); 206 if (err < 0) { 207 dev_err(dc->dev, "output setup failed: %d\n", err); 208 return err; 209 } 210 211 /* 212 * By default, outputs can be associated with each display controller. 213 * RGB outputs are an exception, so we make sure they can be attached 214 * to only their parent display controller. 215 */ 216 rgb->output.encoder.possible_crtcs = 1 << dc->pipe; 217 218 return 0; 219 } 220 221 int tegra_dc_rgb_exit(struct tegra_dc *dc) 222 { 223 if (dc->rgb) { 224 int err; 225 226 err = tegra_output_disable(dc->rgb); 227 if (err < 0) { 228 dev_err(dc->dev, "output failed to disable: %d\n", err); 229 return err; 230 } 231 232 err = tegra_output_exit(dc->rgb); 233 if (err < 0) { 234 dev_err(dc->dev, "output cleanup failed: %d\n", err); 235 return err; 236 } 237 238 dc->rgb = NULL; 239 } 240 241 return 0; 242 } 243