1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/iommu.h> 7 #include <linux/interconnect.h> 8 9 #include <drm/drm_atomic.h> 10 #include <drm/drm_atomic_helper.h> 11 #include <drm/drm_fourcc.h> 12 #include <drm/drm_gem_atomic_helper.h> 13 #include <drm/drm_plane_helper.h> 14 15 #include "dc.h" 16 #include "plane.h" 17 18 static void tegra_plane_destroy(struct drm_plane *plane) 19 { 20 struct tegra_plane *p = to_tegra_plane(plane); 21 22 drm_plane_cleanup(plane); 23 kfree(p); 24 } 25 26 static void tegra_plane_reset(struct drm_plane *plane) 27 { 28 struct tegra_plane *p = to_tegra_plane(plane); 29 struct tegra_plane_state *state; 30 unsigned int i; 31 32 if (plane->state) 33 __drm_atomic_helper_plane_destroy_state(plane->state); 34 35 kfree(plane->state); 36 plane->state = NULL; 37 38 state = kzalloc(sizeof(*state), GFP_KERNEL); 39 if (state) { 40 plane->state = &state->base; 41 plane->state->plane = plane; 42 plane->state->zpos = p->index; 43 plane->state->normalized_zpos = p->index; 44 45 for (i = 0; i < 3; i++) 46 state->iova[i] = DMA_MAPPING_ERROR; 47 } 48 } 49 50 static struct drm_plane_state * 51 tegra_plane_atomic_duplicate_state(struct drm_plane *plane) 52 { 53 struct tegra_plane_state *state = to_tegra_plane_state(plane->state); 54 struct tegra_plane_state *copy; 55 unsigned int i; 56 57 copy = kmalloc(sizeof(*copy), GFP_KERNEL); 58 if (!copy) 59 return NULL; 60 61 __drm_atomic_helper_plane_duplicate_state(plane, ©->base); 62 copy->tiling = state->tiling; 63 copy->format = state->format; 64 copy->swap = state->swap; 65 copy->reflect_x = state->reflect_x; 66 copy->reflect_y = state->reflect_y; 67 copy->opaque = state->opaque; 68 copy->total_peak_memory_bandwidth = state->total_peak_memory_bandwidth; 69 copy->peak_memory_bandwidth = state->peak_memory_bandwidth; 70 copy->avg_memory_bandwidth = state->avg_memory_bandwidth; 71 72 for (i = 0; i < 2; i++) 73 copy->blending[i] = state->blending[i]; 74 75 for (i = 0; i < 3; i++) { 76 copy->iova[i] = DMA_MAPPING_ERROR; 77 copy->map[i] = NULL; 78 } 79 80 return ©->base; 81 } 82 83 static void tegra_plane_atomic_destroy_state(struct drm_plane *plane, 84 struct drm_plane_state *state) 85 { 86 __drm_atomic_helper_plane_destroy_state(state); 87 kfree(state); 88 } 89 90 static bool tegra_plane_supports_sector_layout(struct drm_plane *plane) 91 { 92 struct drm_crtc *crtc; 93 94 drm_for_each_crtc(crtc, plane->dev) { 95 if (plane->possible_crtcs & drm_crtc_mask(crtc)) { 96 struct tegra_dc *dc = to_tegra_dc(crtc); 97 98 if (!dc->soc->supports_sector_layout) 99 return false; 100 } 101 } 102 103 return true; 104 } 105 106 static bool tegra_plane_format_mod_supported(struct drm_plane *plane, 107 uint32_t format, 108 uint64_t modifier) 109 { 110 const struct drm_format_info *info = drm_format_info(format); 111 112 if (modifier == DRM_FORMAT_MOD_LINEAR) 113 return true; 114 115 /* check for the sector layout bit */ 116 if (fourcc_mod_is_vendor(modifier, NVIDIA)) { 117 if (modifier & DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT) { 118 if (!tegra_plane_supports_sector_layout(plane)) 119 return false; 120 } 121 } 122 123 if (info->num_planes == 1) 124 return true; 125 126 return false; 127 } 128 129 const struct drm_plane_funcs tegra_plane_funcs = { 130 .update_plane = drm_atomic_helper_update_plane, 131 .disable_plane = drm_atomic_helper_disable_plane, 132 .destroy = tegra_plane_destroy, 133 .reset = tegra_plane_reset, 134 .atomic_duplicate_state = tegra_plane_atomic_duplicate_state, 135 .atomic_destroy_state = tegra_plane_atomic_destroy_state, 136 .format_mod_supported = tegra_plane_format_mod_supported, 137 }; 138 139 static int tegra_dc_pin(struct tegra_dc *dc, struct tegra_plane_state *state) 140 { 141 unsigned int i; 142 int err; 143 144 for (i = 0; i < state->base.fb->format->num_planes; i++) { 145 struct tegra_bo *bo = tegra_fb_get_plane(state->base.fb, i); 146 struct host1x_bo_mapping *map; 147 148 map = host1x_bo_pin(dc->dev, &bo->base, DMA_TO_DEVICE, &dc->client.cache); 149 if (IS_ERR(map)) { 150 err = PTR_ERR(map); 151 goto unpin; 152 } 153 154 if (!dc->client.group) { 155 /* 156 * The display controller needs contiguous memory, so 157 * fail if the buffer is discontiguous and we fail to 158 * map its SG table to a single contiguous chunk of 159 * I/O virtual memory. 160 */ 161 if (map->chunks > 1) { 162 err = -EINVAL; 163 goto unpin; 164 } 165 166 state->iova[i] = map->phys; 167 } else { 168 state->iova[i] = bo->iova; 169 } 170 171 state->map[i] = map; 172 } 173 174 return 0; 175 176 unpin: 177 dev_err(dc->dev, "failed to map plane %u: %d\n", i, err); 178 179 while (i--) { 180 host1x_bo_unpin(state->map[i]); 181 state->iova[i] = DMA_MAPPING_ERROR; 182 state->map[i] = NULL; 183 } 184 185 return err; 186 } 187 188 static void tegra_dc_unpin(struct tegra_dc *dc, struct tegra_plane_state *state) 189 { 190 unsigned int i; 191 192 for (i = 0; i < state->base.fb->format->num_planes; i++) { 193 host1x_bo_unpin(state->map[i]); 194 state->iova[i] = DMA_MAPPING_ERROR; 195 state->map[i] = NULL; 196 } 197 } 198 199 int tegra_plane_prepare_fb(struct drm_plane *plane, 200 struct drm_plane_state *state) 201 { 202 struct tegra_dc *dc = to_tegra_dc(state->crtc); 203 int err; 204 205 if (!state->fb) 206 return 0; 207 208 err = drm_gem_plane_helper_prepare_fb(plane, state); 209 if (err < 0) 210 return err; 211 212 return tegra_dc_pin(dc, to_tegra_plane_state(state)); 213 } 214 215 void tegra_plane_cleanup_fb(struct drm_plane *plane, 216 struct drm_plane_state *state) 217 { 218 struct tegra_dc *dc = to_tegra_dc(state->crtc); 219 220 if (dc) 221 tegra_dc_unpin(dc, to_tegra_plane_state(state)); 222 } 223 224 static int tegra_plane_calculate_memory_bandwidth(struct drm_plane_state *state) 225 { 226 struct tegra_plane_state *tegra_state = to_tegra_plane_state(state); 227 unsigned int i, bpp, dst_w, dst_h, src_w, src_h, mul; 228 const struct tegra_dc_soc_info *soc; 229 const struct drm_format_info *fmt; 230 struct drm_crtc_state *crtc_state; 231 u64 avg_bandwidth, peak_bandwidth; 232 233 if (!state->visible) 234 return 0; 235 236 crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); 237 if (!crtc_state) 238 return -EINVAL; 239 240 src_w = drm_rect_width(&state->src) >> 16; 241 src_h = drm_rect_height(&state->src) >> 16; 242 dst_w = drm_rect_width(&state->dst); 243 dst_h = drm_rect_height(&state->dst); 244 245 fmt = state->fb->format; 246 soc = to_tegra_dc(state->crtc)->soc; 247 248 /* 249 * Note that real memory bandwidth vary depending on format and 250 * memory layout, we are not taking that into account because small 251 * estimation error isn't important since bandwidth is rounded up 252 * anyway. 253 */ 254 for (i = 0, bpp = 0; i < fmt->num_planes; i++) { 255 unsigned int bpp_plane = fmt->cpp[i] * 8; 256 257 /* 258 * Sub-sampling is relevant for chroma planes only and vertical 259 * readouts are not cached, hence only horizontal sub-sampling 260 * matters. 261 */ 262 if (i > 0) 263 bpp_plane /= fmt->hsub; 264 265 bpp += bpp_plane; 266 } 267 268 /* average bandwidth in kbytes/sec */ 269 avg_bandwidth = min(src_w, dst_w) * min(src_h, dst_h); 270 avg_bandwidth *= drm_mode_vrefresh(&crtc_state->adjusted_mode); 271 avg_bandwidth = DIV_ROUND_UP(avg_bandwidth * bpp, 8) + 999; 272 do_div(avg_bandwidth, 1000); 273 274 /* mode.clock in kHz, peak bandwidth in kbytes/sec */ 275 peak_bandwidth = DIV_ROUND_UP(crtc_state->adjusted_mode.clock * bpp, 8); 276 277 /* 278 * Tegra30/114 Memory Controller can't interleave DC memory requests 279 * for the tiled windows because DC uses 16-bytes atom, while DDR3 280 * uses 32-bytes atom. Hence there is x2 memory overfetch for tiled 281 * framebuffer and DDR3 on these SoCs. 282 */ 283 if (soc->plane_tiled_memory_bandwidth_x2 && 284 tegra_state->tiling.mode == TEGRA_BO_TILING_MODE_TILED) 285 mul = 2; 286 else 287 mul = 1; 288 289 /* ICC bandwidth in kbytes/sec */ 290 tegra_state->peak_memory_bandwidth = kBps_to_icc(peak_bandwidth) * mul; 291 tegra_state->avg_memory_bandwidth = kBps_to_icc(avg_bandwidth) * mul; 292 293 return 0; 294 } 295 296 int tegra_plane_state_add(struct tegra_plane *plane, 297 struct drm_plane_state *state) 298 { 299 struct drm_crtc_state *crtc_state; 300 struct tegra_dc_state *tegra; 301 int err; 302 303 /* Propagate errors from allocation or locking failures. */ 304 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); 305 if (IS_ERR(crtc_state)) 306 return PTR_ERR(crtc_state); 307 308 /* Check plane state for visibility and calculate clipping bounds */ 309 err = drm_atomic_helper_check_plane_state(state, crtc_state, 310 0, INT_MAX, true, true); 311 if (err < 0) 312 return err; 313 314 err = tegra_plane_calculate_memory_bandwidth(state); 315 if (err < 0) 316 return err; 317 318 tegra = to_dc_state(crtc_state); 319 320 tegra->planes |= WIN_A_ACT_REQ << plane->index; 321 322 return 0; 323 } 324 325 int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap) 326 { 327 /* assume no swapping of fetched data */ 328 if (swap) 329 *swap = BYTE_SWAP_NOSWAP; 330 331 switch (fourcc) { 332 case DRM_FORMAT_ARGB4444: 333 *format = WIN_COLOR_DEPTH_B4G4R4A4; 334 break; 335 336 case DRM_FORMAT_ARGB1555: 337 *format = WIN_COLOR_DEPTH_B5G5R5A1; 338 break; 339 340 case DRM_FORMAT_RGB565: 341 *format = WIN_COLOR_DEPTH_B5G6R5; 342 break; 343 344 case DRM_FORMAT_RGBA5551: 345 *format = WIN_COLOR_DEPTH_A1B5G5R5; 346 break; 347 348 case DRM_FORMAT_ARGB8888: 349 *format = WIN_COLOR_DEPTH_B8G8R8A8; 350 break; 351 352 case DRM_FORMAT_ABGR8888: 353 *format = WIN_COLOR_DEPTH_R8G8B8A8; 354 break; 355 356 case DRM_FORMAT_ABGR4444: 357 *format = WIN_COLOR_DEPTH_R4G4B4A4; 358 break; 359 360 case DRM_FORMAT_ABGR1555: 361 *format = WIN_COLOR_DEPTH_R5G5B5A; 362 break; 363 364 case DRM_FORMAT_BGRA5551: 365 *format = WIN_COLOR_DEPTH_AR5G5B5; 366 break; 367 368 case DRM_FORMAT_XRGB1555: 369 *format = WIN_COLOR_DEPTH_B5G5R5X1; 370 break; 371 372 case DRM_FORMAT_RGBX5551: 373 *format = WIN_COLOR_DEPTH_X1B5G5R5; 374 break; 375 376 case DRM_FORMAT_XBGR1555: 377 *format = WIN_COLOR_DEPTH_R5G5B5X1; 378 break; 379 380 case DRM_FORMAT_BGRX5551: 381 *format = WIN_COLOR_DEPTH_X1R5G5B5; 382 break; 383 384 case DRM_FORMAT_BGR565: 385 *format = WIN_COLOR_DEPTH_R5G6B5; 386 break; 387 388 case DRM_FORMAT_BGRA8888: 389 *format = WIN_COLOR_DEPTH_A8R8G8B8; 390 break; 391 392 case DRM_FORMAT_RGBA8888: 393 *format = WIN_COLOR_DEPTH_A8B8G8R8; 394 break; 395 396 case DRM_FORMAT_XRGB8888: 397 *format = WIN_COLOR_DEPTH_B8G8R8X8; 398 break; 399 400 case DRM_FORMAT_XBGR8888: 401 *format = WIN_COLOR_DEPTH_R8G8B8X8; 402 break; 403 404 case DRM_FORMAT_UYVY: 405 *format = WIN_COLOR_DEPTH_YCbCr422; 406 break; 407 408 case DRM_FORMAT_YUYV: 409 if (!swap) 410 return -EINVAL; 411 412 *format = WIN_COLOR_DEPTH_YCbCr422; 413 *swap = BYTE_SWAP_SWAP2; 414 break; 415 416 case DRM_FORMAT_YUV420: 417 *format = WIN_COLOR_DEPTH_YCbCr420P; 418 break; 419 420 case DRM_FORMAT_YUV422: 421 *format = WIN_COLOR_DEPTH_YCbCr422P; 422 break; 423 424 default: 425 return -EINVAL; 426 } 427 428 return 0; 429 } 430 431 bool tegra_plane_format_is_indexed(unsigned int format) 432 { 433 switch (format) { 434 case WIN_COLOR_DEPTH_P1: 435 case WIN_COLOR_DEPTH_P2: 436 case WIN_COLOR_DEPTH_P4: 437 case WIN_COLOR_DEPTH_P8: 438 return true; 439 } 440 441 return false; 442 } 443 444 bool tegra_plane_format_is_yuv(unsigned int format, bool *planar, unsigned int *bpc) 445 { 446 switch (format) { 447 case WIN_COLOR_DEPTH_YCbCr422: 448 case WIN_COLOR_DEPTH_YUV422: 449 if (planar) 450 *planar = false; 451 452 if (bpc) 453 *bpc = 8; 454 455 return true; 456 457 case WIN_COLOR_DEPTH_YCbCr420P: 458 case WIN_COLOR_DEPTH_YUV420P: 459 case WIN_COLOR_DEPTH_YCbCr422P: 460 case WIN_COLOR_DEPTH_YUV422P: 461 case WIN_COLOR_DEPTH_YCbCr422R: 462 case WIN_COLOR_DEPTH_YUV422R: 463 case WIN_COLOR_DEPTH_YCbCr422RA: 464 case WIN_COLOR_DEPTH_YUV422RA: 465 if (planar) 466 *planar = true; 467 468 if (bpc) 469 *bpc = 8; 470 471 return true; 472 } 473 474 if (planar) 475 *planar = false; 476 477 return false; 478 } 479 480 static bool __drm_format_has_alpha(u32 format) 481 { 482 switch (format) { 483 case DRM_FORMAT_ARGB1555: 484 case DRM_FORMAT_RGBA5551: 485 case DRM_FORMAT_ABGR8888: 486 case DRM_FORMAT_ARGB8888: 487 return true; 488 } 489 490 return false; 491 } 492 493 static int tegra_plane_format_get_alpha(unsigned int opaque, 494 unsigned int *alpha) 495 { 496 if (tegra_plane_format_is_yuv(opaque, NULL, NULL)) { 497 *alpha = opaque; 498 return 0; 499 } 500 501 switch (opaque) { 502 case WIN_COLOR_DEPTH_B5G5R5X1: 503 *alpha = WIN_COLOR_DEPTH_B5G5R5A1; 504 return 0; 505 506 case WIN_COLOR_DEPTH_X1B5G5R5: 507 *alpha = WIN_COLOR_DEPTH_A1B5G5R5; 508 return 0; 509 510 case WIN_COLOR_DEPTH_R8G8B8X8: 511 *alpha = WIN_COLOR_DEPTH_R8G8B8A8; 512 return 0; 513 514 case WIN_COLOR_DEPTH_B8G8R8X8: 515 *alpha = WIN_COLOR_DEPTH_B8G8R8A8; 516 return 0; 517 518 case WIN_COLOR_DEPTH_B5G6R5: 519 *alpha = opaque; 520 return 0; 521 } 522 523 return -EINVAL; 524 } 525 526 /* 527 * This is applicable to Tegra20 and Tegra30 only where the opaque formats can 528 * be emulated using the alpha formats and alpha blending disabled. 529 */ 530 static int tegra_plane_setup_opacity(struct tegra_plane *tegra, 531 struct tegra_plane_state *state) 532 { 533 unsigned int format; 534 int err; 535 536 switch (state->format) { 537 case WIN_COLOR_DEPTH_B5G5R5A1: 538 case WIN_COLOR_DEPTH_A1B5G5R5: 539 case WIN_COLOR_DEPTH_R8G8B8A8: 540 case WIN_COLOR_DEPTH_B8G8R8A8: 541 state->opaque = false; 542 break; 543 544 default: 545 err = tegra_plane_format_get_alpha(state->format, &format); 546 if (err < 0) 547 return err; 548 549 state->format = format; 550 state->opaque = true; 551 break; 552 } 553 554 return 0; 555 } 556 557 static int tegra_plane_check_transparency(struct tegra_plane *tegra, 558 struct tegra_plane_state *state) 559 { 560 struct drm_plane_state *old, *plane_state; 561 struct drm_plane *plane; 562 563 old = drm_atomic_get_old_plane_state(state->base.state, &tegra->base); 564 565 /* check if zpos / transparency changed */ 566 if (old->normalized_zpos == state->base.normalized_zpos && 567 to_tegra_plane_state(old)->opaque == state->opaque) 568 return 0; 569 570 /* include all sibling planes into this commit */ 571 drm_for_each_plane(plane, tegra->base.dev) { 572 struct tegra_plane *p = to_tegra_plane(plane); 573 574 /* skip this plane and planes on different CRTCs */ 575 if (p == tegra || p->dc != tegra->dc) 576 continue; 577 578 plane_state = drm_atomic_get_plane_state(state->base.state, 579 plane); 580 if (IS_ERR(plane_state)) 581 return PTR_ERR(plane_state); 582 } 583 584 return 1; 585 } 586 587 static unsigned int tegra_plane_get_overlap_index(struct tegra_plane *plane, 588 struct tegra_plane *other) 589 { 590 unsigned int index = 0, i; 591 592 WARN_ON(plane == other); 593 594 for (i = 0; i < 3; i++) { 595 if (i == plane->index) 596 continue; 597 598 if (i == other->index) 599 break; 600 601 index++; 602 } 603 604 return index; 605 } 606 607 static void tegra_plane_update_transparency(struct tegra_plane *tegra, 608 struct tegra_plane_state *state) 609 { 610 struct drm_plane_state *new; 611 struct drm_plane *plane; 612 unsigned int i; 613 614 for_each_new_plane_in_state(state->base.state, plane, new, i) { 615 struct tegra_plane *p = to_tegra_plane(plane); 616 unsigned index; 617 618 /* skip this plane and planes on different CRTCs */ 619 if (p == tegra || p->dc != tegra->dc) 620 continue; 621 622 index = tegra_plane_get_overlap_index(tegra, p); 623 624 if (new->fb && __drm_format_has_alpha(new->fb->format->format)) 625 state->blending[index].alpha = true; 626 else 627 state->blending[index].alpha = false; 628 629 if (new->normalized_zpos > state->base.normalized_zpos) 630 state->blending[index].top = true; 631 else 632 state->blending[index].top = false; 633 634 /* 635 * Missing framebuffer means that plane is disabled, in this 636 * case mark B / C window as top to be able to differentiate 637 * windows indices order in regards to zPos for the middle 638 * window X / Y registers programming. 639 */ 640 if (!new->fb) 641 state->blending[index].top = (index == 1); 642 } 643 } 644 645 static int tegra_plane_setup_transparency(struct tegra_plane *tegra, 646 struct tegra_plane_state *state) 647 { 648 struct tegra_plane_state *tegra_state; 649 struct drm_plane_state *new; 650 struct drm_plane *plane; 651 int err; 652 653 /* 654 * If planes zpos / transparency changed, sibling planes blending 655 * state may require adjustment and in this case they will be included 656 * into this atom commit, otherwise blending state is unchanged. 657 */ 658 err = tegra_plane_check_transparency(tegra, state); 659 if (err <= 0) 660 return err; 661 662 /* 663 * All planes are now in the atomic state, walk them up and update 664 * transparency state for each plane. 665 */ 666 drm_for_each_plane(plane, tegra->base.dev) { 667 struct tegra_plane *p = to_tegra_plane(plane); 668 669 /* skip planes on different CRTCs */ 670 if (p->dc != tegra->dc) 671 continue; 672 673 new = drm_atomic_get_new_plane_state(state->base.state, plane); 674 tegra_state = to_tegra_plane_state(new); 675 676 /* 677 * There is no need to update blending state for the disabled 678 * plane. 679 */ 680 if (new->fb) 681 tegra_plane_update_transparency(p, tegra_state); 682 } 683 684 return 0; 685 } 686 687 int tegra_plane_setup_legacy_state(struct tegra_plane *tegra, 688 struct tegra_plane_state *state) 689 { 690 int err; 691 692 err = tegra_plane_setup_opacity(tegra, state); 693 if (err < 0) 694 return err; 695 696 err = tegra_plane_setup_transparency(tegra, state); 697 if (err < 0) 698 return err; 699 700 return 0; 701 } 702 703 static const char * const tegra_plane_icc_names[TEGRA_DC_LEGACY_PLANES_NUM] = { 704 "wina", "winb", "winc", NULL, NULL, NULL, "cursor", 705 }; 706 707 int tegra_plane_interconnect_init(struct tegra_plane *plane) 708 { 709 const char *icc_name = tegra_plane_icc_names[plane->index]; 710 struct device *dev = plane->dc->dev; 711 struct tegra_dc *dc = plane->dc; 712 int err; 713 714 if (WARN_ON(plane->index >= TEGRA_DC_LEGACY_PLANES_NUM) || 715 WARN_ON(!tegra_plane_icc_names[plane->index])) 716 return -EINVAL; 717 718 plane->icc_mem = devm_of_icc_get(dev, icc_name); 719 err = PTR_ERR_OR_ZERO(plane->icc_mem); 720 if (err) { 721 dev_err_probe(dev, err, "failed to get %s interconnect\n", 722 icc_name); 723 return err; 724 } 725 726 /* plane B on T20/30 has a dedicated memory client for a 6-tap vertical filter */ 727 if (plane->index == 1 && dc->soc->has_win_b_vfilter_mem_client) { 728 plane->icc_mem_vfilter = devm_of_icc_get(dev, "winb-vfilter"); 729 err = PTR_ERR_OR_ZERO(plane->icc_mem_vfilter); 730 if (err) { 731 dev_err_probe(dev, err, "failed to get %s interconnect\n", 732 "winb-vfilter"); 733 return err; 734 } 735 } 736 737 return 0; 738 } 739