xref: /openbmc/linux/drivers/gpu/drm/tegra/plane.c (revision 2bdd5238)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2017 NVIDIA CORPORATION.  All rights reserved.
4  */
5 
6 #include <linux/iommu.h>
7 #include <linux/interconnect.h>
8 
9 #include <drm/drm_atomic.h>
10 #include <drm/drm_atomic_helper.h>
11 #include <drm/drm_fourcc.h>
12 #include <drm/drm_gem_atomic_helper.h>
13 #include <drm/drm_plane_helper.h>
14 
15 #include "dc.h"
16 #include "plane.h"
17 
18 static void tegra_plane_destroy(struct drm_plane *plane)
19 {
20 	struct tegra_plane *p = to_tegra_plane(plane);
21 
22 	drm_plane_cleanup(plane);
23 	kfree(p);
24 }
25 
26 static void tegra_plane_reset(struct drm_plane *plane)
27 {
28 	struct tegra_plane *p = to_tegra_plane(plane);
29 	struct tegra_plane_state *state;
30 	unsigned int i;
31 
32 	if (plane->state)
33 		__drm_atomic_helper_plane_destroy_state(plane->state);
34 
35 	kfree(plane->state);
36 	plane->state = NULL;
37 
38 	state = kzalloc(sizeof(*state), GFP_KERNEL);
39 	if (state) {
40 		plane->state = &state->base;
41 		plane->state->plane = plane;
42 		plane->state->zpos = p->index;
43 		plane->state->normalized_zpos = p->index;
44 
45 		for (i = 0; i < 3; i++)
46 			state->iova[i] = DMA_MAPPING_ERROR;
47 	}
48 }
49 
50 static struct drm_plane_state *
51 tegra_plane_atomic_duplicate_state(struct drm_plane *plane)
52 {
53 	struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
54 	struct tegra_plane_state *copy;
55 	unsigned int i;
56 
57 	copy = kmalloc(sizeof(*copy), GFP_KERNEL);
58 	if (!copy)
59 		return NULL;
60 
61 	__drm_atomic_helper_plane_duplicate_state(plane, &copy->base);
62 	copy->tiling = state->tiling;
63 	copy->format = state->format;
64 	copy->swap = state->swap;
65 	copy->reflect_x = state->reflect_x;
66 	copy->reflect_y = state->reflect_y;
67 	copy->opaque = state->opaque;
68 	copy->total_peak_memory_bandwidth = state->total_peak_memory_bandwidth;
69 	copy->peak_memory_bandwidth = state->peak_memory_bandwidth;
70 	copy->avg_memory_bandwidth = state->avg_memory_bandwidth;
71 
72 	for (i = 0; i < 2; i++)
73 		copy->blending[i] = state->blending[i];
74 
75 	for (i = 0; i < 3; i++) {
76 		copy->iova[i] = DMA_MAPPING_ERROR;
77 		copy->sgt[i] = NULL;
78 	}
79 
80 	return &copy->base;
81 }
82 
83 static void tegra_plane_atomic_destroy_state(struct drm_plane *plane,
84 					     struct drm_plane_state *state)
85 {
86 	__drm_atomic_helper_plane_destroy_state(state);
87 	kfree(state);
88 }
89 
90 static bool tegra_plane_supports_sector_layout(struct drm_plane *plane)
91 {
92 	struct drm_crtc *crtc;
93 
94 	drm_for_each_crtc(crtc, plane->dev) {
95 		if (plane->possible_crtcs & drm_crtc_mask(crtc)) {
96 			struct tegra_dc *dc = to_tegra_dc(crtc);
97 
98 			if (!dc->soc->supports_sector_layout)
99 				return false;
100 		}
101 	}
102 
103 	return true;
104 }
105 
106 static bool tegra_plane_format_mod_supported(struct drm_plane *plane,
107 					     uint32_t format,
108 					     uint64_t modifier)
109 {
110 	const struct drm_format_info *info = drm_format_info(format);
111 
112 	if (modifier == DRM_FORMAT_MOD_LINEAR)
113 		return true;
114 
115 	/* check for the sector layout bit */
116 	if ((modifier >> 56) == DRM_FORMAT_MOD_VENDOR_NVIDIA) {
117 		if (modifier & DRM_FORMAT_MOD_NVIDIA_SECTOR_LAYOUT) {
118 			if (!tegra_plane_supports_sector_layout(plane))
119 				return false;
120 		}
121 	}
122 
123 	if (info->num_planes == 1)
124 		return true;
125 
126 	return false;
127 }
128 
129 const struct drm_plane_funcs tegra_plane_funcs = {
130 	.update_plane = drm_atomic_helper_update_plane,
131 	.disable_plane = drm_atomic_helper_disable_plane,
132 	.destroy = tegra_plane_destroy,
133 	.reset = tegra_plane_reset,
134 	.atomic_duplicate_state = tegra_plane_atomic_duplicate_state,
135 	.atomic_destroy_state = tegra_plane_atomic_destroy_state,
136 	.format_mod_supported = tegra_plane_format_mod_supported,
137 };
138 
139 static int tegra_dc_pin(struct tegra_dc *dc, struct tegra_plane_state *state)
140 {
141 	struct iommu_domain *domain = iommu_get_domain_for_dev(dc->dev);
142 	unsigned int i;
143 	int err;
144 
145 	for (i = 0; i < state->base.fb->format->num_planes; i++) {
146 		struct tegra_bo *bo = tegra_fb_get_plane(state->base.fb, i);
147 		dma_addr_t phys_addr, *phys;
148 		struct sg_table *sgt;
149 
150 		/*
151 		 * If we're not attached to a domain, we already stored the
152 		 * physical address when the buffer was allocated. If we're
153 		 * part of a group that's shared between all display
154 		 * controllers, we've also already mapped the framebuffer
155 		 * through the SMMU. In both cases we can short-circuit the
156 		 * code below and retrieve the stored IOV address.
157 		 */
158 		if (!domain || dc->client.group)
159 			phys = &phys_addr;
160 		else
161 			phys = NULL;
162 
163 		sgt = host1x_bo_pin(dc->dev, &bo->base, phys);
164 		if (IS_ERR(sgt)) {
165 			err = PTR_ERR(sgt);
166 			goto unpin;
167 		}
168 
169 		if (sgt) {
170 			err = dma_map_sgtable(dc->dev, sgt, DMA_TO_DEVICE, 0);
171 			if (err)
172 				goto unpin;
173 
174 			/*
175 			 * The display controller needs contiguous memory, so
176 			 * fail if the buffer is discontiguous and we fail to
177 			 * map its SG table to a single contiguous chunk of
178 			 * I/O virtual memory.
179 			 */
180 			if (sgt->nents > 1) {
181 				err = -EINVAL;
182 				goto unpin;
183 			}
184 
185 			state->iova[i] = sg_dma_address(sgt->sgl);
186 			state->sgt[i] = sgt;
187 		} else {
188 			state->iova[i] = phys_addr;
189 		}
190 	}
191 
192 	return 0;
193 
194 unpin:
195 	dev_err(dc->dev, "failed to map plane %u: %d\n", i, err);
196 
197 	while (i--) {
198 		struct tegra_bo *bo = tegra_fb_get_plane(state->base.fb, i);
199 		struct sg_table *sgt = state->sgt[i];
200 
201 		if (sgt)
202 			dma_unmap_sgtable(dc->dev, sgt, DMA_TO_DEVICE, 0);
203 
204 		host1x_bo_unpin(dc->dev, &bo->base, sgt);
205 		state->iova[i] = DMA_MAPPING_ERROR;
206 		state->sgt[i] = NULL;
207 	}
208 
209 	return err;
210 }
211 
212 static void tegra_dc_unpin(struct tegra_dc *dc, struct tegra_plane_state *state)
213 {
214 	unsigned int i;
215 
216 	for (i = 0; i < state->base.fb->format->num_planes; i++) {
217 		struct tegra_bo *bo = tegra_fb_get_plane(state->base.fb, i);
218 		struct sg_table *sgt = state->sgt[i];
219 
220 		if (sgt)
221 			dma_unmap_sgtable(dc->dev, sgt, DMA_TO_DEVICE, 0);
222 
223 		host1x_bo_unpin(dc->dev, &bo->base, sgt);
224 		state->iova[i] = DMA_MAPPING_ERROR;
225 		state->sgt[i] = NULL;
226 	}
227 }
228 
229 int tegra_plane_prepare_fb(struct drm_plane *plane,
230 			   struct drm_plane_state *state)
231 {
232 	struct tegra_dc *dc = to_tegra_dc(state->crtc);
233 
234 	if (!state->fb)
235 		return 0;
236 
237 	drm_gem_plane_helper_prepare_fb(plane, state);
238 
239 	return tegra_dc_pin(dc, to_tegra_plane_state(state));
240 }
241 
242 void tegra_plane_cleanup_fb(struct drm_plane *plane,
243 			    struct drm_plane_state *state)
244 {
245 	struct tegra_dc *dc = to_tegra_dc(state->crtc);
246 
247 	if (dc)
248 		tegra_dc_unpin(dc, to_tegra_plane_state(state));
249 }
250 
251 static int tegra_plane_calculate_memory_bandwidth(struct drm_plane_state *state)
252 {
253 	struct tegra_plane_state *tegra_state = to_tegra_plane_state(state);
254 	unsigned int i, bpp, dst_w, dst_h, src_w, src_h, mul;
255 	const struct tegra_dc_soc_info *soc;
256 	const struct drm_format_info *fmt;
257 	struct drm_crtc_state *crtc_state;
258 	u64 avg_bandwidth, peak_bandwidth;
259 
260 	if (!state->visible)
261 		return 0;
262 
263 	crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc);
264 	if (!crtc_state)
265 		return -EINVAL;
266 
267 	src_w = drm_rect_width(&state->src) >> 16;
268 	src_h = drm_rect_height(&state->src) >> 16;
269 	dst_w = drm_rect_width(&state->dst);
270 	dst_h = drm_rect_height(&state->dst);
271 
272 	fmt = state->fb->format;
273 	soc = to_tegra_dc(state->crtc)->soc;
274 
275 	/*
276 	 * Note that real memory bandwidth vary depending on format and
277 	 * memory layout, we are not taking that into account because small
278 	 * estimation error isn't important since bandwidth is rounded up
279 	 * anyway.
280 	 */
281 	for (i = 0, bpp = 0; i < fmt->num_planes; i++) {
282 		unsigned int bpp_plane = fmt->cpp[i] * 8;
283 
284 		/*
285 		 * Sub-sampling is relevant for chroma planes only and vertical
286 		 * readouts are not cached, hence only horizontal sub-sampling
287 		 * matters.
288 		 */
289 		if (i > 0)
290 			bpp_plane /= fmt->hsub;
291 
292 		bpp += bpp_plane;
293 	}
294 
295 	/* average bandwidth in kbytes/sec */
296 	avg_bandwidth  = min(src_w, dst_w) * min(src_h, dst_h);
297 	avg_bandwidth *= drm_mode_vrefresh(&crtc_state->adjusted_mode);
298 	avg_bandwidth  = DIV_ROUND_UP(avg_bandwidth * bpp, 8) + 999;
299 	do_div(avg_bandwidth, 1000);
300 
301 	/* mode.clock in kHz, peak bandwidth in kbytes/sec */
302 	peak_bandwidth = DIV_ROUND_UP(crtc_state->adjusted_mode.clock * bpp, 8);
303 
304 	/*
305 	 * Tegra30/114 Memory Controller can't interleave DC memory requests
306 	 * for the tiled windows because DC uses 16-bytes atom, while DDR3
307 	 * uses 32-bytes atom.  Hence there is x2 memory overfetch for tiled
308 	 * framebuffer and DDR3 on these SoCs.
309 	 */
310 	if (soc->plane_tiled_memory_bandwidth_x2 &&
311 	    tegra_state->tiling.mode == TEGRA_BO_TILING_MODE_TILED)
312 		mul = 2;
313 	else
314 		mul = 1;
315 
316 	/* ICC bandwidth in kbytes/sec */
317 	tegra_state->peak_memory_bandwidth = kBps_to_icc(peak_bandwidth) * mul;
318 	tegra_state->avg_memory_bandwidth  = kBps_to_icc(avg_bandwidth)  * mul;
319 
320 	return 0;
321 }
322 
323 int tegra_plane_state_add(struct tegra_plane *plane,
324 			  struct drm_plane_state *state)
325 {
326 	struct drm_crtc_state *crtc_state;
327 	struct tegra_dc_state *tegra;
328 	int err;
329 
330 	/* Propagate errors from allocation or locking failures. */
331 	crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
332 	if (IS_ERR(crtc_state))
333 		return PTR_ERR(crtc_state);
334 
335 	/* Check plane state for visibility and calculate clipping bounds */
336 	err = drm_atomic_helper_check_plane_state(state, crtc_state,
337 						  0, INT_MAX, true, true);
338 	if (err < 0)
339 		return err;
340 
341 	err = tegra_plane_calculate_memory_bandwidth(state);
342 	if (err < 0)
343 		return err;
344 
345 	tegra = to_dc_state(crtc_state);
346 
347 	tegra->planes |= WIN_A_ACT_REQ << plane->index;
348 
349 	return 0;
350 }
351 
352 int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap)
353 {
354 	/* assume no swapping of fetched data */
355 	if (swap)
356 		*swap = BYTE_SWAP_NOSWAP;
357 
358 	switch (fourcc) {
359 	case DRM_FORMAT_ARGB4444:
360 		*format = WIN_COLOR_DEPTH_B4G4R4A4;
361 		break;
362 
363 	case DRM_FORMAT_ARGB1555:
364 		*format = WIN_COLOR_DEPTH_B5G5R5A1;
365 		break;
366 
367 	case DRM_FORMAT_RGB565:
368 		*format = WIN_COLOR_DEPTH_B5G6R5;
369 		break;
370 
371 	case DRM_FORMAT_RGBA5551:
372 		*format = WIN_COLOR_DEPTH_A1B5G5R5;
373 		break;
374 
375 	case DRM_FORMAT_ARGB8888:
376 		*format = WIN_COLOR_DEPTH_B8G8R8A8;
377 		break;
378 
379 	case DRM_FORMAT_ABGR8888:
380 		*format = WIN_COLOR_DEPTH_R8G8B8A8;
381 		break;
382 
383 	case DRM_FORMAT_ABGR4444:
384 		*format = WIN_COLOR_DEPTH_R4G4B4A4;
385 		break;
386 
387 	case DRM_FORMAT_ABGR1555:
388 		*format = WIN_COLOR_DEPTH_R5G5B5A;
389 		break;
390 
391 	case DRM_FORMAT_BGRA5551:
392 		*format = WIN_COLOR_DEPTH_AR5G5B5;
393 		break;
394 
395 	case DRM_FORMAT_XRGB1555:
396 		*format = WIN_COLOR_DEPTH_B5G5R5X1;
397 		break;
398 
399 	case DRM_FORMAT_RGBX5551:
400 		*format = WIN_COLOR_DEPTH_X1B5G5R5;
401 		break;
402 
403 	case DRM_FORMAT_XBGR1555:
404 		*format = WIN_COLOR_DEPTH_R5G5B5X1;
405 		break;
406 
407 	case DRM_FORMAT_BGRX5551:
408 		*format = WIN_COLOR_DEPTH_X1R5G5B5;
409 		break;
410 
411 	case DRM_FORMAT_BGR565:
412 		*format = WIN_COLOR_DEPTH_R5G6B5;
413 		break;
414 
415 	case DRM_FORMAT_BGRA8888:
416 		*format = WIN_COLOR_DEPTH_A8R8G8B8;
417 		break;
418 
419 	case DRM_FORMAT_RGBA8888:
420 		*format = WIN_COLOR_DEPTH_A8B8G8R8;
421 		break;
422 
423 	case DRM_FORMAT_XRGB8888:
424 		*format = WIN_COLOR_DEPTH_B8G8R8X8;
425 		break;
426 
427 	case DRM_FORMAT_XBGR8888:
428 		*format = WIN_COLOR_DEPTH_R8G8B8X8;
429 		break;
430 
431 	case DRM_FORMAT_UYVY:
432 		*format = WIN_COLOR_DEPTH_YCbCr422;
433 		break;
434 
435 	case DRM_FORMAT_YUYV:
436 		if (!swap)
437 			return -EINVAL;
438 
439 		*format = WIN_COLOR_DEPTH_YCbCr422;
440 		*swap = BYTE_SWAP_SWAP2;
441 		break;
442 
443 	case DRM_FORMAT_YUV420:
444 		*format = WIN_COLOR_DEPTH_YCbCr420P;
445 		break;
446 
447 	case DRM_FORMAT_YUV422:
448 		*format = WIN_COLOR_DEPTH_YCbCr422P;
449 		break;
450 
451 	default:
452 		return -EINVAL;
453 	}
454 
455 	return 0;
456 }
457 
458 bool tegra_plane_format_is_indexed(unsigned int format)
459 {
460 	switch (format) {
461 	case WIN_COLOR_DEPTH_P1:
462 	case WIN_COLOR_DEPTH_P2:
463 	case WIN_COLOR_DEPTH_P4:
464 	case WIN_COLOR_DEPTH_P8:
465 		return true;
466 	}
467 
468 	return false;
469 }
470 
471 bool tegra_plane_format_is_yuv(unsigned int format, bool *planar, unsigned int *bpc)
472 {
473 	switch (format) {
474 	case WIN_COLOR_DEPTH_YCbCr422:
475 	case WIN_COLOR_DEPTH_YUV422:
476 		if (planar)
477 			*planar = false;
478 
479 		if (bpc)
480 			*bpc = 8;
481 
482 		return true;
483 
484 	case WIN_COLOR_DEPTH_YCbCr420P:
485 	case WIN_COLOR_DEPTH_YUV420P:
486 	case WIN_COLOR_DEPTH_YCbCr422P:
487 	case WIN_COLOR_DEPTH_YUV422P:
488 	case WIN_COLOR_DEPTH_YCbCr422R:
489 	case WIN_COLOR_DEPTH_YUV422R:
490 	case WIN_COLOR_DEPTH_YCbCr422RA:
491 	case WIN_COLOR_DEPTH_YUV422RA:
492 		if (planar)
493 			*planar = true;
494 
495 		if (bpc)
496 			*bpc = 8;
497 
498 		return true;
499 	}
500 
501 	if (planar)
502 		*planar = false;
503 
504 	return false;
505 }
506 
507 static bool __drm_format_has_alpha(u32 format)
508 {
509 	switch (format) {
510 	case DRM_FORMAT_ARGB1555:
511 	case DRM_FORMAT_RGBA5551:
512 	case DRM_FORMAT_ABGR8888:
513 	case DRM_FORMAT_ARGB8888:
514 		return true;
515 	}
516 
517 	return false;
518 }
519 
520 static int tegra_plane_format_get_alpha(unsigned int opaque,
521 					unsigned int *alpha)
522 {
523 	if (tegra_plane_format_is_yuv(opaque, NULL, NULL)) {
524 		*alpha = opaque;
525 		return 0;
526 	}
527 
528 	switch (opaque) {
529 	case WIN_COLOR_DEPTH_B5G5R5X1:
530 		*alpha = WIN_COLOR_DEPTH_B5G5R5A1;
531 		return 0;
532 
533 	case WIN_COLOR_DEPTH_X1B5G5R5:
534 		*alpha = WIN_COLOR_DEPTH_A1B5G5R5;
535 		return 0;
536 
537 	case WIN_COLOR_DEPTH_R8G8B8X8:
538 		*alpha = WIN_COLOR_DEPTH_R8G8B8A8;
539 		return 0;
540 
541 	case WIN_COLOR_DEPTH_B8G8R8X8:
542 		*alpha = WIN_COLOR_DEPTH_B8G8R8A8;
543 		return 0;
544 
545 	case WIN_COLOR_DEPTH_B5G6R5:
546 		*alpha = opaque;
547 		return 0;
548 	}
549 
550 	return -EINVAL;
551 }
552 
553 /*
554  * This is applicable to Tegra20 and Tegra30 only where the opaque formats can
555  * be emulated using the alpha formats and alpha blending disabled.
556  */
557 static int tegra_plane_setup_opacity(struct tegra_plane *tegra,
558 				     struct tegra_plane_state *state)
559 {
560 	unsigned int format;
561 	int err;
562 
563 	switch (state->format) {
564 	case WIN_COLOR_DEPTH_B5G5R5A1:
565 	case WIN_COLOR_DEPTH_A1B5G5R5:
566 	case WIN_COLOR_DEPTH_R8G8B8A8:
567 	case WIN_COLOR_DEPTH_B8G8R8A8:
568 		state->opaque = false;
569 		break;
570 
571 	default:
572 		err = tegra_plane_format_get_alpha(state->format, &format);
573 		if (err < 0)
574 			return err;
575 
576 		state->format = format;
577 		state->opaque = true;
578 		break;
579 	}
580 
581 	return 0;
582 }
583 
584 static int tegra_plane_check_transparency(struct tegra_plane *tegra,
585 					  struct tegra_plane_state *state)
586 {
587 	struct drm_plane_state *old, *plane_state;
588 	struct drm_plane *plane;
589 
590 	old = drm_atomic_get_old_plane_state(state->base.state, &tegra->base);
591 
592 	/* check if zpos / transparency changed */
593 	if (old->normalized_zpos == state->base.normalized_zpos &&
594 	    to_tegra_plane_state(old)->opaque == state->opaque)
595 		return 0;
596 
597 	/* include all sibling planes into this commit */
598 	drm_for_each_plane(plane, tegra->base.dev) {
599 		struct tegra_plane *p = to_tegra_plane(plane);
600 
601 		/* skip this plane and planes on different CRTCs */
602 		if (p == tegra || p->dc != tegra->dc)
603 			continue;
604 
605 		plane_state = drm_atomic_get_plane_state(state->base.state,
606 							 plane);
607 		if (IS_ERR(plane_state))
608 			return PTR_ERR(plane_state);
609 	}
610 
611 	return 1;
612 }
613 
614 static unsigned int tegra_plane_get_overlap_index(struct tegra_plane *plane,
615 						  struct tegra_plane *other)
616 {
617 	unsigned int index = 0, i;
618 
619 	WARN_ON(plane == other);
620 
621 	for (i = 0; i < 3; i++) {
622 		if (i == plane->index)
623 			continue;
624 
625 		if (i == other->index)
626 			break;
627 
628 		index++;
629 	}
630 
631 	return index;
632 }
633 
634 static void tegra_plane_update_transparency(struct tegra_plane *tegra,
635 					    struct tegra_plane_state *state)
636 {
637 	struct drm_plane_state *new;
638 	struct drm_plane *plane;
639 	unsigned int i;
640 
641 	for_each_new_plane_in_state(state->base.state, plane, new, i) {
642 		struct tegra_plane *p = to_tegra_plane(plane);
643 		unsigned index;
644 
645 		/* skip this plane and planes on different CRTCs */
646 		if (p == tegra || p->dc != tegra->dc)
647 			continue;
648 
649 		index = tegra_plane_get_overlap_index(tegra, p);
650 
651 		if (new->fb && __drm_format_has_alpha(new->fb->format->format))
652 			state->blending[index].alpha = true;
653 		else
654 			state->blending[index].alpha = false;
655 
656 		if (new->normalized_zpos > state->base.normalized_zpos)
657 			state->blending[index].top = true;
658 		else
659 			state->blending[index].top = false;
660 
661 		/*
662 		 * Missing framebuffer means that plane is disabled, in this
663 		 * case mark B / C window as top to be able to differentiate
664 		 * windows indices order in regards to zPos for the middle
665 		 * window X / Y registers programming.
666 		 */
667 		if (!new->fb)
668 			state->blending[index].top = (index == 1);
669 	}
670 }
671 
672 static int tegra_plane_setup_transparency(struct tegra_plane *tegra,
673 					  struct tegra_plane_state *state)
674 {
675 	struct tegra_plane_state *tegra_state;
676 	struct drm_plane_state *new;
677 	struct drm_plane *plane;
678 	int err;
679 
680 	/*
681 	 * If planes zpos / transparency changed, sibling planes blending
682 	 * state may require adjustment and in this case they will be included
683 	 * into this atom commit, otherwise blending state is unchanged.
684 	 */
685 	err = tegra_plane_check_transparency(tegra, state);
686 	if (err <= 0)
687 		return err;
688 
689 	/*
690 	 * All planes are now in the atomic state, walk them up and update
691 	 * transparency state for each plane.
692 	 */
693 	drm_for_each_plane(plane, tegra->base.dev) {
694 		struct tegra_plane *p = to_tegra_plane(plane);
695 
696 		/* skip planes on different CRTCs */
697 		if (p->dc != tegra->dc)
698 			continue;
699 
700 		new = drm_atomic_get_new_plane_state(state->base.state, plane);
701 		tegra_state = to_tegra_plane_state(new);
702 
703 		/*
704 		 * There is no need to update blending state for the disabled
705 		 * plane.
706 		 */
707 		if (new->fb)
708 			tegra_plane_update_transparency(p, tegra_state);
709 	}
710 
711 	return 0;
712 }
713 
714 int tegra_plane_setup_legacy_state(struct tegra_plane *tegra,
715 				   struct tegra_plane_state *state)
716 {
717 	int err;
718 
719 	err = tegra_plane_setup_opacity(tegra, state);
720 	if (err < 0)
721 		return err;
722 
723 	err = tegra_plane_setup_transparency(tegra, state);
724 	if (err < 0)
725 		return err;
726 
727 	return 0;
728 }
729 
730 static const char * const tegra_plane_icc_names[TEGRA_DC_LEGACY_PLANES_NUM] = {
731 	"wina", "winb", "winc", NULL, NULL, NULL, "cursor",
732 };
733 
734 int tegra_plane_interconnect_init(struct tegra_plane *plane)
735 {
736 	const char *icc_name = tegra_plane_icc_names[plane->index];
737 	struct device *dev = plane->dc->dev;
738 	struct tegra_dc *dc = plane->dc;
739 	int err;
740 
741 	if (WARN_ON(plane->index >= TEGRA_DC_LEGACY_PLANES_NUM) ||
742 	    WARN_ON(!tegra_plane_icc_names[plane->index]))
743 		return -EINVAL;
744 
745 	plane->icc_mem = devm_of_icc_get(dev, icc_name);
746 	err = PTR_ERR_OR_ZERO(plane->icc_mem);
747 	if (err) {
748 		dev_err_probe(dev, err, "failed to get %s interconnect\n",
749 			      icc_name);
750 		return err;
751 	}
752 
753 	/* plane B on T20/30 has a dedicated memory client for a 6-tap vertical filter */
754 	if (plane->index == 1 && dc->soc->has_win_b_vfilter_mem_client) {
755 		plane->icc_mem_vfilter = devm_of_icc_get(dev, "winb-vfilter");
756 		err = PTR_ERR_OR_ZERO(plane->icc_mem_vfilter);
757 		if (err) {
758 			dev_err_probe(dev, err, "failed to get %s interconnect\n",
759 				      "winb-vfilter");
760 			return err;
761 		}
762 	}
763 
764 	return 0;
765 }
766