1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015-2021, NVIDIA Corporation. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/host1x.h> 9 #include <linux/iommu.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/reset.h> 17 18 #include <soc/tegra/pmc.h> 19 20 #include "drm.h" 21 #include "falcon.h" 22 #include "vic.h" 23 24 struct nvdec_config { 25 const char *firmware; 26 unsigned int version; 27 bool supports_sid; 28 }; 29 30 struct nvdec { 31 struct falcon falcon; 32 33 void __iomem *regs; 34 struct tegra_drm_client client; 35 struct host1x_channel *channel; 36 struct device *dev; 37 struct clk *clk; 38 39 /* Platform configuration */ 40 const struct nvdec_config *config; 41 }; 42 43 static inline struct nvdec *to_nvdec(struct tegra_drm_client *client) 44 { 45 return container_of(client, struct nvdec, client); 46 } 47 48 static void nvdec_writel(struct nvdec *nvdec, u32 value, unsigned int offset) 49 { 50 writel(value, nvdec->regs + offset); 51 } 52 53 static int nvdec_boot(struct nvdec *nvdec) 54 { 55 #ifdef CONFIG_IOMMU_API 56 struct iommu_fwspec *spec = dev_iommu_fwspec_get(nvdec->dev); 57 #endif 58 int err; 59 60 #ifdef CONFIG_IOMMU_API 61 if (nvdec->config->supports_sid && spec) { 62 u32 value; 63 64 value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | TRANSCFG_ATT(0, TRANSCFG_SID_HW); 65 nvdec_writel(nvdec, value, VIC_TFBIF_TRANSCFG); 66 67 if (spec->num_ids > 0) { 68 value = spec->ids[0] & 0xffff; 69 70 nvdec_writel(nvdec, value, VIC_THI_STREAMID0); 71 nvdec_writel(nvdec, value, VIC_THI_STREAMID1); 72 } 73 } 74 #endif 75 76 err = falcon_boot(&nvdec->falcon); 77 if (err < 0) 78 return err; 79 80 err = falcon_wait_idle(&nvdec->falcon); 81 if (err < 0) { 82 dev_err(nvdec->dev, "falcon boot timed out\n"); 83 return err; 84 } 85 86 return 0; 87 } 88 89 static int nvdec_init(struct host1x_client *client) 90 { 91 struct tegra_drm_client *drm = host1x_to_drm_client(client); 92 struct drm_device *dev = dev_get_drvdata(client->host); 93 struct tegra_drm *tegra = dev->dev_private; 94 struct nvdec *nvdec = to_nvdec(drm); 95 int err; 96 97 err = host1x_client_iommu_attach(client); 98 if (err < 0 && err != -ENODEV) { 99 dev_err(nvdec->dev, "failed to attach to domain: %d\n", err); 100 return err; 101 } 102 103 nvdec->channel = host1x_channel_request(client); 104 if (!nvdec->channel) { 105 err = -ENOMEM; 106 goto detach; 107 } 108 109 client->syncpts[0] = host1x_syncpt_request(client, 0); 110 if (!client->syncpts[0]) { 111 err = -ENOMEM; 112 goto free_channel; 113 } 114 115 err = tegra_drm_register_client(tegra, drm); 116 if (err < 0) 117 goto free_syncpt; 118 119 /* 120 * Inherit the DMA parameters (such as maximum segment size) from the 121 * parent host1x device. 122 */ 123 client->dev->dma_parms = client->host->dma_parms; 124 125 return 0; 126 127 free_syncpt: 128 host1x_syncpt_put(client->syncpts[0]); 129 free_channel: 130 host1x_channel_put(nvdec->channel); 131 detach: 132 host1x_client_iommu_detach(client); 133 134 return err; 135 } 136 137 static int nvdec_exit(struct host1x_client *client) 138 { 139 struct tegra_drm_client *drm = host1x_to_drm_client(client); 140 struct drm_device *dev = dev_get_drvdata(client->host); 141 struct tegra_drm *tegra = dev->dev_private; 142 struct nvdec *nvdec = to_nvdec(drm); 143 int err; 144 145 /* avoid a dangling pointer just in case this disappears */ 146 client->dev->dma_parms = NULL; 147 148 err = tegra_drm_unregister_client(tegra, drm); 149 if (err < 0) 150 return err; 151 152 host1x_syncpt_put(client->syncpts[0]); 153 host1x_channel_put(nvdec->channel); 154 host1x_client_iommu_detach(client); 155 156 if (client->group) { 157 dma_unmap_single(nvdec->dev, nvdec->falcon.firmware.phys, 158 nvdec->falcon.firmware.size, DMA_TO_DEVICE); 159 tegra_drm_free(tegra, nvdec->falcon.firmware.size, 160 nvdec->falcon.firmware.virt, 161 nvdec->falcon.firmware.iova); 162 } else { 163 dma_free_coherent(nvdec->dev, nvdec->falcon.firmware.size, 164 nvdec->falcon.firmware.virt, 165 nvdec->falcon.firmware.iova); 166 } 167 168 return 0; 169 } 170 171 static const struct host1x_client_ops nvdec_client_ops = { 172 .init = nvdec_init, 173 .exit = nvdec_exit, 174 }; 175 176 static int nvdec_load_firmware(struct nvdec *nvdec) 177 { 178 struct host1x_client *client = &nvdec->client.base; 179 struct tegra_drm *tegra = nvdec->client.drm; 180 dma_addr_t iova; 181 size_t size; 182 void *virt; 183 int err; 184 185 if (nvdec->falcon.firmware.virt) 186 return 0; 187 188 err = falcon_read_firmware(&nvdec->falcon, nvdec->config->firmware); 189 if (err < 0) 190 return err; 191 192 size = nvdec->falcon.firmware.size; 193 194 if (!client->group) { 195 virt = dma_alloc_coherent(nvdec->dev, size, &iova, GFP_KERNEL); 196 197 err = dma_mapping_error(nvdec->dev, iova); 198 if (err < 0) 199 return err; 200 } else { 201 virt = tegra_drm_alloc(tegra, size, &iova); 202 } 203 204 nvdec->falcon.firmware.virt = virt; 205 nvdec->falcon.firmware.iova = iova; 206 207 err = falcon_load_firmware(&nvdec->falcon); 208 if (err < 0) 209 goto cleanup; 210 211 /* 212 * In this case we have received an IOVA from the shared domain, so we 213 * need to make sure to get the physical address so that the DMA API 214 * knows what memory pages to flush the cache for. 215 */ 216 if (client->group) { 217 dma_addr_t phys; 218 219 phys = dma_map_single(nvdec->dev, virt, size, DMA_TO_DEVICE); 220 221 err = dma_mapping_error(nvdec->dev, phys); 222 if (err < 0) 223 goto cleanup; 224 225 nvdec->falcon.firmware.phys = phys; 226 } 227 228 return 0; 229 230 cleanup: 231 if (!client->group) 232 dma_free_coherent(nvdec->dev, size, virt, iova); 233 else 234 tegra_drm_free(tegra, size, virt, iova); 235 236 return err; 237 } 238 239 240 static int nvdec_runtime_resume(struct device *dev) 241 { 242 struct nvdec *nvdec = dev_get_drvdata(dev); 243 int err; 244 245 err = clk_prepare_enable(nvdec->clk); 246 if (err < 0) 247 return err; 248 249 usleep_range(10, 20); 250 251 err = nvdec_load_firmware(nvdec); 252 if (err < 0) 253 goto disable; 254 255 err = nvdec_boot(nvdec); 256 if (err < 0) 257 goto disable; 258 259 return 0; 260 261 disable: 262 clk_disable_unprepare(nvdec->clk); 263 return err; 264 } 265 266 static int nvdec_runtime_suspend(struct device *dev) 267 { 268 struct nvdec *nvdec = dev_get_drvdata(dev); 269 270 clk_disable_unprepare(nvdec->clk); 271 272 return 0; 273 } 274 275 static int nvdec_open_channel(struct tegra_drm_client *client, 276 struct tegra_drm_context *context) 277 { 278 struct nvdec *nvdec = to_nvdec(client); 279 int err; 280 281 err = pm_runtime_get_sync(nvdec->dev); 282 if (err < 0) { 283 pm_runtime_put(nvdec->dev); 284 return err; 285 } 286 287 context->channel = host1x_channel_get(nvdec->channel); 288 if (!context->channel) { 289 pm_runtime_put(nvdec->dev); 290 return -ENOMEM; 291 } 292 293 return 0; 294 } 295 296 static void nvdec_close_channel(struct tegra_drm_context *context) 297 { 298 struct nvdec *nvdec = to_nvdec(context->client); 299 300 host1x_channel_put(context->channel); 301 pm_runtime_put(nvdec->dev); 302 } 303 304 static const struct tegra_drm_client_ops nvdec_ops = { 305 .open_channel = nvdec_open_channel, 306 .close_channel = nvdec_close_channel, 307 .submit = tegra_drm_submit, 308 }; 309 310 #define NVIDIA_TEGRA_210_NVDEC_FIRMWARE "nvidia/tegra210/nvdec.bin" 311 312 static const struct nvdec_config nvdec_t210_config = { 313 .firmware = NVIDIA_TEGRA_210_NVDEC_FIRMWARE, 314 .version = 0x21, 315 .supports_sid = false, 316 }; 317 318 #define NVIDIA_TEGRA_186_NVDEC_FIRMWARE "nvidia/tegra186/nvdec.bin" 319 320 static const struct nvdec_config nvdec_t186_config = { 321 .firmware = NVIDIA_TEGRA_186_NVDEC_FIRMWARE, 322 .version = 0x18, 323 .supports_sid = true, 324 }; 325 326 #define NVIDIA_TEGRA_194_NVDEC_FIRMWARE "nvidia/tegra194/nvdec.bin" 327 328 static const struct nvdec_config nvdec_t194_config = { 329 .firmware = NVIDIA_TEGRA_194_NVDEC_FIRMWARE, 330 .version = 0x19, 331 .supports_sid = true, 332 }; 333 334 static const struct of_device_id tegra_nvdec_of_match[] = { 335 { .compatible = "nvidia,tegra210-nvdec", .data = &nvdec_t210_config }, 336 { .compatible = "nvidia,tegra186-nvdec", .data = &nvdec_t186_config }, 337 { .compatible = "nvidia,tegra194-nvdec", .data = &nvdec_t194_config }, 338 { }, 339 }; 340 MODULE_DEVICE_TABLE(of, tegra_nvdec_of_match); 341 342 static int nvdec_probe(struct platform_device *pdev) 343 { 344 struct device *dev = &pdev->dev; 345 struct host1x_syncpt **syncpts; 346 struct nvdec *nvdec; 347 u32 host_class; 348 int err; 349 350 /* inherit DMA mask from host1x parent */ 351 err = dma_coerce_mask_and_coherent(dev, *dev->parent->dma_mask); 352 if (err < 0) { 353 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 354 return err; 355 } 356 357 nvdec = devm_kzalloc(dev, sizeof(*nvdec), GFP_KERNEL); 358 if (!nvdec) 359 return -ENOMEM; 360 361 nvdec->config = of_device_get_match_data(dev); 362 363 syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL); 364 if (!syncpts) 365 return -ENOMEM; 366 367 nvdec->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 368 if (IS_ERR(nvdec->regs)) 369 return PTR_ERR(nvdec->regs); 370 371 nvdec->clk = devm_clk_get(dev, NULL); 372 if (IS_ERR(nvdec->clk)) { 373 dev_err(&pdev->dev, "failed to get clock\n"); 374 return PTR_ERR(nvdec->clk); 375 } 376 377 err = clk_set_rate(nvdec->clk, ULONG_MAX); 378 if (err < 0) { 379 dev_err(&pdev->dev, "failed to set clock rate\n"); 380 return err; 381 } 382 383 err = of_property_read_u32(dev->of_node, "nvidia,host1x-class", &host_class); 384 if (err < 0) 385 host_class = HOST1X_CLASS_NVDEC; 386 387 nvdec->falcon.dev = dev; 388 nvdec->falcon.regs = nvdec->regs; 389 390 err = falcon_init(&nvdec->falcon); 391 if (err < 0) 392 return err; 393 394 platform_set_drvdata(pdev, nvdec); 395 396 INIT_LIST_HEAD(&nvdec->client.base.list); 397 nvdec->client.base.ops = &nvdec_client_ops; 398 nvdec->client.base.dev = dev; 399 nvdec->client.base.class = host_class; 400 nvdec->client.base.syncpts = syncpts; 401 nvdec->client.base.num_syncpts = 1; 402 nvdec->dev = dev; 403 404 INIT_LIST_HEAD(&nvdec->client.list); 405 nvdec->client.version = nvdec->config->version; 406 nvdec->client.ops = &nvdec_ops; 407 408 err = host1x_client_register(&nvdec->client.base); 409 if (err < 0) { 410 dev_err(dev, "failed to register host1x client: %d\n", err); 411 goto exit_falcon; 412 } 413 414 pm_runtime_enable(&pdev->dev); 415 pm_runtime_set_autosuspend_delay(&pdev->dev, 500); 416 pm_runtime_use_autosuspend(&pdev->dev); 417 418 return 0; 419 420 exit_falcon: 421 falcon_exit(&nvdec->falcon); 422 423 return err; 424 } 425 426 static int nvdec_remove(struct platform_device *pdev) 427 { 428 struct nvdec *nvdec = platform_get_drvdata(pdev); 429 int err; 430 431 err = host1x_client_unregister(&nvdec->client.base); 432 if (err < 0) { 433 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 434 err); 435 return err; 436 } 437 438 if (pm_runtime_enabled(&pdev->dev)) 439 pm_runtime_disable(&pdev->dev); 440 else 441 nvdec_runtime_suspend(&pdev->dev); 442 443 falcon_exit(&nvdec->falcon); 444 445 return 0; 446 } 447 448 static const struct dev_pm_ops nvdec_pm_ops = { 449 SET_RUNTIME_PM_OPS(nvdec_runtime_suspend, nvdec_runtime_resume, NULL) 450 }; 451 452 struct platform_driver tegra_nvdec_driver = { 453 .driver = { 454 .name = "tegra-nvdec", 455 .of_match_table = tegra_nvdec_of_match, 456 .pm = &nvdec_pm_ops 457 }, 458 .probe = nvdec_probe, 459 .remove = nvdec_remove, 460 }; 461 462 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) 463 MODULE_FIRMWARE(NVIDIA_TEGRA_210_NVDEC_FIRMWARE); 464 #endif 465 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) 466 MODULE_FIRMWARE(NVIDIA_TEGRA_186_NVDEC_FIRMWARE); 467 #endif 468 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) 469 MODULE_FIRMWARE(NVIDIA_TEGRA_194_NVDEC_FIRMWARE); 470 #endif 471