1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015-2021, NVIDIA Corporation. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/host1x.h> 9 #include <linux/iommu.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/reset.h> 17 18 #include <soc/tegra/pmc.h> 19 20 #include "drm.h" 21 #include "falcon.h" 22 #include "vic.h" 23 24 struct nvdec_config { 25 const char *firmware; 26 unsigned int version; 27 bool supports_sid; 28 }; 29 30 struct nvdec { 31 struct falcon falcon; 32 33 void __iomem *regs; 34 struct tegra_drm_client client; 35 struct host1x_channel *channel; 36 struct device *dev; 37 struct clk *clk; 38 39 /* Platform configuration */ 40 const struct nvdec_config *config; 41 }; 42 43 static inline struct nvdec *to_nvdec(struct tegra_drm_client *client) 44 { 45 return container_of(client, struct nvdec, client); 46 } 47 48 static inline void nvdec_writel(struct nvdec *nvdec, u32 value, 49 unsigned int offset) 50 { 51 writel(value, nvdec->regs + offset); 52 } 53 54 static int nvdec_boot(struct nvdec *nvdec) 55 { 56 #ifdef CONFIG_IOMMU_API 57 struct iommu_fwspec *spec = dev_iommu_fwspec_get(nvdec->dev); 58 #endif 59 int err; 60 61 #ifdef CONFIG_IOMMU_API 62 if (nvdec->config->supports_sid && spec) { 63 u32 value; 64 65 value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | TRANSCFG_ATT(0, TRANSCFG_SID_HW); 66 nvdec_writel(nvdec, value, VIC_TFBIF_TRANSCFG); 67 68 if (spec->num_ids > 0) { 69 value = spec->ids[0] & 0xffff; 70 71 nvdec_writel(nvdec, value, VIC_THI_STREAMID0); 72 nvdec_writel(nvdec, value, VIC_THI_STREAMID1); 73 } 74 } 75 #endif 76 77 err = falcon_boot(&nvdec->falcon); 78 if (err < 0) 79 return err; 80 81 err = falcon_wait_idle(&nvdec->falcon); 82 if (err < 0) { 83 dev_err(nvdec->dev, "falcon boot timed out\n"); 84 return err; 85 } 86 87 return 0; 88 } 89 90 static int nvdec_init(struct host1x_client *client) 91 { 92 struct tegra_drm_client *drm = host1x_to_drm_client(client); 93 struct drm_device *dev = dev_get_drvdata(client->host); 94 struct tegra_drm *tegra = dev->dev_private; 95 struct nvdec *nvdec = to_nvdec(drm); 96 int err; 97 98 err = host1x_client_iommu_attach(client); 99 if (err < 0 && err != -ENODEV) { 100 dev_err(nvdec->dev, "failed to attach to domain: %d\n", err); 101 return err; 102 } 103 104 nvdec->channel = host1x_channel_request(client); 105 if (!nvdec->channel) { 106 err = -ENOMEM; 107 goto detach; 108 } 109 110 client->syncpts[0] = host1x_syncpt_request(client, 0); 111 if (!client->syncpts[0]) { 112 err = -ENOMEM; 113 goto free_channel; 114 } 115 116 pm_runtime_enable(client->dev); 117 pm_runtime_use_autosuspend(client->dev); 118 pm_runtime_set_autosuspend_delay(client->dev, 500); 119 120 err = tegra_drm_register_client(tegra, drm); 121 if (err < 0) 122 goto disable_rpm; 123 124 /* 125 * Inherit the DMA parameters (such as maximum segment size) from the 126 * parent host1x device. 127 */ 128 client->dev->dma_parms = client->host->dma_parms; 129 130 return 0; 131 132 disable_rpm: 133 pm_runtime_dont_use_autosuspend(client->dev); 134 pm_runtime_force_suspend(client->dev); 135 136 host1x_syncpt_put(client->syncpts[0]); 137 free_channel: 138 host1x_channel_put(nvdec->channel); 139 detach: 140 host1x_client_iommu_detach(client); 141 142 return err; 143 } 144 145 static int nvdec_exit(struct host1x_client *client) 146 { 147 struct tegra_drm_client *drm = host1x_to_drm_client(client); 148 struct drm_device *dev = dev_get_drvdata(client->host); 149 struct tegra_drm *tegra = dev->dev_private; 150 struct nvdec *nvdec = to_nvdec(drm); 151 int err; 152 153 /* avoid a dangling pointer just in case this disappears */ 154 client->dev->dma_parms = NULL; 155 156 err = tegra_drm_unregister_client(tegra, drm); 157 if (err < 0) 158 return err; 159 160 pm_runtime_dont_use_autosuspend(client->dev); 161 pm_runtime_force_suspend(client->dev); 162 163 host1x_syncpt_put(client->syncpts[0]); 164 host1x_channel_put(nvdec->channel); 165 host1x_client_iommu_detach(client); 166 167 nvdec->channel = NULL; 168 169 if (client->group) { 170 dma_unmap_single(nvdec->dev, nvdec->falcon.firmware.phys, 171 nvdec->falcon.firmware.size, DMA_TO_DEVICE); 172 tegra_drm_free(tegra, nvdec->falcon.firmware.size, 173 nvdec->falcon.firmware.virt, 174 nvdec->falcon.firmware.iova); 175 } else { 176 dma_free_coherent(nvdec->dev, nvdec->falcon.firmware.size, 177 nvdec->falcon.firmware.virt, 178 nvdec->falcon.firmware.iova); 179 } 180 181 return 0; 182 } 183 184 static const struct host1x_client_ops nvdec_client_ops = { 185 .init = nvdec_init, 186 .exit = nvdec_exit, 187 }; 188 189 static int nvdec_load_firmware(struct nvdec *nvdec) 190 { 191 struct host1x_client *client = &nvdec->client.base; 192 struct tegra_drm *tegra = nvdec->client.drm; 193 dma_addr_t iova; 194 size_t size; 195 void *virt; 196 int err; 197 198 if (nvdec->falcon.firmware.virt) 199 return 0; 200 201 err = falcon_read_firmware(&nvdec->falcon, nvdec->config->firmware); 202 if (err < 0) 203 return err; 204 205 size = nvdec->falcon.firmware.size; 206 207 if (!client->group) { 208 virt = dma_alloc_coherent(nvdec->dev, size, &iova, GFP_KERNEL); 209 210 err = dma_mapping_error(nvdec->dev, iova); 211 if (err < 0) 212 return err; 213 } else { 214 virt = tegra_drm_alloc(tegra, size, &iova); 215 } 216 217 nvdec->falcon.firmware.virt = virt; 218 nvdec->falcon.firmware.iova = iova; 219 220 err = falcon_load_firmware(&nvdec->falcon); 221 if (err < 0) 222 goto cleanup; 223 224 /* 225 * In this case we have received an IOVA from the shared domain, so we 226 * need to make sure to get the physical address so that the DMA API 227 * knows what memory pages to flush the cache for. 228 */ 229 if (client->group) { 230 dma_addr_t phys; 231 232 phys = dma_map_single(nvdec->dev, virt, size, DMA_TO_DEVICE); 233 234 err = dma_mapping_error(nvdec->dev, phys); 235 if (err < 0) 236 goto cleanup; 237 238 nvdec->falcon.firmware.phys = phys; 239 } 240 241 return 0; 242 243 cleanup: 244 if (!client->group) 245 dma_free_coherent(nvdec->dev, size, virt, iova); 246 else 247 tegra_drm_free(tegra, size, virt, iova); 248 249 return err; 250 } 251 252 253 static __maybe_unused int nvdec_runtime_resume(struct device *dev) 254 { 255 struct nvdec *nvdec = dev_get_drvdata(dev); 256 int err; 257 258 err = clk_prepare_enable(nvdec->clk); 259 if (err < 0) 260 return err; 261 262 usleep_range(10, 20); 263 264 err = nvdec_load_firmware(nvdec); 265 if (err < 0) 266 goto disable; 267 268 err = nvdec_boot(nvdec); 269 if (err < 0) 270 goto disable; 271 272 return 0; 273 274 disable: 275 clk_disable_unprepare(nvdec->clk); 276 return err; 277 } 278 279 static __maybe_unused int nvdec_runtime_suspend(struct device *dev) 280 { 281 struct nvdec *nvdec = dev_get_drvdata(dev); 282 283 host1x_channel_stop(nvdec->channel); 284 285 clk_disable_unprepare(nvdec->clk); 286 287 return 0; 288 } 289 290 static int nvdec_open_channel(struct tegra_drm_client *client, 291 struct tegra_drm_context *context) 292 { 293 struct nvdec *nvdec = to_nvdec(client); 294 int err; 295 296 err = pm_runtime_get_sync(nvdec->dev); 297 if (err < 0) { 298 pm_runtime_put(nvdec->dev); 299 return err; 300 } 301 302 context->channel = host1x_channel_get(nvdec->channel); 303 if (!context->channel) { 304 pm_runtime_put(nvdec->dev); 305 return -ENOMEM; 306 } 307 308 return 0; 309 } 310 311 static void nvdec_close_channel(struct tegra_drm_context *context) 312 { 313 struct nvdec *nvdec = to_nvdec(context->client); 314 315 host1x_channel_put(context->channel); 316 pm_runtime_put(nvdec->dev); 317 } 318 319 static const struct tegra_drm_client_ops nvdec_ops = { 320 .open_channel = nvdec_open_channel, 321 .close_channel = nvdec_close_channel, 322 .submit = tegra_drm_submit, 323 }; 324 325 #define NVIDIA_TEGRA_210_NVDEC_FIRMWARE "nvidia/tegra210/nvdec.bin" 326 327 static const struct nvdec_config nvdec_t210_config = { 328 .firmware = NVIDIA_TEGRA_210_NVDEC_FIRMWARE, 329 .version = 0x21, 330 .supports_sid = false, 331 }; 332 333 #define NVIDIA_TEGRA_186_NVDEC_FIRMWARE "nvidia/tegra186/nvdec.bin" 334 335 static const struct nvdec_config nvdec_t186_config = { 336 .firmware = NVIDIA_TEGRA_186_NVDEC_FIRMWARE, 337 .version = 0x18, 338 .supports_sid = true, 339 }; 340 341 #define NVIDIA_TEGRA_194_NVDEC_FIRMWARE "nvidia/tegra194/nvdec.bin" 342 343 static const struct nvdec_config nvdec_t194_config = { 344 .firmware = NVIDIA_TEGRA_194_NVDEC_FIRMWARE, 345 .version = 0x19, 346 .supports_sid = true, 347 }; 348 349 static const struct of_device_id tegra_nvdec_of_match[] = { 350 { .compatible = "nvidia,tegra210-nvdec", .data = &nvdec_t210_config }, 351 { .compatible = "nvidia,tegra186-nvdec", .data = &nvdec_t186_config }, 352 { .compatible = "nvidia,tegra194-nvdec", .data = &nvdec_t194_config }, 353 { }, 354 }; 355 MODULE_DEVICE_TABLE(of, tegra_nvdec_of_match); 356 357 static int nvdec_probe(struct platform_device *pdev) 358 { 359 struct device *dev = &pdev->dev; 360 struct host1x_syncpt **syncpts; 361 struct nvdec *nvdec; 362 u32 host_class; 363 int err; 364 365 /* inherit DMA mask from host1x parent */ 366 err = dma_coerce_mask_and_coherent(dev, *dev->parent->dma_mask); 367 if (err < 0) { 368 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 369 return err; 370 } 371 372 nvdec = devm_kzalloc(dev, sizeof(*nvdec), GFP_KERNEL); 373 if (!nvdec) 374 return -ENOMEM; 375 376 nvdec->config = of_device_get_match_data(dev); 377 378 syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL); 379 if (!syncpts) 380 return -ENOMEM; 381 382 nvdec->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 383 if (IS_ERR(nvdec->regs)) 384 return PTR_ERR(nvdec->regs); 385 386 nvdec->clk = devm_clk_get(dev, NULL); 387 if (IS_ERR(nvdec->clk)) { 388 dev_err(&pdev->dev, "failed to get clock\n"); 389 return PTR_ERR(nvdec->clk); 390 } 391 392 err = clk_set_rate(nvdec->clk, ULONG_MAX); 393 if (err < 0) { 394 dev_err(&pdev->dev, "failed to set clock rate\n"); 395 return err; 396 } 397 398 err = of_property_read_u32(dev->of_node, "nvidia,host1x-class", &host_class); 399 if (err < 0) 400 host_class = HOST1X_CLASS_NVDEC; 401 402 nvdec->falcon.dev = dev; 403 nvdec->falcon.regs = nvdec->regs; 404 405 err = falcon_init(&nvdec->falcon); 406 if (err < 0) 407 return err; 408 409 platform_set_drvdata(pdev, nvdec); 410 411 INIT_LIST_HEAD(&nvdec->client.base.list); 412 nvdec->client.base.ops = &nvdec_client_ops; 413 nvdec->client.base.dev = dev; 414 nvdec->client.base.class = host_class; 415 nvdec->client.base.syncpts = syncpts; 416 nvdec->client.base.num_syncpts = 1; 417 nvdec->dev = dev; 418 419 INIT_LIST_HEAD(&nvdec->client.list); 420 nvdec->client.version = nvdec->config->version; 421 nvdec->client.ops = &nvdec_ops; 422 423 err = host1x_client_register(&nvdec->client.base); 424 if (err < 0) { 425 dev_err(dev, "failed to register host1x client: %d\n", err); 426 goto exit_falcon; 427 } 428 429 return 0; 430 431 exit_falcon: 432 falcon_exit(&nvdec->falcon); 433 434 return err; 435 } 436 437 static int nvdec_remove(struct platform_device *pdev) 438 { 439 struct nvdec *nvdec = platform_get_drvdata(pdev); 440 int err; 441 442 err = host1x_client_unregister(&nvdec->client.base); 443 if (err < 0) { 444 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 445 err); 446 return err; 447 } 448 449 falcon_exit(&nvdec->falcon); 450 451 return 0; 452 } 453 454 static const struct dev_pm_ops nvdec_pm_ops = { 455 SET_RUNTIME_PM_OPS(nvdec_runtime_suspend, nvdec_runtime_resume, NULL) 456 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 457 pm_runtime_force_resume) 458 }; 459 460 struct platform_driver tegra_nvdec_driver = { 461 .driver = { 462 .name = "tegra-nvdec", 463 .of_match_table = tegra_nvdec_of_match, 464 .pm = &nvdec_pm_ops 465 }, 466 .probe = nvdec_probe, 467 .remove = nvdec_remove, 468 }; 469 470 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) 471 MODULE_FIRMWARE(NVIDIA_TEGRA_210_NVDEC_FIRMWARE); 472 #endif 473 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) 474 MODULE_FIRMWARE(NVIDIA_TEGRA_186_NVDEC_FIRMWARE); 475 #endif 476 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) 477 MODULE_FIRMWARE(NVIDIA_TEGRA_194_NVDEC_FIRMWARE); 478 #endif 479