1 /* 2 * Copyright (C) 2012 Avionic Design GmbH 3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/debugfs.h> 12 #include <linux/gpio.h> 13 #include <linux/hdmi.h> 14 #include <linux/math64.h> 15 #include <linux/of_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/reset.h> 19 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_crtc.h> 22 #include <drm/drm_probe_helper.h> 23 24 #include "hda.h" 25 #include "hdmi.h" 26 #include "drm.h" 27 #include "dc.h" 28 #include "trace.h" 29 30 #define HDMI_ELD_BUFFER_SIZE 96 31 32 struct tmds_config { 33 unsigned int pclk; 34 u32 pll0; 35 u32 pll1; 36 u32 pe_current; 37 u32 drive_current; 38 u32 peak_current; 39 }; 40 41 struct tegra_hdmi_config { 42 const struct tmds_config *tmds; 43 unsigned int num_tmds; 44 45 unsigned long fuse_override_offset; 46 u32 fuse_override_value; 47 48 bool has_sor_io_peak_current; 49 bool has_hda; 50 bool has_hbr; 51 }; 52 53 struct tegra_hdmi { 54 struct host1x_client client; 55 struct tegra_output output; 56 struct device *dev; 57 58 struct regulator *hdmi; 59 struct regulator *pll; 60 struct regulator *vdd; 61 62 void __iomem *regs; 63 unsigned int irq; 64 65 struct clk *clk_parent; 66 struct clk *clk; 67 struct reset_control *rst; 68 69 const struct tegra_hdmi_config *config; 70 71 unsigned int audio_source; 72 struct tegra_hda_format format; 73 74 unsigned int pixel_clock; 75 bool stereo; 76 bool dvi; 77 78 struct drm_info_list *debugfs_files; 79 }; 80 81 static inline struct tegra_hdmi * 82 host1x_client_to_hdmi(struct host1x_client *client) 83 { 84 return container_of(client, struct tegra_hdmi, client); 85 } 86 87 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output) 88 { 89 return container_of(output, struct tegra_hdmi, output); 90 } 91 92 #define HDMI_AUDIOCLK_FREQ 216000000 93 #define HDMI_REKEY_DEFAULT 56 94 95 enum { 96 AUTO = 0, 97 SPDIF, 98 HDA, 99 }; 100 101 static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi, 102 unsigned int offset) 103 { 104 u32 value = readl(hdmi->regs + (offset << 2)); 105 106 trace_hdmi_readl(hdmi->dev, offset, value); 107 108 return value; 109 } 110 111 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value, 112 unsigned int offset) 113 { 114 trace_hdmi_writel(hdmi->dev, offset, value); 115 writel(value, hdmi->regs + (offset << 2)); 116 } 117 118 struct tegra_hdmi_audio_config { 119 unsigned int n; 120 unsigned int cts; 121 unsigned int aval; 122 }; 123 124 static const struct tmds_config tegra20_tmds_config[] = { 125 { /* slow pixel clock modes */ 126 .pclk = 27000000, 127 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 128 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) | 129 SOR_PLL_TX_REG_LOAD(3), 130 .pll1 = SOR_PLL_TMDS_TERM_ENABLE, 131 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) | 132 PE_CURRENT1(PE_CURRENT_0_0_mA) | 133 PE_CURRENT2(PE_CURRENT_0_0_mA) | 134 PE_CURRENT3(PE_CURRENT_0_0_mA), 135 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) | 136 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | 137 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | 138 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), 139 }, 140 { /* high pixel clock modes */ 141 .pclk = UINT_MAX, 142 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 143 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) | 144 SOR_PLL_TX_REG_LOAD(3), 145 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, 146 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) | 147 PE_CURRENT1(PE_CURRENT_6_0_mA) | 148 PE_CURRENT2(PE_CURRENT_6_0_mA) | 149 PE_CURRENT3(PE_CURRENT_6_0_mA), 150 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) | 151 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | 152 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | 153 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), 154 }, 155 }; 156 157 static const struct tmds_config tegra30_tmds_config[] = { 158 { /* 480p modes */ 159 .pclk = 27000000, 160 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 161 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) | 162 SOR_PLL_TX_REG_LOAD(0), 163 .pll1 = SOR_PLL_TMDS_TERM_ENABLE, 164 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) | 165 PE_CURRENT1(PE_CURRENT_0_0_mA) | 166 PE_CURRENT2(PE_CURRENT_0_0_mA) | 167 PE_CURRENT3(PE_CURRENT_0_0_mA), 168 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | 169 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | 170 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | 171 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), 172 }, { /* 720p modes */ 173 .pclk = 74250000, 174 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 175 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) | 176 SOR_PLL_TX_REG_LOAD(0), 177 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, 178 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) | 179 PE_CURRENT1(PE_CURRENT_5_0_mA) | 180 PE_CURRENT2(PE_CURRENT_5_0_mA) | 181 PE_CURRENT3(PE_CURRENT_5_0_mA), 182 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | 183 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | 184 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | 185 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), 186 }, { /* 1080p modes */ 187 .pclk = UINT_MAX, 188 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 189 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) | 190 SOR_PLL_TX_REG_LOAD(0), 191 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, 192 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) | 193 PE_CURRENT1(PE_CURRENT_5_0_mA) | 194 PE_CURRENT2(PE_CURRENT_5_0_mA) | 195 PE_CURRENT3(PE_CURRENT_5_0_mA), 196 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | 197 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | 198 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | 199 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), 200 }, 201 }; 202 203 static const struct tmds_config tegra114_tmds_config[] = { 204 { /* 480p/576p / 25.2MHz/27MHz modes */ 205 .pclk = 27000000, 206 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 207 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL, 208 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), 209 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | 210 PE_CURRENT1(PE_CURRENT_0_mA_T114) | 211 PE_CURRENT2(PE_CURRENT_0_mA_T114) | 212 PE_CURRENT3(PE_CURRENT_0_mA_T114), 213 .drive_current = 214 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | 215 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | 216 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | 217 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), 218 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 219 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 220 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 221 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 222 }, { /* 720p / 74.25MHz modes */ 223 .pclk = 74250000, 224 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 225 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL, 226 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | 227 SOR_PLL_TMDS_TERMADJ(0), 228 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) | 229 PE_CURRENT1(PE_CURRENT_15_mA_T114) | 230 PE_CURRENT2(PE_CURRENT_15_mA_T114) | 231 PE_CURRENT3(PE_CURRENT_15_mA_T114), 232 .drive_current = 233 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | 234 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | 235 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | 236 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), 237 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 238 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 239 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 240 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 241 }, { /* 1080p / 148.5MHz modes */ 242 .pclk = 148500000, 243 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 244 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL, 245 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | 246 SOR_PLL_TMDS_TERMADJ(0), 247 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) | 248 PE_CURRENT1(PE_CURRENT_10_mA_T114) | 249 PE_CURRENT2(PE_CURRENT_10_mA_T114) | 250 PE_CURRENT3(PE_CURRENT_10_mA_T114), 251 .drive_current = 252 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) | 253 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) | 254 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) | 255 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114), 256 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 257 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 258 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 259 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 260 }, { /* 225/297MHz modes */ 261 .pclk = UINT_MAX, 262 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 263 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL, 264 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7) 265 | SOR_PLL_TMDS_TERM_ENABLE, 266 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | 267 PE_CURRENT1(PE_CURRENT_0_mA_T114) | 268 PE_CURRENT2(PE_CURRENT_0_mA_T114) | 269 PE_CURRENT3(PE_CURRENT_0_mA_T114), 270 .drive_current = 271 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) | 272 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) | 273 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) | 274 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114), 275 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) | 276 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) | 277 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) | 278 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA), 279 }, 280 }; 281 282 static const struct tmds_config tegra124_tmds_config[] = { 283 { /* 480p/576p / 25.2MHz/27MHz modes */ 284 .pclk = 27000000, 285 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 286 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL, 287 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), 288 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | 289 PE_CURRENT1(PE_CURRENT_0_mA_T114) | 290 PE_CURRENT2(PE_CURRENT_0_mA_T114) | 291 PE_CURRENT3(PE_CURRENT_0_mA_T114), 292 .drive_current = 293 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | 294 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | 295 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | 296 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), 297 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 298 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 299 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 300 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 301 }, { /* 720p / 74.25MHz modes */ 302 .pclk = 74250000, 303 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 304 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL, 305 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | 306 SOR_PLL_TMDS_TERMADJ(0), 307 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) | 308 PE_CURRENT1(PE_CURRENT_15_mA_T114) | 309 PE_CURRENT2(PE_CURRENT_15_mA_T114) | 310 PE_CURRENT3(PE_CURRENT_15_mA_T114), 311 .drive_current = 312 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | 313 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | 314 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | 315 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), 316 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 317 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 318 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 319 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 320 }, { /* 1080p / 148.5MHz modes */ 321 .pclk = 148500000, 322 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 323 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL, 324 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | 325 SOR_PLL_TMDS_TERMADJ(0), 326 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) | 327 PE_CURRENT1(PE_CURRENT_10_mA_T114) | 328 PE_CURRENT2(PE_CURRENT_10_mA_T114) | 329 PE_CURRENT3(PE_CURRENT_10_mA_T114), 330 .drive_current = 331 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) | 332 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) | 333 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) | 334 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114), 335 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 336 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 337 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 338 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 339 }, { /* 225/297MHz modes */ 340 .pclk = UINT_MAX, 341 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 342 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL, 343 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7) 344 | SOR_PLL_TMDS_TERM_ENABLE, 345 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | 346 PE_CURRENT1(PE_CURRENT_0_mA_T114) | 347 PE_CURRENT2(PE_CURRENT_0_mA_T114) | 348 PE_CURRENT3(PE_CURRENT_0_mA_T114), 349 .drive_current = 350 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) | 351 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) | 352 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) | 353 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114), 354 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) | 355 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) | 356 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) | 357 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA), 358 }, 359 }; 360 361 static int 362 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pix_clock, 363 struct tegra_hdmi_audio_config *config) 364 { 365 const unsigned int afreq = 128 * audio_freq; 366 const unsigned int min_n = afreq / 1500; 367 const unsigned int max_n = afreq / 300; 368 const unsigned int ideal_n = afreq / 1000; 369 int64_t min_err = (uint64_t)-1 >> 1; 370 unsigned int min_delta = -1; 371 int n; 372 373 memset(config, 0, sizeof(*config)); 374 config->n = -1; 375 376 for (n = min_n; n <= max_n; n++) { 377 uint64_t cts_f, aval_f; 378 unsigned int delta; 379 int64_t cts, err; 380 381 /* compute aval in 48.16 fixed point */ 382 aval_f = ((int64_t)24000000 << 16) * n; 383 do_div(aval_f, afreq); 384 /* It should round without any rest */ 385 if (aval_f & 0xFFFF) 386 continue; 387 388 /* Compute cts in 48.16 fixed point */ 389 cts_f = ((int64_t)pix_clock << 16) * n; 390 do_div(cts_f, afreq); 391 /* Round it to the nearest integer */ 392 cts = (cts_f & ~0xFFFF) + ((cts_f & BIT(15)) << 1); 393 394 delta = abs(n - ideal_n); 395 396 /* Compute the absolute error */ 397 err = abs((int64_t)cts_f - cts); 398 if (err < min_err || (err == min_err && delta < min_delta)) { 399 config->n = n; 400 config->cts = cts >> 16; 401 config->aval = aval_f >> 16; 402 min_delta = delta; 403 min_err = err; 404 } 405 } 406 407 return config->n != -1 ? 0 : -EINVAL; 408 } 409 410 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi) 411 { 412 const unsigned int freqs[] = { 413 32000, 44100, 48000, 88200, 96000, 176400, 192000 414 }; 415 unsigned int i; 416 417 for (i = 0; i < ARRAY_SIZE(freqs); i++) { 418 unsigned int f = freqs[i]; 419 unsigned int eight_half; 420 unsigned int delta; 421 u32 value; 422 423 if (f > 96000) 424 delta = 2; 425 else if (f > 48000) 426 delta = 6; 427 else 428 delta = 9; 429 430 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128); 431 value = AUDIO_FS_LOW(eight_half - delta) | 432 AUDIO_FS_HIGH(eight_half + delta); 433 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i)); 434 } 435 } 436 437 static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value) 438 { 439 static const struct { 440 unsigned int sample_rate; 441 unsigned int offset; 442 } regs[] = { 443 { 32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 }, 444 { 44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 }, 445 { 48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 }, 446 { 88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 }, 447 { 96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 }, 448 { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 }, 449 { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 }, 450 }; 451 unsigned int i; 452 453 for (i = 0; i < ARRAY_SIZE(regs); i++) { 454 if (regs[i].sample_rate == hdmi->format.sample_rate) { 455 tegra_hdmi_writel(hdmi, value, regs[i].offset); 456 break; 457 } 458 } 459 } 460 461 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi) 462 { 463 struct tegra_hdmi_audio_config config; 464 u32 source, value; 465 int err; 466 467 switch (hdmi->audio_source) { 468 case HDA: 469 if (hdmi->config->has_hda) 470 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL; 471 else 472 return -EINVAL; 473 474 break; 475 476 case SPDIF: 477 if (hdmi->config->has_hda) 478 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF; 479 else 480 source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF; 481 break; 482 483 default: 484 if (hdmi->config->has_hda) 485 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO; 486 else 487 source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO; 488 break; 489 } 490 491 /* 492 * Tegra30 and later use a slightly modified version of the register 493 * layout to accomodate for changes related to supporting HDA as the 494 * audio input source for HDMI. The source select field has moved to 495 * the SOR_AUDIO_CNTRL0 register, but the error tolerance and frames 496 * per block fields remain in the AUDIO_CNTRL0 register. 497 */ 498 if (hdmi->config->has_hda) { 499 /* 500 * Inject null samples into the audio FIFO for every frame in 501 * which the codec did not receive any samples. This applies 502 * to stereo LPCM only. 503 * 504 * XXX: This seems to be a remnant of MCP days when this was 505 * used to work around issues with monitors not being able to 506 * play back system startup sounds early. It is possibly not 507 * needed on Linux at all. 508 */ 509 if (hdmi->format.channels == 2) 510 value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL; 511 else 512 value = 0; 513 514 value |= source; 515 516 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0); 517 } 518 519 /* 520 * On Tegra20, HDA is not a supported audio source and the source 521 * select field is part of the AUDIO_CNTRL0 register. 522 */ 523 value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) | 524 AUDIO_CNTRL0_ERROR_TOLERANCE(6); 525 526 if (!hdmi->config->has_hda) 527 value |= source; 528 529 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0); 530 531 /* 532 * Advertise support for High Bit-Rate on Tegra114 and later. 533 */ 534 if (hdmi->config->has_hbr) { 535 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0); 536 value |= SOR_AUDIO_SPARE0_HBR_ENABLE; 537 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0); 538 } 539 540 err = tegra_hdmi_get_audio_config(hdmi->format.sample_rate, 541 hdmi->pixel_clock, &config); 542 if (err < 0) { 543 dev_err(hdmi->dev, 544 "cannot set audio to %u Hz at %u Hz pixel clock\n", 545 hdmi->format.sample_rate, hdmi->pixel_clock); 546 return err; 547 } 548 549 dev_dbg(hdmi->dev, "audio: pixclk=%u, n=%u, cts=%u, aval=%u\n", 550 hdmi->pixel_clock, config.n, config.cts, config.aval); 551 552 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL); 553 554 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE | 555 AUDIO_N_VALUE(config.n - 1); 556 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N); 557 558 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config.n) | ACR_ENABLE, 559 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH); 560 561 tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config.cts), 562 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW); 563 564 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1); 565 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE); 566 567 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N); 568 value &= ~AUDIO_N_RESETF; 569 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N); 570 571 if (hdmi->config->has_hda) 572 tegra_hdmi_write_aval(hdmi, config.aval); 573 574 tegra_hdmi_setup_audio_fs_tables(hdmi); 575 576 return 0; 577 } 578 579 static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi) 580 { 581 u32 value; 582 583 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 584 value &= ~GENERIC_CTRL_AUDIO; 585 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 586 } 587 588 static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi) 589 { 590 u32 value; 591 592 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 593 value |= GENERIC_CTRL_AUDIO; 594 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 595 } 596 597 static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi) 598 { 599 size_t length = drm_eld_size(hdmi->output.connector.eld), i; 600 u32 value; 601 602 for (i = 0; i < length; i++) 603 tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i], 604 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR); 605 606 /* 607 * The HDA codec will always report an ELD buffer size of 96 bytes and 608 * the HDA codec driver will check that each byte read from the buffer 609 * is valid. Therefore every byte must be written, even if no 96 bytes 610 * were parsed from EDID. 611 */ 612 for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++) 613 tegra_hdmi_writel(hdmi, i << 8 | 0, 614 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR); 615 616 value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT; 617 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE); 618 } 619 620 static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size) 621 { 622 u32 value = 0; 623 size_t i; 624 625 for (i = size; i > 0; i--) 626 value = (value << 8) | ptr[i - 1]; 627 628 return value; 629 } 630 631 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data, 632 size_t size) 633 { 634 const u8 *ptr = data; 635 unsigned long offset; 636 size_t i, j; 637 u32 value; 638 639 switch (ptr[0]) { 640 case HDMI_INFOFRAME_TYPE_AVI: 641 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER; 642 break; 643 644 case HDMI_INFOFRAME_TYPE_AUDIO: 645 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER; 646 break; 647 648 case HDMI_INFOFRAME_TYPE_VENDOR: 649 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER; 650 break; 651 652 default: 653 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n", 654 ptr[0]); 655 return; 656 } 657 658 value = INFOFRAME_HEADER_TYPE(ptr[0]) | 659 INFOFRAME_HEADER_VERSION(ptr[1]) | 660 INFOFRAME_HEADER_LEN(ptr[2]); 661 tegra_hdmi_writel(hdmi, value, offset); 662 offset++; 663 664 /* 665 * Each subpack contains 7 bytes, divided into: 666 * - subpack_low: bytes 0 - 3 667 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) 668 */ 669 for (i = 3, j = 0; i < size; i += 7, j += 8) { 670 size_t rem = size - i, num = min_t(size_t, rem, 4); 671 672 value = tegra_hdmi_subpack(&ptr[i], num); 673 tegra_hdmi_writel(hdmi, value, offset++); 674 675 num = min_t(size_t, rem - num, 3); 676 677 value = tegra_hdmi_subpack(&ptr[i + 4], num); 678 tegra_hdmi_writel(hdmi, value, offset++); 679 } 680 } 681 682 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi, 683 struct drm_display_mode *mode) 684 { 685 struct hdmi_avi_infoframe frame; 686 u8 buffer[17]; 687 ssize_t err; 688 689 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, 690 &hdmi->output.connector, mode); 691 if (err < 0) { 692 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err); 693 return; 694 } 695 696 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 697 if (err < 0) { 698 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err); 699 return; 700 } 701 702 tegra_hdmi_write_infopack(hdmi, buffer, err); 703 } 704 705 static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi) 706 { 707 u32 value; 708 709 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); 710 value &= ~INFOFRAME_CTRL_ENABLE; 711 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); 712 } 713 714 static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi) 715 { 716 u32 value; 717 718 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); 719 value |= INFOFRAME_CTRL_ENABLE; 720 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); 721 } 722 723 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi) 724 { 725 struct hdmi_audio_infoframe frame; 726 u8 buffer[14]; 727 ssize_t err; 728 729 err = hdmi_audio_infoframe_init(&frame); 730 if (err < 0) { 731 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n", 732 err); 733 return; 734 } 735 736 frame.channels = hdmi->format.channels; 737 738 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 739 if (err < 0) { 740 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n", 741 err); 742 return; 743 } 744 745 /* 746 * The audio infoframe has only one set of subpack registers, so the 747 * infoframe needs to be truncated. One set of subpack registers can 748 * contain 7 bytes. Including the 3 byte header only the first 10 749 * bytes can be programmed. 750 */ 751 tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err)); 752 } 753 754 static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi) 755 { 756 u32 value; 757 758 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); 759 value &= ~INFOFRAME_CTRL_ENABLE; 760 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); 761 } 762 763 static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi) 764 { 765 u32 value; 766 767 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); 768 value |= INFOFRAME_CTRL_ENABLE; 769 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); 770 } 771 772 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi) 773 { 774 struct hdmi_vendor_infoframe frame; 775 u8 buffer[10]; 776 ssize_t err; 777 778 hdmi_vendor_infoframe_init(&frame); 779 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING; 780 781 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 782 if (err < 0) { 783 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n", 784 err); 785 return; 786 } 787 788 tegra_hdmi_write_infopack(hdmi, buffer, err); 789 } 790 791 static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi) 792 { 793 u32 value; 794 795 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 796 value &= ~GENERIC_CTRL_ENABLE; 797 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 798 } 799 800 static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi) 801 { 802 u32 value; 803 804 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 805 value |= GENERIC_CTRL_ENABLE; 806 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 807 } 808 809 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi, 810 const struct tmds_config *tmds) 811 { 812 u32 value; 813 814 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0); 815 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); 816 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT); 817 818 tegra_hdmi_writel(hdmi, tmds->drive_current, 819 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT); 820 821 value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset); 822 value |= hdmi->config->fuse_override_value; 823 tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset); 824 825 if (hdmi->config->has_sor_io_peak_current) 826 tegra_hdmi_writel(hdmi, tmds->peak_current, 827 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT); 828 } 829 830 static bool tegra_output_is_hdmi(struct tegra_output *output) 831 { 832 struct edid *edid; 833 834 if (!output->connector.edid_blob_ptr) 835 return false; 836 837 edid = (struct edid *)output->connector.edid_blob_ptr->data; 838 839 return drm_detect_hdmi_monitor(edid); 840 } 841 842 static enum drm_connector_status 843 tegra_hdmi_connector_detect(struct drm_connector *connector, bool force) 844 { 845 struct tegra_output *output = connector_to_output(connector); 846 struct tegra_hdmi *hdmi = to_hdmi(output); 847 enum drm_connector_status status; 848 849 status = tegra_output_connector_detect(connector, force); 850 if (status == connector_status_connected) 851 return status; 852 853 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE); 854 return status; 855 } 856 857 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 858 859 static const struct debugfs_reg32 tegra_hdmi_regs[] = { 860 DEBUGFS_REG32(HDMI_CTXSW), 861 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0), 862 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1), 863 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2), 864 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB), 865 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB), 866 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB), 867 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB), 868 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB), 869 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB), 870 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB), 871 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB), 872 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB), 873 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB), 874 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB), 875 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB), 876 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL), 877 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE), 878 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB), 879 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB), 880 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB), 881 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2), 882 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1), 883 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI), 884 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB), 885 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB), 886 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0), 887 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0), 888 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1), 889 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2), 890 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL), 891 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS), 892 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER), 893 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW), 894 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH), 895 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL), 896 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS), 897 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER), 898 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW), 899 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH), 900 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW), 901 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH), 902 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL), 903 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS), 904 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER), 905 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW), 906 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH), 907 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW), 908 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH), 909 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW), 910 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH), 911 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW), 912 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH), 913 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL), 914 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW), 915 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH), 916 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW), 917 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH), 918 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW), 919 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH), 920 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW), 921 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH), 922 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW), 923 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH), 924 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW), 925 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH), 926 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW), 927 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH), 928 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL), 929 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT), 930 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW), 931 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL), 932 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS), 933 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK), 934 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1), 935 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2), 936 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0), 937 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1), 938 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA), 939 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE), 940 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1), 941 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2), 942 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL), 943 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP), 944 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR), 945 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST), 946 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0), 947 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1), 948 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2), 949 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM), 950 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS), 951 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA), 952 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB), 953 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK), 954 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL), 955 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)), 956 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)), 957 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)), 958 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)), 959 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)), 960 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)), 961 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)), 962 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)), 963 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)), 964 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)), 965 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)), 966 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)), 967 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)), 968 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)), 969 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)), 970 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)), 971 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0), 972 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1), 973 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0), 974 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1), 975 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0), 976 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1), 977 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0), 978 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1), 979 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0), 980 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1), 981 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG), 982 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK), 983 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT), 984 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0), 985 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1), 986 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2), 987 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)), 988 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)), 989 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)), 990 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)), 991 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)), 992 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)), 993 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)), 994 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH), 995 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD), 996 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0), 997 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N), 998 DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING), 999 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK), 1000 DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL), 1001 DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL), 1002 DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH), 1003 DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT), 1004 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL), 1005 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0), 1006 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1), 1007 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2), 1008 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0), 1009 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1), 1010 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2), 1011 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3), 1012 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG), 1013 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX), 1014 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0), 1015 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0), 1016 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0), 1017 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1), 1018 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR), 1019 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE), 1020 DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS), 1021 DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK), 1022 DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE), 1023 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT), 1024 }; 1025 1026 static int tegra_hdmi_show_regs(struct seq_file *s, void *data) 1027 { 1028 struct drm_info_node *node = s->private; 1029 struct tegra_hdmi *hdmi = node->info_ent->data; 1030 struct drm_crtc *crtc = hdmi->output.encoder.crtc; 1031 struct drm_device *drm = node->minor->dev; 1032 unsigned int i; 1033 int err = 0; 1034 1035 drm_modeset_lock_all(drm); 1036 1037 if (!crtc || !crtc->state->active) { 1038 err = -EBUSY; 1039 goto unlock; 1040 } 1041 1042 for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) { 1043 unsigned int offset = tegra_hdmi_regs[i].offset; 1044 1045 seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name, 1046 offset, tegra_hdmi_readl(hdmi, offset)); 1047 } 1048 1049 unlock: 1050 drm_modeset_unlock_all(drm); 1051 return err; 1052 } 1053 1054 static struct drm_info_list debugfs_files[] = { 1055 { "regs", tegra_hdmi_show_regs, 0, NULL }, 1056 }; 1057 1058 static int tegra_hdmi_late_register(struct drm_connector *connector) 1059 { 1060 struct tegra_output *output = connector_to_output(connector); 1061 unsigned int i, count = ARRAY_SIZE(debugfs_files); 1062 struct drm_minor *minor = connector->dev->primary; 1063 struct dentry *root = connector->debugfs_entry; 1064 struct tegra_hdmi *hdmi = to_hdmi(output); 1065 int err; 1066 1067 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1068 GFP_KERNEL); 1069 if (!hdmi->debugfs_files) 1070 return -ENOMEM; 1071 1072 for (i = 0; i < count; i++) 1073 hdmi->debugfs_files[i].data = hdmi; 1074 1075 err = drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor); 1076 if (err < 0) 1077 goto free; 1078 1079 return 0; 1080 1081 free: 1082 kfree(hdmi->debugfs_files); 1083 hdmi->debugfs_files = NULL; 1084 1085 return err; 1086 } 1087 1088 static void tegra_hdmi_early_unregister(struct drm_connector *connector) 1089 { 1090 struct tegra_output *output = connector_to_output(connector); 1091 struct drm_minor *minor = connector->dev->primary; 1092 unsigned int count = ARRAY_SIZE(debugfs_files); 1093 struct tegra_hdmi *hdmi = to_hdmi(output); 1094 1095 drm_debugfs_remove_files(hdmi->debugfs_files, count, minor); 1096 kfree(hdmi->debugfs_files); 1097 hdmi->debugfs_files = NULL; 1098 } 1099 1100 static const struct drm_connector_funcs tegra_hdmi_connector_funcs = { 1101 .reset = drm_atomic_helper_connector_reset, 1102 .detect = tegra_hdmi_connector_detect, 1103 .fill_modes = drm_helper_probe_single_connector_modes, 1104 .destroy = tegra_output_connector_destroy, 1105 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1106 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1107 .late_register = tegra_hdmi_late_register, 1108 .early_unregister = tegra_hdmi_early_unregister, 1109 }; 1110 1111 static enum drm_mode_status 1112 tegra_hdmi_connector_mode_valid(struct drm_connector *connector, 1113 struct drm_display_mode *mode) 1114 { 1115 struct tegra_output *output = connector_to_output(connector); 1116 struct tegra_hdmi *hdmi = to_hdmi(output); 1117 unsigned long pclk = mode->clock * 1000; 1118 enum drm_mode_status status = MODE_OK; 1119 struct clk *parent; 1120 long err; 1121 1122 parent = clk_get_parent(hdmi->clk_parent); 1123 1124 err = clk_round_rate(parent, pclk * 4); 1125 if (err <= 0) 1126 status = MODE_NOCLOCK; 1127 1128 return status; 1129 } 1130 1131 static const struct drm_connector_helper_funcs 1132 tegra_hdmi_connector_helper_funcs = { 1133 .get_modes = tegra_output_connector_get_modes, 1134 .mode_valid = tegra_hdmi_connector_mode_valid, 1135 }; 1136 1137 static const struct drm_encoder_funcs tegra_hdmi_encoder_funcs = { 1138 .destroy = tegra_output_encoder_destroy, 1139 }; 1140 1141 static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder) 1142 { 1143 struct tegra_output *output = encoder_to_output(encoder); 1144 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1145 struct tegra_hdmi *hdmi = to_hdmi(output); 1146 u32 value; 1147 1148 /* 1149 * The following accesses registers of the display controller, so make 1150 * sure it's only executed when the output is attached to one. 1151 */ 1152 if (dc) { 1153 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1154 value &= ~HDMI_ENABLE; 1155 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1156 1157 tegra_dc_commit(dc); 1158 } 1159 1160 if (!hdmi->dvi) { 1161 if (hdmi->stereo) 1162 tegra_hdmi_disable_stereo_infoframe(hdmi); 1163 1164 tegra_hdmi_disable_audio_infoframe(hdmi); 1165 tegra_hdmi_disable_avi_infoframe(hdmi); 1166 tegra_hdmi_disable_audio(hdmi); 1167 } 1168 1169 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE); 1170 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK); 1171 1172 pm_runtime_put(hdmi->dev); 1173 } 1174 1175 static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder) 1176 { 1177 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 1178 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey; 1179 struct tegra_output *output = encoder_to_output(encoder); 1180 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1181 struct tegra_hdmi *hdmi = to_hdmi(output); 1182 unsigned int pulse_start, div82; 1183 int retries = 1000; 1184 u32 value; 1185 int err; 1186 1187 pm_runtime_get_sync(hdmi->dev); 1188 1189 /* 1190 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This 1191 * is used for interoperability between the HDA codec driver and the 1192 * HDMI driver. 1193 */ 1194 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE); 1195 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK); 1196 1197 hdmi->pixel_clock = mode->clock * 1000; 1198 h_sync_width = mode->hsync_end - mode->hsync_start; 1199 h_back_porch = mode->htotal - mode->hsync_end; 1200 h_front_porch = mode->hsync_start - mode->hdisplay; 1201 1202 err = clk_set_rate(hdmi->clk, hdmi->pixel_clock); 1203 if (err < 0) { 1204 dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n", 1205 err); 1206 } 1207 1208 DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk)); 1209 1210 /* power up sequence */ 1211 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0); 1212 value &= ~SOR_PLL_PDBG; 1213 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0); 1214 1215 usleep_range(10, 20); 1216 1217 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0); 1218 value &= ~SOR_PLL_PWR; 1219 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0); 1220 1221 tegra_dc_writel(dc, VSYNC_H_POSITION(1), 1222 DC_DISP_DISP_TIMING_OPTIONS); 1223 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888, 1224 DC_DISP_DISP_COLOR_CONTROL); 1225 1226 /* video_preamble uses h_pulse2 */ 1227 pulse_start = 1 + h_sync_width + h_back_porch - 10; 1228 1229 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0); 1230 1231 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE | 1232 PULSE_LAST_END_A; 1233 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); 1234 1235 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8); 1236 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); 1237 1238 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) | 1239 VSYNC_WINDOW_ENABLE; 1240 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW); 1241 1242 if (dc->pipe) 1243 value = HDMI_SRC_DISPLAYB; 1244 else 1245 value = HDMI_SRC_DISPLAYA; 1246 1247 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) || 1248 (mode->vdisplay == 576))) 1249 tegra_hdmi_writel(hdmi, 1250 value | ARM_VIDEO_RANGE_FULL, 1251 HDMI_NV_PDISP_INPUT_CONTROL); 1252 else 1253 tegra_hdmi_writel(hdmi, 1254 value | ARM_VIDEO_RANGE_LIMITED, 1255 HDMI_NV_PDISP_INPUT_CONTROL); 1256 1257 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4; 1258 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82); 1259 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK); 1260 1261 hdmi->dvi = !tegra_output_is_hdmi(output); 1262 if (!hdmi->dvi) { 1263 err = tegra_hdmi_setup_audio(hdmi); 1264 if (err < 0) 1265 hdmi->dvi = true; 1266 } 1267 1268 if (hdmi->config->has_hda) 1269 tegra_hdmi_write_eld(hdmi); 1270 1271 rekey = HDMI_REKEY_DEFAULT; 1272 value = HDMI_CTRL_REKEY(rekey); 1273 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch + 1274 h_front_porch - rekey - 18) / 32); 1275 1276 if (!hdmi->dvi) 1277 value |= HDMI_CTRL_ENABLE; 1278 1279 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL); 1280 1281 if (!hdmi->dvi) { 1282 tegra_hdmi_setup_avi_infoframe(hdmi, mode); 1283 tegra_hdmi_setup_audio_infoframe(hdmi); 1284 1285 if (hdmi->stereo) 1286 tegra_hdmi_setup_stereo_infoframe(hdmi); 1287 } 1288 1289 /* TMDS CONFIG */ 1290 for (i = 0; i < hdmi->config->num_tmds; i++) { 1291 if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) { 1292 tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]); 1293 break; 1294 } 1295 } 1296 1297 tegra_hdmi_writel(hdmi, 1298 SOR_SEQ_PU_PC(0) | 1299 SOR_SEQ_PU_PC_ALT(0) | 1300 SOR_SEQ_PD_PC(8) | 1301 SOR_SEQ_PD_PC_ALT(8), 1302 HDMI_NV_PDISP_SOR_SEQ_CTL); 1303 1304 value = SOR_SEQ_INST_WAIT_TIME(1) | 1305 SOR_SEQ_INST_WAIT_UNITS_VSYNC | 1306 SOR_SEQ_INST_HALT | 1307 SOR_SEQ_INST_PIN_A_LOW | 1308 SOR_SEQ_INST_PIN_B_LOW | 1309 SOR_SEQ_INST_DRIVE_PWM_OUT_LO; 1310 1311 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0)); 1312 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8)); 1313 1314 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM); 1315 value &= ~SOR_CSTM_ROTCLK(~0); 1316 value |= SOR_CSTM_ROTCLK(2); 1317 value |= SOR_CSTM_PLLDIV; 1318 value &= ~SOR_CSTM_LVDS_ENABLE; 1319 value &= ~SOR_CSTM_MODE_MASK; 1320 value |= SOR_CSTM_MODE_TMDS; 1321 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM); 1322 1323 /* start SOR */ 1324 tegra_hdmi_writel(hdmi, 1325 SOR_PWR_NORMAL_STATE_PU | 1326 SOR_PWR_NORMAL_START_NORMAL | 1327 SOR_PWR_SAFE_STATE_PD | 1328 SOR_PWR_SETTING_NEW_TRIGGER, 1329 HDMI_NV_PDISP_SOR_PWR); 1330 tegra_hdmi_writel(hdmi, 1331 SOR_PWR_NORMAL_STATE_PU | 1332 SOR_PWR_NORMAL_START_NORMAL | 1333 SOR_PWR_SAFE_STATE_PD | 1334 SOR_PWR_SETTING_NEW_DONE, 1335 HDMI_NV_PDISP_SOR_PWR); 1336 1337 do { 1338 BUG_ON(--retries < 0); 1339 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR); 1340 } while (value & SOR_PWR_SETTING_NEW_PENDING); 1341 1342 value = SOR_STATE_ASY_CRCMODE_COMPLETE | 1343 SOR_STATE_ASY_OWNER_HEAD0 | 1344 SOR_STATE_ASY_SUBOWNER_BOTH | 1345 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A | 1346 SOR_STATE_ASY_DEPOL_POS; 1347 1348 /* setup sync polarities */ 1349 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1350 value |= SOR_STATE_ASY_HSYNCPOL_POS; 1351 1352 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1353 value |= SOR_STATE_ASY_HSYNCPOL_NEG; 1354 1355 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1356 value |= SOR_STATE_ASY_VSYNCPOL_POS; 1357 1358 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1359 value |= SOR_STATE_ASY_VSYNCPOL_NEG; 1360 1361 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2); 1362 1363 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL; 1364 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1); 1365 1366 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0); 1367 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0); 1368 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED, 1369 HDMI_NV_PDISP_SOR_STATE1); 1370 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0); 1371 1372 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1373 value |= HDMI_ENABLE; 1374 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1375 1376 tegra_dc_commit(dc); 1377 1378 if (!hdmi->dvi) { 1379 tegra_hdmi_enable_avi_infoframe(hdmi); 1380 tegra_hdmi_enable_audio_infoframe(hdmi); 1381 tegra_hdmi_enable_audio(hdmi); 1382 1383 if (hdmi->stereo) 1384 tegra_hdmi_enable_stereo_infoframe(hdmi); 1385 } 1386 1387 /* TODO: add HDCP support */ 1388 } 1389 1390 static int 1391 tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1392 struct drm_crtc_state *crtc_state, 1393 struct drm_connector_state *conn_state) 1394 { 1395 struct tegra_output *output = encoder_to_output(encoder); 1396 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 1397 unsigned long pclk = crtc_state->mode.clock * 1000; 1398 struct tegra_hdmi *hdmi = to_hdmi(output); 1399 int err; 1400 1401 err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent, 1402 pclk, 0); 1403 if (err < 0) { 1404 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 1405 return err; 1406 } 1407 1408 return err; 1409 } 1410 1411 static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = { 1412 .disable = tegra_hdmi_encoder_disable, 1413 .enable = tegra_hdmi_encoder_enable, 1414 .atomic_check = tegra_hdmi_encoder_atomic_check, 1415 }; 1416 1417 static int tegra_hdmi_init(struct host1x_client *client) 1418 { 1419 struct drm_device *drm = dev_get_drvdata(client->parent); 1420 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); 1421 int err; 1422 1423 hdmi->output.dev = client->dev; 1424 1425 drm_connector_init(drm, &hdmi->output.connector, 1426 &tegra_hdmi_connector_funcs, 1427 DRM_MODE_CONNECTOR_HDMIA); 1428 drm_connector_helper_add(&hdmi->output.connector, 1429 &tegra_hdmi_connector_helper_funcs); 1430 hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF; 1431 1432 drm_encoder_init(drm, &hdmi->output.encoder, &tegra_hdmi_encoder_funcs, 1433 DRM_MODE_ENCODER_TMDS, NULL); 1434 drm_encoder_helper_add(&hdmi->output.encoder, 1435 &tegra_hdmi_encoder_helper_funcs); 1436 1437 drm_connector_attach_encoder(&hdmi->output.connector, 1438 &hdmi->output.encoder); 1439 drm_connector_register(&hdmi->output.connector); 1440 1441 err = tegra_output_init(drm, &hdmi->output); 1442 if (err < 0) { 1443 dev_err(client->dev, "failed to initialize output: %d\n", err); 1444 return err; 1445 } 1446 1447 hdmi->output.encoder.possible_crtcs = 0x3; 1448 1449 err = regulator_enable(hdmi->hdmi); 1450 if (err < 0) { 1451 dev_err(client->dev, "failed to enable HDMI regulator: %d\n", 1452 err); 1453 return err; 1454 } 1455 1456 err = regulator_enable(hdmi->pll); 1457 if (err < 0) { 1458 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err); 1459 return err; 1460 } 1461 1462 err = regulator_enable(hdmi->vdd); 1463 if (err < 0) { 1464 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err); 1465 return err; 1466 } 1467 1468 return 0; 1469 } 1470 1471 static int tegra_hdmi_exit(struct host1x_client *client) 1472 { 1473 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); 1474 1475 tegra_output_exit(&hdmi->output); 1476 1477 regulator_disable(hdmi->vdd); 1478 regulator_disable(hdmi->pll); 1479 regulator_disable(hdmi->hdmi); 1480 1481 return 0; 1482 } 1483 1484 static const struct host1x_client_ops hdmi_client_ops = { 1485 .init = tegra_hdmi_init, 1486 .exit = tegra_hdmi_exit, 1487 }; 1488 1489 static const struct tegra_hdmi_config tegra20_hdmi_config = { 1490 .tmds = tegra20_tmds_config, 1491 .num_tmds = ARRAY_SIZE(tegra20_tmds_config), 1492 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT, 1493 .fuse_override_value = 1 << 31, 1494 .has_sor_io_peak_current = false, 1495 .has_hda = false, 1496 .has_hbr = false, 1497 }; 1498 1499 static const struct tegra_hdmi_config tegra30_hdmi_config = { 1500 .tmds = tegra30_tmds_config, 1501 .num_tmds = ARRAY_SIZE(tegra30_tmds_config), 1502 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT, 1503 .fuse_override_value = 1 << 31, 1504 .has_sor_io_peak_current = false, 1505 .has_hda = true, 1506 .has_hbr = false, 1507 }; 1508 1509 static const struct tegra_hdmi_config tegra114_hdmi_config = { 1510 .tmds = tegra114_tmds_config, 1511 .num_tmds = ARRAY_SIZE(tegra114_tmds_config), 1512 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0, 1513 .fuse_override_value = 1 << 31, 1514 .has_sor_io_peak_current = true, 1515 .has_hda = true, 1516 .has_hbr = true, 1517 }; 1518 1519 static const struct tegra_hdmi_config tegra124_hdmi_config = { 1520 .tmds = tegra124_tmds_config, 1521 .num_tmds = ARRAY_SIZE(tegra124_tmds_config), 1522 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0, 1523 .fuse_override_value = 1 << 31, 1524 .has_sor_io_peak_current = true, 1525 .has_hda = true, 1526 .has_hbr = true, 1527 }; 1528 1529 static const struct of_device_id tegra_hdmi_of_match[] = { 1530 { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config }, 1531 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config }, 1532 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config }, 1533 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config }, 1534 { }, 1535 }; 1536 MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match); 1537 1538 static irqreturn_t tegra_hdmi_irq(int irq, void *data) 1539 { 1540 struct tegra_hdmi *hdmi = data; 1541 u32 value; 1542 int err; 1543 1544 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS); 1545 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS); 1546 1547 if (value & INT_CODEC_SCRATCH0) { 1548 unsigned int format; 1549 u32 value; 1550 1551 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0); 1552 1553 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) { 1554 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK; 1555 1556 tegra_hda_parse_format(format, &hdmi->format); 1557 1558 err = tegra_hdmi_setup_audio(hdmi); 1559 if (err < 0) { 1560 tegra_hdmi_disable_audio_infoframe(hdmi); 1561 tegra_hdmi_disable_audio(hdmi); 1562 } else { 1563 tegra_hdmi_setup_audio_infoframe(hdmi); 1564 tegra_hdmi_enable_audio_infoframe(hdmi); 1565 tegra_hdmi_enable_audio(hdmi); 1566 } 1567 } else { 1568 tegra_hdmi_disable_audio_infoframe(hdmi); 1569 tegra_hdmi_disable_audio(hdmi); 1570 } 1571 } 1572 1573 return IRQ_HANDLED; 1574 } 1575 1576 static int tegra_hdmi_probe(struct platform_device *pdev) 1577 { 1578 struct tegra_hdmi *hdmi; 1579 struct resource *regs; 1580 int err; 1581 1582 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); 1583 if (!hdmi) 1584 return -ENOMEM; 1585 1586 hdmi->config = of_device_get_match_data(&pdev->dev); 1587 hdmi->dev = &pdev->dev; 1588 1589 hdmi->audio_source = AUTO; 1590 hdmi->stereo = false; 1591 hdmi->dvi = false; 1592 1593 hdmi->clk = devm_clk_get(&pdev->dev, NULL); 1594 if (IS_ERR(hdmi->clk)) { 1595 dev_err(&pdev->dev, "failed to get clock\n"); 1596 return PTR_ERR(hdmi->clk); 1597 } 1598 1599 hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi"); 1600 if (IS_ERR(hdmi->rst)) { 1601 dev_err(&pdev->dev, "failed to get reset\n"); 1602 return PTR_ERR(hdmi->rst); 1603 } 1604 1605 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent"); 1606 if (IS_ERR(hdmi->clk_parent)) 1607 return PTR_ERR(hdmi->clk_parent); 1608 1609 err = clk_set_parent(hdmi->clk, hdmi->clk_parent); 1610 if (err < 0) { 1611 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err); 1612 return err; 1613 } 1614 1615 hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi"); 1616 if (IS_ERR(hdmi->hdmi)) { 1617 dev_err(&pdev->dev, "failed to get HDMI regulator\n"); 1618 return PTR_ERR(hdmi->hdmi); 1619 } 1620 1621 hdmi->pll = devm_regulator_get(&pdev->dev, "pll"); 1622 if (IS_ERR(hdmi->pll)) { 1623 dev_err(&pdev->dev, "failed to get PLL regulator\n"); 1624 return PTR_ERR(hdmi->pll); 1625 } 1626 1627 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd"); 1628 if (IS_ERR(hdmi->vdd)) { 1629 dev_err(&pdev->dev, "failed to get VDD regulator\n"); 1630 return PTR_ERR(hdmi->vdd); 1631 } 1632 1633 hdmi->output.dev = &pdev->dev; 1634 1635 err = tegra_output_probe(&hdmi->output); 1636 if (err < 0) 1637 return err; 1638 1639 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1640 hdmi->regs = devm_ioremap_resource(&pdev->dev, regs); 1641 if (IS_ERR(hdmi->regs)) 1642 return PTR_ERR(hdmi->regs); 1643 1644 err = platform_get_irq(pdev, 0); 1645 if (err < 0) 1646 return err; 1647 1648 hdmi->irq = err; 1649 1650 err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0, 1651 dev_name(hdmi->dev), hdmi); 1652 if (err < 0) { 1653 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", 1654 hdmi->irq, err); 1655 return err; 1656 } 1657 1658 platform_set_drvdata(pdev, hdmi); 1659 pm_runtime_enable(&pdev->dev); 1660 1661 INIT_LIST_HEAD(&hdmi->client.list); 1662 hdmi->client.ops = &hdmi_client_ops; 1663 hdmi->client.dev = &pdev->dev; 1664 1665 err = host1x_client_register(&hdmi->client); 1666 if (err < 0) { 1667 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 1668 err); 1669 return err; 1670 } 1671 1672 return 0; 1673 } 1674 1675 static int tegra_hdmi_remove(struct platform_device *pdev) 1676 { 1677 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev); 1678 int err; 1679 1680 pm_runtime_disable(&pdev->dev); 1681 1682 err = host1x_client_unregister(&hdmi->client); 1683 if (err < 0) { 1684 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 1685 err); 1686 return err; 1687 } 1688 1689 tegra_output_remove(&hdmi->output); 1690 1691 return 0; 1692 } 1693 1694 #ifdef CONFIG_PM 1695 static int tegra_hdmi_suspend(struct device *dev) 1696 { 1697 struct tegra_hdmi *hdmi = dev_get_drvdata(dev); 1698 int err; 1699 1700 err = reset_control_assert(hdmi->rst); 1701 if (err < 0) { 1702 dev_err(dev, "failed to assert reset: %d\n", err); 1703 return err; 1704 } 1705 1706 usleep_range(1000, 2000); 1707 1708 clk_disable_unprepare(hdmi->clk); 1709 1710 return 0; 1711 } 1712 1713 static int tegra_hdmi_resume(struct device *dev) 1714 { 1715 struct tegra_hdmi *hdmi = dev_get_drvdata(dev); 1716 int err; 1717 1718 err = clk_prepare_enable(hdmi->clk); 1719 if (err < 0) { 1720 dev_err(dev, "failed to enable clock: %d\n", err); 1721 return err; 1722 } 1723 1724 usleep_range(1000, 2000); 1725 1726 err = reset_control_deassert(hdmi->rst); 1727 if (err < 0) { 1728 dev_err(dev, "failed to deassert reset: %d\n", err); 1729 clk_disable_unprepare(hdmi->clk); 1730 return err; 1731 } 1732 1733 return 0; 1734 } 1735 #endif 1736 1737 static const struct dev_pm_ops tegra_hdmi_pm_ops = { 1738 SET_RUNTIME_PM_OPS(tegra_hdmi_suspend, tegra_hdmi_resume, NULL) 1739 }; 1740 1741 struct platform_driver tegra_hdmi_driver = { 1742 .driver = { 1743 .name = "tegra-hdmi", 1744 .of_match_table = tegra_hdmi_of_match, 1745 .pm = &tegra_hdmi_pm_ops, 1746 }, 1747 .probe = tegra_hdmi_probe, 1748 .remove = tegra_hdmi_remove, 1749 }; 1750