1 /* 2 * Copyright (C) 2012 Avionic Design GmbH 3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/debugfs.h> 12 #include <linux/gpio.h> 13 #include <linux/hdmi.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/clk/tegra.h> 19 20 #include <drm/drm_edid.h> 21 22 #include "hdmi.h" 23 #include "drm.h" 24 #include "dc.h" 25 26 struct tegra_hdmi { 27 struct host1x_client client; 28 struct tegra_output output; 29 struct device *dev; 30 31 struct regulator *vdd; 32 struct regulator *pll; 33 34 void __iomem *regs; 35 unsigned int irq; 36 37 struct clk *clk_parent; 38 struct clk *clk; 39 40 unsigned int audio_source; 41 unsigned int audio_freq; 42 bool stereo; 43 bool dvi; 44 45 struct drm_info_list *debugfs_files; 46 struct drm_minor *minor; 47 struct dentry *debugfs; 48 }; 49 50 static inline struct tegra_hdmi * 51 host1x_client_to_hdmi(struct host1x_client *client) 52 { 53 return container_of(client, struct tegra_hdmi, client); 54 } 55 56 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output) 57 { 58 return container_of(output, struct tegra_hdmi, output); 59 } 60 61 #define HDMI_AUDIOCLK_FREQ 216000000 62 #define HDMI_REKEY_DEFAULT 56 63 64 enum { 65 AUTO = 0, 66 SPDIF, 67 HDA, 68 }; 69 70 static inline unsigned long tegra_hdmi_readl(struct tegra_hdmi *hdmi, 71 unsigned long reg) 72 { 73 return readl(hdmi->regs + (reg << 2)); 74 } 75 76 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, unsigned long val, 77 unsigned long reg) 78 { 79 writel(val, hdmi->regs + (reg << 2)); 80 } 81 82 struct tegra_hdmi_audio_config { 83 unsigned int pclk; 84 unsigned int n; 85 unsigned int cts; 86 unsigned int aval; 87 }; 88 89 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = { 90 { 25200000, 4096, 25200, 24000 }, 91 { 27000000, 4096, 27000, 24000 }, 92 { 74250000, 4096, 74250, 24000 }, 93 { 148500000, 4096, 148500, 24000 }, 94 { 0, 0, 0, 0 }, 95 }; 96 97 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = { 98 { 25200000, 5880, 26250, 25000 }, 99 { 27000000, 5880, 28125, 25000 }, 100 { 74250000, 4704, 61875, 20000 }, 101 { 148500000, 4704, 123750, 20000 }, 102 { 0, 0, 0, 0 }, 103 }; 104 105 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = { 106 { 25200000, 6144, 25200, 24000 }, 107 { 27000000, 6144, 27000, 24000 }, 108 { 74250000, 6144, 74250, 24000 }, 109 { 148500000, 6144, 148500, 24000 }, 110 { 0, 0, 0, 0 }, 111 }; 112 113 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = { 114 { 25200000, 11760, 26250, 25000 }, 115 { 27000000, 11760, 28125, 25000 }, 116 { 74250000, 9408, 61875, 20000 }, 117 { 148500000, 9408, 123750, 20000 }, 118 { 0, 0, 0, 0 }, 119 }; 120 121 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = { 122 { 25200000, 12288, 25200, 24000 }, 123 { 27000000, 12288, 27000, 24000 }, 124 { 74250000, 12288, 74250, 24000 }, 125 { 148500000, 12288, 148500, 24000 }, 126 { 0, 0, 0, 0 }, 127 }; 128 129 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = { 130 { 25200000, 23520, 26250, 25000 }, 131 { 27000000, 23520, 28125, 25000 }, 132 { 74250000, 18816, 61875, 20000 }, 133 { 148500000, 18816, 123750, 20000 }, 134 { 0, 0, 0, 0 }, 135 }; 136 137 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = { 138 { 25200000, 24576, 25200, 24000 }, 139 { 27000000, 24576, 27000, 24000 }, 140 { 74250000, 24576, 74250, 24000 }, 141 { 148500000, 24576, 148500, 24000 }, 142 { 0, 0, 0, 0 }, 143 }; 144 145 struct tmds_config { 146 unsigned int pclk; 147 u32 pll0; 148 u32 pll1; 149 u32 pe_current; 150 u32 drive_current; 151 }; 152 153 static const struct tmds_config tegra2_tmds_config[] = { 154 { /* slow pixel clock modes */ 155 .pclk = 27000000, 156 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 157 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) | 158 SOR_PLL_TX_REG_LOAD(3), 159 .pll1 = SOR_PLL_TMDS_TERM_ENABLE, 160 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) | 161 PE_CURRENT1(PE_CURRENT_0_0_mA) | 162 PE_CURRENT2(PE_CURRENT_0_0_mA) | 163 PE_CURRENT3(PE_CURRENT_0_0_mA), 164 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) | 165 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | 166 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | 167 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), 168 }, 169 { /* high pixel clock modes */ 170 .pclk = UINT_MAX, 171 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 172 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) | 173 SOR_PLL_TX_REG_LOAD(3), 174 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, 175 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) | 176 PE_CURRENT1(PE_CURRENT_6_0_mA) | 177 PE_CURRENT2(PE_CURRENT_6_0_mA) | 178 PE_CURRENT3(PE_CURRENT_6_0_mA), 179 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) | 180 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | 181 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | 182 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), 183 }, 184 }; 185 186 static const struct tmds_config tegra3_tmds_config[] = { 187 { /* 480p modes */ 188 .pclk = 27000000, 189 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 190 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) | 191 SOR_PLL_TX_REG_LOAD(0), 192 .pll1 = SOR_PLL_TMDS_TERM_ENABLE, 193 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) | 194 PE_CURRENT1(PE_CURRENT_0_0_mA) | 195 PE_CURRENT2(PE_CURRENT_0_0_mA) | 196 PE_CURRENT3(PE_CURRENT_0_0_mA), 197 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | 198 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | 199 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | 200 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), 201 }, { /* 720p modes */ 202 .pclk = 74250000, 203 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 204 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) | 205 SOR_PLL_TX_REG_LOAD(0), 206 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, 207 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) | 208 PE_CURRENT1(PE_CURRENT_5_0_mA) | 209 PE_CURRENT2(PE_CURRENT_5_0_mA) | 210 PE_CURRENT3(PE_CURRENT_5_0_mA), 211 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | 212 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | 213 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | 214 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), 215 }, { /* 1080p modes */ 216 .pclk = UINT_MAX, 217 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 218 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) | 219 SOR_PLL_TX_REG_LOAD(0), 220 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, 221 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) | 222 PE_CURRENT1(PE_CURRENT_5_0_mA) | 223 PE_CURRENT2(PE_CURRENT_5_0_mA) | 224 PE_CURRENT3(PE_CURRENT_5_0_mA), 225 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | 226 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | 227 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | 228 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), 229 }, 230 }; 231 232 static const struct tegra_hdmi_audio_config * 233 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk) 234 { 235 const struct tegra_hdmi_audio_config *table; 236 237 switch (audio_freq) { 238 case 32000: 239 table = tegra_hdmi_audio_32k; 240 break; 241 242 case 44100: 243 table = tegra_hdmi_audio_44_1k; 244 break; 245 246 case 48000: 247 table = tegra_hdmi_audio_48k; 248 break; 249 250 case 88200: 251 table = tegra_hdmi_audio_88_2k; 252 break; 253 254 case 96000: 255 table = tegra_hdmi_audio_96k; 256 break; 257 258 case 176400: 259 table = tegra_hdmi_audio_176_4k; 260 break; 261 262 case 192000: 263 table = tegra_hdmi_audio_192k; 264 break; 265 266 default: 267 return NULL; 268 } 269 270 while (table->pclk) { 271 if (table->pclk == pclk) 272 return table; 273 274 table++; 275 } 276 277 return NULL; 278 } 279 280 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi) 281 { 282 const unsigned int freqs[] = { 283 32000, 44100, 48000, 88200, 96000, 176400, 192000 284 }; 285 unsigned int i; 286 287 for (i = 0; i < ARRAY_SIZE(freqs); i++) { 288 unsigned int f = freqs[i]; 289 unsigned int eight_half; 290 unsigned long value; 291 unsigned int delta; 292 293 if (f > 96000) 294 delta = 2; 295 else if (f > 480000) 296 delta = 6; 297 else 298 delta = 9; 299 300 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128); 301 value = AUDIO_FS_LOW(eight_half - delta) | 302 AUDIO_FS_HIGH(eight_half + delta); 303 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i)); 304 } 305 } 306 307 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk) 308 { 309 struct device_node *node = hdmi->dev->of_node; 310 const struct tegra_hdmi_audio_config *config; 311 unsigned int offset = 0; 312 unsigned long value; 313 314 switch (hdmi->audio_source) { 315 case HDA: 316 value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL; 317 break; 318 319 case SPDIF: 320 value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF; 321 break; 322 323 default: 324 value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO; 325 break; 326 } 327 328 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) { 329 value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) | 330 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0); 331 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0); 332 } else { 333 value |= AUDIO_CNTRL0_INJECT_NULLSMPL; 334 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0); 335 336 value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) | 337 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0); 338 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0); 339 } 340 341 config = tegra_hdmi_get_audio_config(hdmi->audio_freq, pclk); 342 if (!config) { 343 dev_err(hdmi->dev, "cannot set audio to %u at %u pclk\n", 344 hdmi->audio_freq, pclk); 345 return -EINVAL; 346 } 347 348 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL); 349 350 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE | 351 AUDIO_N_VALUE(config->n - 1); 352 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N); 353 354 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE, 355 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH); 356 357 value = ACR_SUBPACK_CTS(config->cts); 358 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW); 359 360 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1); 361 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE); 362 363 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N); 364 value &= ~AUDIO_N_RESETF; 365 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N); 366 367 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) { 368 switch (hdmi->audio_freq) { 369 case 32000: 370 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320; 371 break; 372 373 case 44100: 374 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441; 375 break; 376 377 case 48000: 378 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480; 379 break; 380 381 case 88200: 382 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882; 383 break; 384 385 case 96000: 386 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960; 387 break; 388 389 case 176400: 390 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764; 391 break; 392 393 case 192000: 394 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920; 395 break; 396 } 397 398 tegra_hdmi_writel(hdmi, config->aval, offset); 399 } 400 401 tegra_hdmi_setup_audio_fs_tables(hdmi); 402 403 return 0; 404 } 405 406 static inline unsigned long tegra_hdmi_subpack(const u8 *ptr, size_t size) 407 { 408 unsigned long value = 0; 409 size_t i; 410 411 for (i = size; i > 0; i--) 412 value = (value << 8) | ptr[i - 1]; 413 414 return value; 415 } 416 417 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data, 418 size_t size) 419 { 420 const u8 *ptr = data; 421 unsigned long offset; 422 unsigned long value; 423 size_t i, j; 424 425 switch (ptr[0]) { 426 case HDMI_INFOFRAME_TYPE_AVI: 427 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER; 428 break; 429 430 case HDMI_INFOFRAME_TYPE_AUDIO: 431 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER; 432 break; 433 434 case HDMI_INFOFRAME_TYPE_VENDOR: 435 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER; 436 break; 437 438 default: 439 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n", 440 ptr[0]); 441 return; 442 } 443 444 value = INFOFRAME_HEADER_TYPE(ptr[0]) | 445 INFOFRAME_HEADER_VERSION(ptr[1]) | 446 INFOFRAME_HEADER_LEN(ptr[2]); 447 tegra_hdmi_writel(hdmi, value, offset); 448 offset++; 449 450 /* 451 * Each subpack contains 7 bytes, divided into: 452 * - subpack_low: bytes 0 - 3 453 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) 454 */ 455 for (i = 3, j = 0; i < size; i += 7, j += 8) { 456 size_t rem = size - i, num = min_t(size_t, rem, 4); 457 458 value = tegra_hdmi_subpack(&ptr[i], num); 459 tegra_hdmi_writel(hdmi, value, offset++); 460 461 num = min_t(size_t, rem - num, 3); 462 463 value = tegra_hdmi_subpack(&ptr[i + 4], num); 464 tegra_hdmi_writel(hdmi, value, offset++); 465 } 466 } 467 468 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi, 469 struct drm_display_mode *mode) 470 { 471 struct hdmi_avi_infoframe frame; 472 u8 buffer[17]; 473 ssize_t err; 474 475 if (hdmi->dvi) { 476 tegra_hdmi_writel(hdmi, 0, 477 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); 478 return; 479 } 480 481 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 482 if (err < 0) { 483 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err); 484 return; 485 } 486 487 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 488 if (err < 0) { 489 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err); 490 return; 491 } 492 493 tegra_hdmi_write_infopack(hdmi, buffer, err); 494 495 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE, 496 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); 497 } 498 499 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi) 500 { 501 struct hdmi_audio_infoframe frame; 502 u8 buffer[14]; 503 ssize_t err; 504 505 if (hdmi->dvi) { 506 tegra_hdmi_writel(hdmi, 0, 507 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); 508 return; 509 } 510 511 err = hdmi_audio_infoframe_init(&frame); 512 if (err < 0) { 513 dev_err(hdmi->dev, "failed to initialize audio infoframe: %d\n", 514 err); 515 return; 516 } 517 518 frame.channels = 2; 519 520 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 521 if (err < 0) { 522 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n", 523 err); 524 return; 525 } 526 527 /* 528 * The audio infoframe has only one set of subpack registers, so the 529 * infoframe needs to be truncated. One set of subpack registers can 530 * contain 7 bytes. Including the 3 byte header only the first 10 531 * bytes can be programmed. 532 */ 533 tegra_hdmi_write_infopack(hdmi, buffer, min(10, err)); 534 535 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE, 536 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); 537 } 538 539 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi) 540 { 541 struct hdmi_vendor_infoframe frame; 542 unsigned long value; 543 u8 buffer[10]; 544 ssize_t err; 545 546 if (!hdmi->stereo) { 547 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 548 value &= ~GENERIC_CTRL_ENABLE; 549 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 550 return; 551 } 552 553 memset(&frame, 0, sizeof(frame)); 554 555 frame.type = HDMI_INFOFRAME_TYPE_VENDOR; 556 frame.version = 0x01; 557 frame.length = 6; 558 559 frame.data[0] = 0x03; /* regid0 */ 560 frame.data[1] = 0x0c; /* regid1 */ 561 frame.data[2] = 0x00; /* regid2 */ 562 frame.data[3] = 0x02 << 5; /* video format */ 563 564 /* TODO: 74 MHz limit? */ 565 if (1) { 566 frame.data[4] = 0x00 << 4; /* 3D structure */ 567 } else { 568 frame.data[4] = 0x08 << 4; /* 3D structure */ 569 frame.data[5] = 0x00 << 4; /* 3D ext. data */ 570 } 571 572 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 573 if (err < 0) { 574 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n", 575 err); 576 return; 577 } 578 579 tegra_hdmi_write_infopack(hdmi, buffer, err); 580 581 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 582 value |= GENERIC_CTRL_ENABLE; 583 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 584 } 585 586 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi, 587 const struct tmds_config *tmds) 588 { 589 unsigned long value; 590 591 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0); 592 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); 593 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT); 594 595 value = tmds->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE; 596 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT); 597 } 598 599 static int tegra_output_hdmi_enable(struct tegra_output *output) 600 { 601 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey; 602 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); 603 struct drm_display_mode *mode = &dc->base.mode; 604 struct tegra_hdmi *hdmi = to_hdmi(output); 605 struct device_node *node = hdmi->dev->of_node; 606 unsigned int pulse_start, div82, pclk; 607 const struct tmds_config *tmds; 608 unsigned int num_tmds; 609 unsigned long value; 610 int retries = 1000; 611 int err; 612 613 pclk = mode->clock * 1000; 614 h_sync_width = mode->hsync_end - mode->hsync_start; 615 h_back_porch = mode->htotal - mode->hsync_end; 616 h_front_porch = mode->hsync_start - mode->hdisplay; 617 618 err = regulator_enable(hdmi->vdd); 619 if (err < 0) { 620 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err); 621 return err; 622 } 623 624 err = regulator_enable(hdmi->pll); 625 if (err < 0) { 626 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err); 627 return err; 628 } 629 630 /* 631 * This assumes that the display controller will divide its parent 632 * clock by 2 to generate the pixel clock. 633 */ 634 err = tegra_output_setup_clock(output, hdmi->clk, pclk * 2); 635 if (err < 0) { 636 dev_err(hdmi->dev, "failed to setup clock: %d\n", err); 637 return err; 638 } 639 640 err = clk_set_rate(hdmi->clk, pclk); 641 if (err < 0) 642 return err; 643 644 err = clk_enable(hdmi->clk); 645 if (err < 0) { 646 dev_err(hdmi->dev, "failed to enable clock: %d\n", err); 647 return err; 648 } 649 650 tegra_periph_reset_assert(hdmi->clk); 651 usleep_range(1000, 2000); 652 tegra_periph_reset_deassert(hdmi->clk); 653 654 tegra_dc_writel(dc, VSYNC_H_POSITION(1), 655 DC_DISP_DISP_TIMING_OPTIONS); 656 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888, 657 DC_DISP_DISP_COLOR_CONTROL); 658 659 /* video_preamble uses h_pulse2 */ 660 pulse_start = 1 + h_sync_width + h_back_porch - 10; 661 662 tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0); 663 664 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE | 665 PULSE_LAST_END_A; 666 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); 667 668 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8); 669 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); 670 671 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) | 672 VSYNC_WINDOW_ENABLE; 673 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW); 674 675 if (dc->pipe) 676 value = HDMI_SRC_DISPLAYB; 677 else 678 value = HDMI_SRC_DISPLAYA; 679 680 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) || 681 (mode->vdisplay == 576))) 682 tegra_hdmi_writel(hdmi, 683 value | ARM_VIDEO_RANGE_FULL, 684 HDMI_NV_PDISP_INPUT_CONTROL); 685 else 686 tegra_hdmi_writel(hdmi, 687 value | ARM_VIDEO_RANGE_LIMITED, 688 HDMI_NV_PDISP_INPUT_CONTROL); 689 690 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4; 691 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82); 692 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK); 693 694 if (!hdmi->dvi) { 695 err = tegra_hdmi_setup_audio(hdmi, pclk); 696 if (err < 0) 697 hdmi->dvi = true; 698 } 699 700 if (of_device_is_compatible(node, "nvidia,tegra20-hdmi")) { 701 /* 702 * TODO: add ELD support 703 */ 704 } 705 706 rekey = HDMI_REKEY_DEFAULT; 707 value = HDMI_CTRL_REKEY(rekey); 708 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch + 709 h_front_porch - rekey - 18) / 32); 710 711 if (!hdmi->dvi) 712 value |= HDMI_CTRL_ENABLE; 713 714 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL); 715 716 if (hdmi->dvi) 717 tegra_hdmi_writel(hdmi, 0x0, 718 HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 719 else 720 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO, 721 HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 722 723 tegra_hdmi_setup_avi_infoframe(hdmi, mode); 724 tegra_hdmi_setup_audio_infoframe(hdmi); 725 tegra_hdmi_setup_stereo_infoframe(hdmi); 726 727 /* TMDS CONFIG */ 728 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) { 729 num_tmds = ARRAY_SIZE(tegra3_tmds_config); 730 tmds = tegra3_tmds_config; 731 } else { 732 num_tmds = ARRAY_SIZE(tegra2_tmds_config); 733 tmds = tegra2_tmds_config; 734 } 735 736 for (i = 0; i < num_tmds; i++) { 737 if (pclk <= tmds[i].pclk) { 738 tegra_hdmi_setup_tmds(hdmi, &tmds[i]); 739 break; 740 } 741 } 742 743 tegra_hdmi_writel(hdmi, 744 SOR_SEQ_CTL_PU_PC(0) | 745 SOR_SEQ_PU_PC_ALT(0) | 746 SOR_SEQ_PD_PC(8) | 747 SOR_SEQ_PD_PC_ALT(8), 748 HDMI_NV_PDISP_SOR_SEQ_CTL); 749 750 value = SOR_SEQ_INST_WAIT_TIME(1) | 751 SOR_SEQ_INST_WAIT_UNITS_VSYNC | 752 SOR_SEQ_INST_HALT | 753 SOR_SEQ_INST_PIN_A_LOW | 754 SOR_SEQ_INST_PIN_B_LOW | 755 SOR_SEQ_INST_DRIVE_PWM_OUT_LO; 756 757 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0)); 758 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8)); 759 760 value = 0x1c800; 761 value &= ~SOR_CSTM_ROTCLK(~0); 762 value |= SOR_CSTM_ROTCLK(2); 763 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM); 764 765 tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND); 766 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); 767 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 768 769 /* start SOR */ 770 tegra_hdmi_writel(hdmi, 771 SOR_PWR_NORMAL_STATE_PU | 772 SOR_PWR_NORMAL_START_NORMAL | 773 SOR_PWR_SAFE_STATE_PD | 774 SOR_PWR_SETTING_NEW_TRIGGER, 775 HDMI_NV_PDISP_SOR_PWR); 776 tegra_hdmi_writel(hdmi, 777 SOR_PWR_NORMAL_STATE_PU | 778 SOR_PWR_NORMAL_START_NORMAL | 779 SOR_PWR_SAFE_STATE_PD | 780 SOR_PWR_SETTING_NEW_DONE, 781 HDMI_NV_PDISP_SOR_PWR); 782 783 do { 784 BUG_ON(--retries < 0); 785 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR); 786 } while (value & SOR_PWR_SETTING_NEW_PENDING); 787 788 value = SOR_STATE_ASY_CRCMODE_COMPLETE | 789 SOR_STATE_ASY_OWNER_HEAD0 | 790 SOR_STATE_ASY_SUBOWNER_BOTH | 791 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A | 792 SOR_STATE_ASY_DEPOL_POS; 793 794 /* setup sync polarities */ 795 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 796 value |= SOR_STATE_ASY_HSYNCPOL_POS; 797 798 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 799 value |= SOR_STATE_ASY_HSYNCPOL_NEG; 800 801 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 802 value |= SOR_STATE_ASY_VSYNCPOL_POS; 803 804 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 805 value |= SOR_STATE_ASY_VSYNCPOL_NEG; 806 807 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2); 808 809 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL; 810 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1); 811 812 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0); 813 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0); 814 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED, 815 HDMI_NV_PDISP_SOR_STATE1); 816 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0); 817 818 tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS); 819 820 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 821 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; 822 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 823 824 value = DISP_CTRL_MODE_C_DISPLAY; 825 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 826 827 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); 828 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 829 830 /* TODO: add HDCP support */ 831 832 return 0; 833 } 834 835 static int tegra_output_hdmi_disable(struct tegra_output *output) 836 { 837 struct tegra_hdmi *hdmi = to_hdmi(output); 838 839 tegra_periph_reset_assert(hdmi->clk); 840 clk_disable(hdmi->clk); 841 regulator_disable(hdmi->pll); 842 regulator_disable(hdmi->vdd); 843 844 return 0; 845 } 846 847 static int tegra_output_hdmi_setup_clock(struct tegra_output *output, 848 struct clk *clk, unsigned long pclk) 849 { 850 struct tegra_hdmi *hdmi = to_hdmi(output); 851 struct clk *base; 852 int err; 853 854 err = clk_set_parent(clk, hdmi->clk_parent); 855 if (err < 0) { 856 dev_err(output->dev, "failed to set parent: %d\n", err); 857 return err; 858 } 859 860 base = clk_get_parent(hdmi->clk_parent); 861 862 /* 863 * This assumes that the parent clock is pll_d_out0 or pll_d2_out 864 * respectively, each of which divides the base pll_d by 2. 865 */ 866 err = clk_set_rate(base, pclk * 2); 867 if (err < 0) 868 dev_err(output->dev, 869 "failed to set base clock rate to %lu Hz\n", 870 pclk * 2); 871 872 return 0; 873 } 874 875 static int tegra_output_hdmi_check_mode(struct tegra_output *output, 876 struct drm_display_mode *mode, 877 enum drm_mode_status *status) 878 { 879 struct tegra_hdmi *hdmi = to_hdmi(output); 880 unsigned long pclk = mode->clock * 1000; 881 struct clk *parent; 882 long err; 883 884 parent = clk_get_parent(hdmi->clk_parent); 885 886 err = clk_round_rate(parent, pclk * 4); 887 if (err < 0) 888 *status = MODE_NOCLOCK; 889 else 890 *status = MODE_OK; 891 892 return 0; 893 } 894 895 static const struct tegra_output_ops hdmi_ops = { 896 .enable = tegra_output_hdmi_enable, 897 .disable = tegra_output_hdmi_disable, 898 .setup_clock = tegra_output_hdmi_setup_clock, 899 .check_mode = tegra_output_hdmi_check_mode, 900 }; 901 902 static int tegra_hdmi_show_regs(struct seq_file *s, void *data) 903 { 904 struct drm_info_node *node = s->private; 905 struct tegra_hdmi *hdmi = node->info_ent->data; 906 907 #define DUMP_REG(name) \ 908 seq_printf(s, "%-56s %#05x %08lx\n", #name, name, \ 909 tegra_hdmi_readl(hdmi, name)) 910 911 DUMP_REG(HDMI_CTXSW); 912 DUMP_REG(HDMI_NV_PDISP_SOR_STATE0); 913 DUMP_REG(HDMI_NV_PDISP_SOR_STATE1); 914 DUMP_REG(HDMI_NV_PDISP_SOR_STATE2); 915 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB); 916 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB); 917 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB); 918 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB); 919 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB); 920 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB); 921 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB); 922 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB); 923 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB); 924 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB); 925 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB); 926 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB); 927 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL); 928 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE); 929 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB); 930 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB); 931 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB); 932 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2); 933 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1); 934 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI); 935 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB); 936 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB); 937 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0); 938 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0); 939 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1); 940 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2); 941 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); 942 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS); 943 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER); 944 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW); 945 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH); 946 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); 947 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS); 948 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER); 949 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW); 950 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH); 951 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW); 952 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH); 953 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 954 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS); 955 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER); 956 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW); 957 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH); 958 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW); 959 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH); 960 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW); 961 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH); 962 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW); 963 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH); 964 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL); 965 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW); 966 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH); 967 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW); 968 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH); 969 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW); 970 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH); 971 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW); 972 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH); 973 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW); 974 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH); 975 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW); 976 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH); 977 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW); 978 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH); 979 DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL); 980 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT); 981 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW); 982 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL); 983 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS); 984 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK); 985 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1); 986 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2); 987 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0); 988 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1); 989 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA); 990 DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE); 991 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1); 992 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2); 993 DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL); 994 DUMP_REG(HDMI_NV_PDISP_SOR_CAP); 995 DUMP_REG(HDMI_NV_PDISP_SOR_PWR); 996 DUMP_REG(HDMI_NV_PDISP_SOR_TEST); 997 DUMP_REG(HDMI_NV_PDISP_SOR_PLL0); 998 DUMP_REG(HDMI_NV_PDISP_SOR_PLL1); 999 DUMP_REG(HDMI_NV_PDISP_SOR_PLL2); 1000 DUMP_REG(HDMI_NV_PDISP_SOR_CSTM); 1001 DUMP_REG(HDMI_NV_PDISP_SOR_LVDS); 1002 DUMP_REG(HDMI_NV_PDISP_SOR_CRCA); 1003 DUMP_REG(HDMI_NV_PDISP_SOR_CRCB); 1004 DUMP_REG(HDMI_NV_PDISP_SOR_BLANK); 1005 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL); 1006 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0)); 1007 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1)); 1008 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2)); 1009 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3)); 1010 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4)); 1011 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5)); 1012 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6)); 1013 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7)); 1014 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8)); 1015 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9)); 1016 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10)); 1017 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11)); 1018 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12)); 1019 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13)); 1020 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14)); 1021 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15)); 1022 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0); 1023 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1); 1024 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0); 1025 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1); 1026 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0); 1027 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1); 1028 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0); 1029 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1); 1030 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0); 1031 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1); 1032 DUMP_REG(HDMI_NV_PDISP_SOR_TRIG); 1033 DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK); 1034 DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT); 1035 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0); 1036 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1); 1037 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2); 1038 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0)); 1039 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1)); 1040 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2)); 1041 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3)); 1042 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4)); 1043 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5)); 1044 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6)); 1045 DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH); 1046 DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD); 1047 DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0); 1048 DUMP_REG(HDMI_NV_PDISP_AUDIO_N); 1049 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING); 1050 DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK); 1051 DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL); 1052 DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL); 1053 DUMP_REG(HDMI_NV_PDISP_SCRATCH); 1054 DUMP_REG(HDMI_NV_PDISP_PE_CURRENT); 1055 DUMP_REG(HDMI_NV_PDISP_KEY_CTRL); 1056 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0); 1057 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1); 1058 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2); 1059 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0); 1060 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1); 1061 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2); 1062 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3); 1063 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG); 1064 DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX); 1065 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0); 1066 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR); 1067 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE); 1068 1069 #undef DUMP_REG 1070 1071 return 0; 1072 } 1073 1074 static struct drm_info_list debugfs_files[] = { 1075 { "regs", tegra_hdmi_show_regs, 0, NULL }, 1076 }; 1077 1078 static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi, 1079 struct drm_minor *minor) 1080 { 1081 unsigned int i; 1082 int err; 1083 1084 hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root); 1085 if (!hdmi->debugfs) 1086 return -ENOMEM; 1087 1088 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1089 GFP_KERNEL); 1090 if (!hdmi->debugfs_files) { 1091 err = -ENOMEM; 1092 goto remove; 1093 } 1094 1095 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) 1096 hdmi->debugfs_files[i].data = hdmi; 1097 1098 err = drm_debugfs_create_files(hdmi->debugfs_files, 1099 ARRAY_SIZE(debugfs_files), 1100 hdmi->debugfs, minor); 1101 if (err < 0) 1102 goto free; 1103 1104 hdmi->minor = minor; 1105 1106 return 0; 1107 1108 free: 1109 kfree(hdmi->debugfs_files); 1110 hdmi->debugfs_files = NULL; 1111 remove: 1112 debugfs_remove(hdmi->debugfs); 1113 hdmi->debugfs = NULL; 1114 1115 return err; 1116 } 1117 1118 static int tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi) 1119 { 1120 drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files), 1121 hdmi->minor); 1122 hdmi->minor = NULL; 1123 1124 kfree(hdmi->debugfs_files); 1125 hdmi->debugfs_files = NULL; 1126 1127 debugfs_remove(hdmi->debugfs); 1128 hdmi->debugfs = NULL; 1129 1130 return 0; 1131 } 1132 1133 static int tegra_hdmi_drm_init(struct host1x_client *client, 1134 struct drm_device *drm) 1135 { 1136 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); 1137 int err; 1138 1139 hdmi->output.type = TEGRA_OUTPUT_HDMI; 1140 hdmi->output.dev = client->dev; 1141 hdmi->output.ops = &hdmi_ops; 1142 1143 err = tegra_output_init(drm, &hdmi->output); 1144 if (err < 0) { 1145 dev_err(client->dev, "output setup failed: %d\n", err); 1146 return err; 1147 } 1148 1149 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1150 err = tegra_hdmi_debugfs_init(hdmi, drm->primary); 1151 if (err < 0) 1152 dev_err(client->dev, "debugfs setup failed: %d\n", err); 1153 } 1154 1155 return 0; 1156 } 1157 1158 static int tegra_hdmi_drm_exit(struct host1x_client *client) 1159 { 1160 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); 1161 int err; 1162 1163 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1164 err = tegra_hdmi_debugfs_exit(hdmi); 1165 if (err < 0) 1166 dev_err(client->dev, "debugfs cleanup failed: %d\n", 1167 err); 1168 } 1169 1170 err = tegra_output_disable(&hdmi->output); 1171 if (err < 0) { 1172 dev_err(client->dev, "output failed to disable: %d\n", err); 1173 return err; 1174 } 1175 1176 err = tegra_output_exit(&hdmi->output); 1177 if (err < 0) { 1178 dev_err(client->dev, "output cleanup failed: %d\n", err); 1179 return err; 1180 } 1181 1182 return 0; 1183 } 1184 1185 static const struct host1x_client_ops hdmi_client_ops = { 1186 .drm_init = tegra_hdmi_drm_init, 1187 .drm_exit = tegra_hdmi_drm_exit, 1188 }; 1189 1190 static int tegra_hdmi_probe(struct platform_device *pdev) 1191 { 1192 struct host1x *host1x = dev_get_drvdata(pdev->dev.parent); 1193 struct tegra_hdmi *hdmi; 1194 struct resource *regs; 1195 int err; 1196 1197 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); 1198 if (!hdmi) 1199 return -ENOMEM; 1200 1201 hdmi->dev = &pdev->dev; 1202 hdmi->audio_source = AUTO; 1203 hdmi->audio_freq = 44100; 1204 hdmi->stereo = false; 1205 hdmi->dvi = false; 1206 1207 hdmi->clk = devm_clk_get(&pdev->dev, NULL); 1208 if (IS_ERR(hdmi->clk)) { 1209 dev_err(&pdev->dev, "failed to get clock\n"); 1210 return PTR_ERR(hdmi->clk); 1211 } 1212 1213 err = clk_prepare(hdmi->clk); 1214 if (err < 0) 1215 return err; 1216 1217 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent"); 1218 if (IS_ERR(hdmi->clk_parent)) 1219 return PTR_ERR(hdmi->clk_parent); 1220 1221 err = clk_prepare(hdmi->clk_parent); 1222 if (err < 0) 1223 return err; 1224 1225 err = clk_set_parent(hdmi->clk, hdmi->clk_parent); 1226 if (err < 0) { 1227 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err); 1228 return err; 1229 } 1230 1231 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd"); 1232 if (IS_ERR(hdmi->vdd)) { 1233 dev_err(&pdev->dev, "failed to get VDD regulator\n"); 1234 return PTR_ERR(hdmi->vdd); 1235 } 1236 1237 hdmi->pll = devm_regulator_get(&pdev->dev, "pll"); 1238 if (IS_ERR(hdmi->pll)) { 1239 dev_err(&pdev->dev, "failed to get PLL regulator\n"); 1240 return PTR_ERR(hdmi->pll); 1241 } 1242 1243 hdmi->output.dev = &pdev->dev; 1244 1245 err = tegra_output_parse_dt(&hdmi->output); 1246 if (err < 0) 1247 return err; 1248 1249 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1250 if (!regs) 1251 return -ENXIO; 1252 1253 hdmi->regs = devm_ioremap_resource(&pdev->dev, regs); 1254 if (IS_ERR(hdmi->regs)) 1255 return PTR_ERR(hdmi->regs); 1256 1257 err = platform_get_irq(pdev, 0); 1258 if (err < 0) 1259 return err; 1260 1261 hdmi->irq = err; 1262 1263 hdmi->client.ops = &hdmi_client_ops; 1264 INIT_LIST_HEAD(&hdmi->client.list); 1265 hdmi->client.dev = &pdev->dev; 1266 1267 err = host1x_register_client(host1x, &hdmi->client); 1268 if (err < 0) { 1269 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 1270 err); 1271 return err; 1272 } 1273 1274 platform_set_drvdata(pdev, hdmi); 1275 1276 return 0; 1277 } 1278 1279 static int tegra_hdmi_remove(struct platform_device *pdev) 1280 { 1281 struct host1x *host1x = dev_get_drvdata(pdev->dev.parent); 1282 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev); 1283 int err; 1284 1285 err = host1x_unregister_client(host1x, &hdmi->client); 1286 if (err < 0) { 1287 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 1288 err); 1289 return err; 1290 } 1291 1292 clk_unprepare(hdmi->clk_parent); 1293 clk_unprepare(hdmi->clk); 1294 1295 return 0; 1296 } 1297 1298 static struct of_device_id tegra_hdmi_of_match[] = { 1299 { .compatible = "nvidia,tegra30-hdmi", }, 1300 { .compatible = "nvidia,tegra20-hdmi", }, 1301 { }, 1302 }; 1303 1304 struct platform_driver tegra_hdmi_driver = { 1305 .driver = { 1306 .name = "tegra-hdmi", 1307 .owner = THIS_MODULE, 1308 .of_match_table = tegra_hdmi_of_match, 1309 }, 1310 .probe = tegra_hdmi_probe, 1311 .remove = tegra_hdmi_remove, 1312 }; 1313