1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Avionic Design GmbH 4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/debugfs.h> 9 #include <linux/delay.h> 10 #include <linux/hdmi.h> 11 #include <linux/math64.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/reset.h> 17 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_crtc.h> 20 #include <drm/drm_debugfs.h> 21 #include <drm/drm_file.h> 22 #include <drm/drm_fourcc.h> 23 #include <drm/drm_probe_helper.h> 24 #include <drm/drm_simple_kms_helper.h> 25 26 #include "hda.h" 27 #include "hdmi.h" 28 #include "drm.h" 29 #include "dc.h" 30 #include "trace.h" 31 32 #define HDMI_ELD_BUFFER_SIZE 96 33 34 struct tmds_config { 35 unsigned int pclk; 36 u32 pll0; 37 u32 pll1; 38 u32 pe_current; 39 u32 drive_current; 40 u32 peak_current; 41 }; 42 43 struct tegra_hdmi_config { 44 const struct tmds_config *tmds; 45 unsigned int num_tmds; 46 47 unsigned long fuse_override_offset; 48 u32 fuse_override_value; 49 50 bool has_sor_io_peak_current; 51 bool has_hda; 52 bool has_hbr; 53 }; 54 55 struct tegra_hdmi { 56 struct host1x_client client; 57 struct tegra_output output; 58 struct device *dev; 59 60 struct regulator *hdmi; 61 struct regulator *pll; 62 struct regulator *vdd; 63 64 void __iomem *regs; 65 unsigned int irq; 66 67 struct clk *clk_parent; 68 struct clk *clk; 69 struct reset_control *rst; 70 71 const struct tegra_hdmi_config *config; 72 73 unsigned int audio_source; 74 struct tegra_hda_format format; 75 76 unsigned int pixel_clock; 77 bool stereo; 78 bool dvi; 79 80 struct drm_info_list *debugfs_files; 81 }; 82 83 static inline struct tegra_hdmi * 84 host1x_client_to_hdmi(struct host1x_client *client) 85 { 86 return container_of(client, struct tegra_hdmi, client); 87 } 88 89 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output) 90 { 91 return container_of(output, struct tegra_hdmi, output); 92 } 93 94 #define HDMI_AUDIOCLK_FREQ 216000000 95 #define HDMI_REKEY_DEFAULT 56 96 97 enum { 98 AUTO = 0, 99 SPDIF, 100 HDA, 101 }; 102 103 static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi, 104 unsigned int offset) 105 { 106 u32 value = readl(hdmi->regs + (offset << 2)); 107 108 trace_hdmi_readl(hdmi->dev, offset, value); 109 110 return value; 111 } 112 113 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value, 114 unsigned int offset) 115 { 116 trace_hdmi_writel(hdmi->dev, offset, value); 117 writel(value, hdmi->regs + (offset << 2)); 118 } 119 120 struct tegra_hdmi_audio_config { 121 unsigned int n; 122 unsigned int cts; 123 unsigned int aval; 124 }; 125 126 static const struct tmds_config tegra20_tmds_config[] = { 127 { /* slow pixel clock modes */ 128 .pclk = 27000000, 129 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 130 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) | 131 SOR_PLL_TX_REG_LOAD(3), 132 .pll1 = SOR_PLL_TMDS_TERM_ENABLE, 133 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) | 134 PE_CURRENT1(PE_CURRENT_0_0_mA) | 135 PE_CURRENT2(PE_CURRENT_0_0_mA) | 136 PE_CURRENT3(PE_CURRENT_0_0_mA), 137 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) | 138 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | 139 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | 140 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), 141 }, 142 { /* high pixel clock modes */ 143 .pclk = UINT_MAX, 144 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 145 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) | 146 SOR_PLL_TX_REG_LOAD(3), 147 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, 148 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) | 149 PE_CURRENT1(PE_CURRENT_6_0_mA) | 150 PE_CURRENT2(PE_CURRENT_6_0_mA) | 151 PE_CURRENT3(PE_CURRENT_6_0_mA), 152 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) | 153 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) | 154 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) | 155 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA), 156 }, 157 }; 158 159 static const struct tmds_config tegra30_tmds_config[] = { 160 { /* 480p modes */ 161 .pclk = 27000000, 162 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 163 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) | 164 SOR_PLL_TX_REG_LOAD(0), 165 .pll1 = SOR_PLL_TMDS_TERM_ENABLE, 166 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) | 167 PE_CURRENT1(PE_CURRENT_0_0_mA) | 168 PE_CURRENT2(PE_CURRENT_0_0_mA) | 169 PE_CURRENT3(PE_CURRENT_0_0_mA), 170 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | 171 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | 172 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | 173 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), 174 }, { /* 720p modes */ 175 .pclk = 74250000, 176 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 177 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) | 178 SOR_PLL_TX_REG_LOAD(0), 179 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, 180 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) | 181 PE_CURRENT1(PE_CURRENT_5_0_mA) | 182 PE_CURRENT2(PE_CURRENT_5_0_mA) | 183 PE_CURRENT3(PE_CURRENT_5_0_mA), 184 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | 185 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | 186 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | 187 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), 188 }, { /* 1080p modes */ 189 .pclk = UINT_MAX, 190 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) | 191 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) | 192 SOR_PLL_TX_REG_LOAD(0), 193 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN, 194 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) | 195 PE_CURRENT1(PE_CURRENT_5_0_mA) | 196 PE_CURRENT2(PE_CURRENT_5_0_mA) | 197 PE_CURRENT3(PE_CURRENT_5_0_mA), 198 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) | 199 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) | 200 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) | 201 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA), 202 }, 203 }; 204 205 static const struct tmds_config tegra114_tmds_config[] = { 206 { /* 480p/576p / 25.2MHz/27MHz modes */ 207 .pclk = 27000000, 208 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 209 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL, 210 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), 211 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | 212 PE_CURRENT1(PE_CURRENT_0_mA_T114) | 213 PE_CURRENT2(PE_CURRENT_0_mA_T114) | 214 PE_CURRENT3(PE_CURRENT_0_mA_T114), 215 .drive_current = 216 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | 217 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | 218 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | 219 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), 220 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 221 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 222 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 223 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 224 }, { /* 720p / 74.25MHz modes */ 225 .pclk = 74250000, 226 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 227 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL, 228 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | 229 SOR_PLL_TMDS_TERMADJ(0), 230 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) | 231 PE_CURRENT1(PE_CURRENT_15_mA_T114) | 232 PE_CURRENT2(PE_CURRENT_15_mA_T114) | 233 PE_CURRENT3(PE_CURRENT_15_mA_T114), 234 .drive_current = 235 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | 236 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | 237 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | 238 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), 239 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 240 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 241 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 242 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 243 }, { /* 1080p / 148.5MHz modes */ 244 .pclk = 148500000, 245 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 246 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL, 247 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | 248 SOR_PLL_TMDS_TERMADJ(0), 249 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) | 250 PE_CURRENT1(PE_CURRENT_10_mA_T114) | 251 PE_CURRENT2(PE_CURRENT_10_mA_T114) | 252 PE_CURRENT3(PE_CURRENT_10_mA_T114), 253 .drive_current = 254 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) | 255 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) | 256 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) | 257 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114), 258 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 259 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 260 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 261 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 262 }, { /* 225/297MHz modes */ 263 .pclk = UINT_MAX, 264 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 265 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL, 266 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7) 267 | SOR_PLL_TMDS_TERM_ENABLE, 268 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | 269 PE_CURRENT1(PE_CURRENT_0_mA_T114) | 270 PE_CURRENT2(PE_CURRENT_0_mA_T114) | 271 PE_CURRENT3(PE_CURRENT_0_mA_T114), 272 .drive_current = 273 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) | 274 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) | 275 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) | 276 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114), 277 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) | 278 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) | 279 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) | 280 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA), 281 }, 282 }; 283 284 static const struct tmds_config tegra124_tmds_config[] = { 285 { /* 480p/576p / 25.2MHz/27MHz modes */ 286 .pclk = 27000000, 287 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 288 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL, 289 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0), 290 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | 291 PE_CURRENT1(PE_CURRENT_0_mA_T114) | 292 PE_CURRENT2(PE_CURRENT_0_mA_T114) | 293 PE_CURRENT3(PE_CURRENT_0_mA_T114), 294 .drive_current = 295 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | 296 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | 297 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | 298 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), 299 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 300 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 301 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 302 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 303 }, { /* 720p / 74.25MHz modes */ 304 .pclk = 74250000, 305 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 306 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL, 307 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | 308 SOR_PLL_TMDS_TERMADJ(0), 309 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) | 310 PE_CURRENT1(PE_CURRENT_15_mA_T114) | 311 PE_CURRENT2(PE_CURRENT_15_mA_T114) | 312 PE_CURRENT3(PE_CURRENT_15_mA_T114), 313 .drive_current = 314 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) | 315 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) | 316 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) | 317 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114), 318 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 319 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 320 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 321 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 322 }, { /* 1080p / 148.5MHz modes */ 323 .pclk = 148500000, 324 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 325 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL, 326 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | 327 SOR_PLL_TMDS_TERMADJ(0), 328 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) | 329 PE_CURRENT1(PE_CURRENT_10_mA_T114) | 330 PE_CURRENT2(PE_CURRENT_10_mA_T114) | 331 PE_CURRENT3(PE_CURRENT_10_mA_T114), 332 .drive_current = 333 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) | 334 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) | 335 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) | 336 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114), 337 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) | 338 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) | 339 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) | 340 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA), 341 }, { /* 225/297MHz modes */ 342 .pclk = UINT_MAX, 343 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) | 344 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL, 345 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7) 346 | SOR_PLL_TMDS_TERM_ENABLE, 347 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) | 348 PE_CURRENT1(PE_CURRENT_0_mA_T114) | 349 PE_CURRENT2(PE_CURRENT_0_mA_T114) | 350 PE_CURRENT3(PE_CURRENT_0_mA_T114), 351 .drive_current = 352 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) | 353 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) | 354 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) | 355 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114), 356 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) | 357 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) | 358 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) | 359 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA), 360 }, 361 }; 362 363 static int 364 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pix_clock, 365 struct tegra_hdmi_audio_config *config) 366 { 367 const unsigned int afreq = 128 * audio_freq; 368 const unsigned int min_n = afreq / 1500; 369 const unsigned int max_n = afreq / 300; 370 const unsigned int ideal_n = afreq / 1000; 371 int64_t min_err = (uint64_t)-1 >> 1; 372 unsigned int min_delta = -1; 373 int n; 374 375 memset(config, 0, sizeof(*config)); 376 config->n = -1; 377 378 for (n = min_n; n <= max_n; n++) { 379 uint64_t cts_f, aval_f; 380 unsigned int delta; 381 int64_t cts, err; 382 383 /* compute aval in 48.16 fixed point */ 384 aval_f = ((int64_t)24000000 << 16) * n; 385 do_div(aval_f, afreq); 386 /* It should round without any rest */ 387 if (aval_f & 0xFFFF) 388 continue; 389 390 /* Compute cts in 48.16 fixed point */ 391 cts_f = ((int64_t)pix_clock << 16) * n; 392 do_div(cts_f, afreq); 393 /* Round it to the nearest integer */ 394 cts = (cts_f & ~0xFFFF) + ((cts_f & BIT(15)) << 1); 395 396 delta = abs(n - ideal_n); 397 398 /* Compute the absolute error */ 399 err = abs((int64_t)cts_f - cts); 400 if (err < min_err || (err == min_err && delta < min_delta)) { 401 config->n = n; 402 config->cts = cts >> 16; 403 config->aval = aval_f >> 16; 404 min_delta = delta; 405 min_err = err; 406 } 407 } 408 409 return config->n != -1 ? 0 : -EINVAL; 410 } 411 412 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi) 413 { 414 const unsigned int freqs[] = { 415 32000, 44100, 48000, 88200, 96000, 176400, 192000 416 }; 417 unsigned int i; 418 419 for (i = 0; i < ARRAY_SIZE(freqs); i++) { 420 unsigned int f = freqs[i]; 421 unsigned int eight_half; 422 unsigned int delta; 423 u32 value; 424 425 if (f > 96000) 426 delta = 2; 427 else if (f > 48000) 428 delta = 6; 429 else 430 delta = 9; 431 432 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128); 433 value = AUDIO_FS_LOW(eight_half - delta) | 434 AUDIO_FS_HIGH(eight_half + delta); 435 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i)); 436 } 437 } 438 439 static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value) 440 { 441 static const struct { 442 unsigned int sample_rate; 443 unsigned int offset; 444 } regs[] = { 445 { 32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 }, 446 { 44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 }, 447 { 48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 }, 448 { 88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 }, 449 { 96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 }, 450 { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 }, 451 { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 }, 452 }; 453 unsigned int i; 454 455 for (i = 0; i < ARRAY_SIZE(regs); i++) { 456 if (regs[i].sample_rate == hdmi->format.sample_rate) { 457 tegra_hdmi_writel(hdmi, value, regs[i].offset); 458 break; 459 } 460 } 461 } 462 463 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi) 464 { 465 struct tegra_hdmi_audio_config config; 466 u32 source, value; 467 int err; 468 469 switch (hdmi->audio_source) { 470 case HDA: 471 if (hdmi->config->has_hda) 472 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL; 473 else 474 return -EINVAL; 475 476 break; 477 478 case SPDIF: 479 if (hdmi->config->has_hda) 480 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF; 481 else 482 source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF; 483 break; 484 485 default: 486 if (hdmi->config->has_hda) 487 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO; 488 else 489 source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO; 490 break; 491 } 492 493 /* 494 * Tegra30 and later use a slightly modified version of the register 495 * layout to accomodate for changes related to supporting HDA as the 496 * audio input source for HDMI. The source select field has moved to 497 * the SOR_AUDIO_CNTRL0 register, but the error tolerance and frames 498 * per block fields remain in the AUDIO_CNTRL0 register. 499 */ 500 if (hdmi->config->has_hda) { 501 /* 502 * Inject null samples into the audio FIFO for every frame in 503 * which the codec did not receive any samples. This applies 504 * to stereo LPCM only. 505 * 506 * XXX: This seems to be a remnant of MCP days when this was 507 * used to work around issues with monitors not being able to 508 * play back system startup sounds early. It is possibly not 509 * needed on Linux at all. 510 */ 511 if (hdmi->format.channels == 2) 512 value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL; 513 else 514 value = 0; 515 516 value |= source; 517 518 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0); 519 } 520 521 /* 522 * On Tegra20, HDA is not a supported audio source and the source 523 * select field is part of the AUDIO_CNTRL0 register. 524 */ 525 value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) | 526 AUDIO_CNTRL0_ERROR_TOLERANCE(6); 527 528 if (!hdmi->config->has_hda) 529 value |= source; 530 531 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0); 532 533 /* 534 * Advertise support for High Bit-Rate on Tegra114 and later. 535 */ 536 if (hdmi->config->has_hbr) { 537 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0); 538 value |= SOR_AUDIO_SPARE0_HBR_ENABLE; 539 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0); 540 } 541 542 err = tegra_hdmi_get_audio_config(hdmi->format.sample_rate, 543 hdmi->pixel_clock, &config); 544 if (err < 0) { 545 dev_err(hdmi->dev, 546 "cannot set audio to %u Hz at %u Hz pixel clock\n", 547 hdmi->format.sample_rate, hdmi->pixel_clock); 548 return err; 549 } 550 551 dev_dbg(hdmi->dev, "audio: pixclk=%u, n=%u, cts=%u, aval=%u\n", 552 hdmi->pixel_clock, config.n, config.cts, config.aval); 553 554 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL); 555 556 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE | 557 AUDIO_N_VALUE(config.n - 1); 558 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N); 559 560 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config.n) | ACR_ENABLE, 561 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH); 562 563 tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config.cts), 564 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW); 565 566 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1); 567 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE); 568 569 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N); 570 value &= ~AUDIO_N_RESETF; 571 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N); 572 573 if (hdmi->config->has_hda) 574 tegra_hdmi_write_aval(hdmi, config.aval); 575 576 tegra_hdmi_setup_audio_fs_tables(hdmi); 577 578 return 0; 579 } 580 581 static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi) 582 { 583 u32 value; 584 585 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 586 value &= ~GENERIC_CTRL_AUDIO; 587 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 588 } 589 590 static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi) 591 { 592 u32 value; 593 594 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 595 value |= GENERIC_CTRL_AUDIO; 596 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 597 } 598 599 static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi) 600 { 601 size_t length = drm_eld_size(hdmi->output.connector.eld), i; 602 u32 value; 603 604 for (i = 0; i < length; i++) 605 tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i], 606 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR); 607 608 /* 609 * The HDA codec will always report an ELD buffer size of 96 bytes and 610 * the HDA codec driver will check that each byte read from the buffer 611 * is valid. Therefore every byte must be written, even if no 96 bytes 612 * were parsed from EDID. 613 */ 614 for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++) 615 tegra_hdmi_writel(hdmi, i << 8 | 0, 616 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR); 617 618 value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT; 619 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE); 620 } 621 622 static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size) 623 { 624 u32 value = 0; 625 size_t i; 626 627 for (i = size; i > 0; i--) 628 value = (value << 8) | ptr[i - 1]; 629 630 return value; 631 } 632 633 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data, 634 size_t size) 635 { 636 const u8 *ptr = data; 637 unsigned long offset; 638 size_t i, j; 639 u32 value; 640 641 switch (ptr[0]) { 642 case HDMI_INFOFRAME_TYPE_AVI: 643 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER; 644 break; 645 646 case HDMI_INFOFRAME_TYPE_AUDIO: 647 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER; 648 break; 649 650 case HDMI_INFOFRAME_TYPE_VENDOR: 651 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER; 652 break; 653 654 default: 655 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n", 656 ptr[0]); 657 return; 658 } 659 660 value = INFOFRAME_HEADER_TYPE(ptr[0]) | 661 INFOFRAME_HEADER_VERSION(ptr[1]) | 662 INFOFRAME_HEADER_LEN(ptr[2]); 663 tegra_hdmi_writel(hdmi, value, offset); 664 offset++; 665 666 /* 667 * Each subpack contains 7 bytes, divided into: 668 * - subpack_low: bytes 0 - 3 669 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) 670 */ 671 for (i = 3, j = 0; i < size; i += 7, j += 8) { 672 size_t rem = size - i, num = min_t(size_t, rem, 4); 673 674 value = tegra_hdmi_subpack(&ptr[i], num); 675 tegra_hdmi_writel(hdmi, value, offset++); 676 677 num = min_t(size_t, rem - num, 3); 678 679 value = tegra_hdmi_subpack(&ptr[i + 4], num); 680 tegra_hdmi_writel(hdmi, value, offset++); 681 } 682 } 683 684 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi, 685 struct drm_display_mode *mode) 686 { 687 struct hdmi_avi_infoframe frame; 688 u8 buffer[17]; 689 ssize_t err; 690 691 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, 692 &hdmi->output.connector, mode); 693 if (err < 0) { 694 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err); 695 return; 696 } 697 698 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 699 if (err < 0) { 700 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err); 701 return; 702 } 703 704 tegra_hdmi_write_infopack(hdmi, buffer, err); 705 } 706 707 static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi) 708 { 709 u32 value; 710 711 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); 712 value &= ~INFOFRAME_CTRL_ENABLE; 713 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); 714 } 715 716 static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi) 717 { 718 u32 value; 719 720 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); 721 value |= INFOFRAME_CTRL_ENABLE; 722 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL); 723 } 724 725 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi) 726 { 727 struct hdmi_audio_infoframe frame; 728 u8 buffer[14]; 729 ssize_t err; 730 731 err = hdmi_audio_infoframe_init(&frame); 732 if (err < 0) { 733 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n", 734 err); 735 return; 736 } 737 738 frame.channels = hdmi->format.channels; 739 740 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 741 if (err < 0) { 742 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n", 743 err); 744 return; 745 } 746 747 /* 748 * The audio infoframe has only one set of subpack registers, so the 749 * infoframe needs to be truncated. One set of subpack registers can 750 * contain 7 bytes. Including the 3 byte header only the first 10 751 * bytes can be programmed. 752 */ 753 tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err)); 754 } 755 756 static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi) 757 { 758 u32 value; 759 760 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); 761 value &= ~INFOFRAME_CTRL_ENABLE; 762 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); 763 } 764 765 static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi) 766 { 767 u32 value; 768 769 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); 770 value |= INFOFRAME_CTRL_ENABLE; 771 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL); 772 } 773 774 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi) 775 { 776 struct hdmi_vendor_infoframe frame; 777 u8 buffer[10]; 778 ssize_t err; 779 780 hdmi_vendor_infoframe_init(&frame); 781 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING; 782 783 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 784 if (err < 0) { 785 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n", 786 err); 787 return; 788 } 789 790 tegra_hdmi_write_infopack(hdmi, buffer, err); 791 } 792 793 static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi) 794 { 795 u32 value; 796 797 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 798 value &= ~GENERIC_CTRL_ENABLE; 799 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 800 } 801 802 static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi) 803 { 804 u32 value; 805 806 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 807 value |= GENERIC_CTRL_ENABLE; 808 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL); 809 } 810 811 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi, 812 const struct tmds_config *tmds) 813 { 814 u32 value; 815 816 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0); 817 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); 818 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT); 819 820 tegra_hdmi_writel(hdmi, tmds->drive_current, 821 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT); 822 823 value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset); 824 value |= hdmi->config->fuse_override_value; 825 tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset); 826 827 if (hdmi->config->has_sor_io_peak_current) 828 tegra_hdmi_writel(hdmi, tmds->peak_current, 829 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT); 830 } 831 832 static bool tegra_output_is_hdmi(struct tegra_output *output) 833 { 834 struct edid *edid; 835 836 if (!output->connector.edid_blob_ptr) 837 return false; 838 839 edid = (struct edid *)output->connector.edid_blob_ptr->data; 840 841 return drm_detect_hdmi_monitor(edid); 842 } 843 844 static enum drm_connector_status 845 tegra_hdmi_connector_detect(struct drm_connector *connector, bool force) 846 { 847 struct tegra_output *output = connector_to_output(connector); 848 struct tegra_hdmi *hdmi = to_hdmi(output); 849 enum drm_connector_status status; 850 851 status = tegra_output_connector_detect(connector, force); 852 if (status == connector_status_connected) 853 return status; 854 855 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE); 856 return status; 857 } 858 859 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 860 861 static const struct debugfs_reg32 tegra_hdmi_regs[] = { 862 DEBUGFS_REG32(HDMI_CTXSW), 863 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0), 864 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1), 865 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2), 866 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB), 867 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB), 868 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB), 869 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB), 870 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB), 871 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB), 872 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB), 873 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB), 874 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB), 875 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB), 876 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB), 877 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB), 878 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL), 879 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE), 880 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB), 881 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB), 882 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB), 883 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2), 884 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1), 885 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI), 886 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB), 887 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB), 888 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0), 889 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0), 890 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1), 891 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2), 892 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL), 893 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS), 894 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER), 895 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW), 896 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH), 897 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL), 898 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS), 899 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER), 900 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW), 901 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH), 902 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW), 903 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH), 904 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL), 905 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS), 906 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER), 907 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW), 908 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH), 909 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW), 910 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH), 911 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW), 912 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH), 913 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW), 914 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH), 915 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL), 916 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW), 917 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH), 918 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW), 919 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH), 920 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW), 921 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH), 922 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW), 923 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH), 924 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW), 925 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH), 926 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW), 927 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH), 928 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW), 929 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH), 930 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL), 931 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT), 932 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW), 933 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL), 934 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS), 935 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK), 936 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1), 937 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2), 938 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0), 939 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1), 940 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA), 941 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE), 942 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1), 943 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2), 944 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL), 945 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP), 946 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR), 947 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST), 948 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0), 949 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1), 950 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2), 951 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM), 952 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS), 953 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA), 954 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB), 955 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK), 956 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL), 957 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)), 958 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)), 959 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)), 960 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)), 961 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)), 962 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)), 963 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)), 964 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)), 965 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)), 966 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)), 967 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)), 968 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)), 969 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)), 970 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)), 971 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)), 972 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)), 973 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0), 974 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1), 975 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0), 976 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1), 977 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0), 978 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1), 979 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0), 980 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1), 981 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0), 982 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1), 983 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG), 984 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK), 985 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT), 986 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0), 987 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1), 988 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2), 989 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)), 990 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)), 991 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)), 992 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)), 993 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)), 994 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)), 995 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)), 996 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH), 997 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD), 998 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0), 999 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N), 1000 DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING), 1001 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK), 1002 DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL), 1003 DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL), 1004 DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH), 1005 DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT), 1006 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL), 1007 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0), 1008 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1), 1009 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2), 1010 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0), 1011 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1), 1012 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2), 1013 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3), 1014 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG), 1015 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX), 1016 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0), 1017 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0), 1018 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0), 1019 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1), 1020 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR), 1021 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE), 1022 DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS), 1023 DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK), 1024 DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE), 1025 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT), 1026 }; 1027 1028 static int tegra_hdmi_show_regs(struct seq_file *s, void *data) 1029 { 1030 struct drm_info_node *node = s->private; 1031 struct tegra_hdmi *hdmi = node->info_ent->data; 1032 struct drm_crtc *crtc = hdmi->output.encoder.crtc; 1033 struct drm_device *drm = node->minor->dev; 1034 unsigned int i; 1035 int err = 0; 1036 1037 drm_modeset_lock_all(drm); 1038 1039 if (!crtc || !crtc->state->active) { 1040 err = -EBUSY; 1041 goto unlock; 1042 } 1043 1044 for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) { 1045 unsigned int offset = tegra_hdmi_regs[i].offset; 1046 1047 seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name, 1048 offset, tegra_hdmi_readl(hdmi, offset)); 1049 } 1050 1051 unlock: 1052 drm_modeset_unlock_all(drm); 1053 return err; 1054 } 1055 1056 static struct drm_info_list debugfs_files[] = { 1057 { "regs", tegra_hdmi_show_regs, 0, NULL }, 1058 }; 1059 1060 static int tegra_hdmi_late_register(struct drm_connector *connector) 1061 { 1062 struct tegra_output *output = connector_to_output(connector); 1063 unsigned int i, count = ARRAY_SIZE(debugfs_files); 1064 struct drm_minor *minor = connector->dev->primary; 1065 struct dentry *root = connector->debugfs_entry; 1066 struct tegra_hdmi *hdmi = to_hdmi(output); 1067 1068 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1069 GFP_KERNEL); 1070 if (!hdmi->debugfs_files) 1071 return -ENOMEM; 1072 1073 for (i = 0; i < count; i++) 1074 hdmi->debugfs_files[i].data = hdmi; 1075 1076 drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor); 1077 1078 return 0; 1079 } 1080 1081 static void tegra_hdmi_early_unregister(struct drm_connector *connector) 1082 { 1083 struct tegra_output *output = connector_to_output(connector); 1084 struct drm_minor *minor = connector->dev->primary; 1085 unsigned int count = ARRAY_SIZE(debugfs_files); 1086 struct tegra_hdmi *hdmi = to_hdmi(output); 1087 1088 drm_debugfs_remove_files(hdmi->debugfs_files, count, minor); 1089 kfree(hdmi->debugfs_files); 1090 hdmi->debugfs_files = NULL; 1091 } 1092 1093 static const struct drm_connector_funcs tegra_hdmi_connector_funcs = { 1094 .reset = drm_atomic_helper_connector_reset, 1095 .detect = tegra_hdmi_connector_detect, 1096 .fill_modes = drm_helper_probe_single_connector_modes, 1097 .destroy = tegra_output_connector_destroy, 1098 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1099 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1100 .late_register = tegra_hdmi_late_register, 1101 .early_unregister = tegra_hdmi_early_unregister, 1102 }; 1103 1104 static enum drm_mode_status 1105 tegra_hdmi_connector_mode_valid(struct drm_connector *connector, 1106 struct drm_display_mode *mode) 1107 { 1108 struct tegra_output *output = connector_to_output(connector); 1109 struct tegra_hdmi *hdmi = to_hdmi(output); 1110 unsigned long pclk = mode->clock * 1000; 1111 enum drm_mode_status status = MODE_OK; 1112 struct clk *parent; 1113 long err; 1114 1115 parent = clk_get_parent(hdmi->clk_parent); 1116 1117 err = clk_round_rate(parent, pclk * 4); 1118 if (err <= 0) 1119 status = MODE_NOCLOCK; 1120 1121 return status; 1122 } 1123 1124 static const struct drm_connector_helper_funcs 1125 tegra_hdmi_connector_helper_funcs = { 1126 .get_modes = tegra_output_connector_get_modes, 1127 .mode_valid = tegra_hdmi_connector_mode_valid, 1128 }; 1129 1130 static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder) 1131 { 1132 struct tegra_output *output = encoder_to_output(encoder); 1133 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1134 struct tegra_hdmi *hdmi = to_hdmi(output); 1135 u32 value; 1136 int err; 1137 1138 /* 1139 * The following accesses registers of the display controller, so make 1140 * sure it's only executed when the output is attached to one. 1141 */ 1142 if (dc) { 1143 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1144 value &= ~HDMI_ENABLE; 1145 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1146 1147 tegra_dc_commit(dc); 1148 } 1149 1150 if (!hdmi->dvi) { 1151 if (hdmi->stereo) 1152 tegra_hdmi_disable_stereo_infoframe(hdmi); 1153 1154 tegra_hdmi_disable_audio_infoframe(hdmi); 1155 tegra_hdmi_disable_avi_infoframe(hdmi); 1156 tegra_hdmi_disable_audio(hdmi); 1157 } 1158 1159 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE); 1160 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK); 1161 1162 err = host1x_client_suspend(&hdmi->client); 1163 if (err < 0) 1164 dev_err(hdmi->dev, "failed to suspend: %d\n", err); 1165 } 1166 1167 static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder) 1168 { 1169 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 1170 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey; 1171 struct tegra_output *output = encoder_to_output(encoder); 1172 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 1173 struct tegra_hdmi *hdmi = to_hdmi(output); 1174 unsigned int pulse_start, div82; 1175 int retries = 1000; 1176 u32 value; 1177 int err; 1178 1179 err = host1x_client_resume(&hdmi->client); 1180 if (err < 0) { 1181 dev_err(hdmi->dev, "failed to resume: %d\n", err); 1182 return; 1183 } 1184 1185 /* 1186 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This 1187 * is used for interoperability between the HDA codec driver and the 1188 * HDMI driver. 1189 */ 1190 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE); 1191 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK); 1192 1193 hdmi->pixel_clock = mode->clock * 1000; 1194 h_sync_width = mode->hsync_end - mode->hsync_start; 1195 h_back_porch = mode->htotal - mode->hsync_end; 1196 h_front_porch = mode->hsync_start - mode->hdisplay; 1197 1198 err = clk_set_rate(hdmi->clk, hdmi->pixel_clock); 1199 if (err < 0) { 1200 dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n", 1201 err); 1202 } 1203 1204 DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk)); 1205 1206 /* power up sequence */ 1207 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0); 1208 value &= ~SOR_PLL_PDBG; 1209 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0); 1210 1211 usleep_range(10, 20); 1212 1213 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0); 1214 value &= ~SOR_PLL_PWR; 1215 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0); 1216 1217 tegra_dc_writel(dc, VSYNC_H_POSITION(1), 1218 DC_DISP_DISP_TIMING_OPTIONS); 1219 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888, 1220 DC_DISP_DISP_COLOR_CONTROL); 1221 1222 /* video_preamble uses h_pulse2 */ 1223 pulse_start = 1 + h_sync_width + h_back_porch - 10; 1224 1225 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0); 1226 1227 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE | 1228 PULSE_LAST_END_A; 1229 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); 1230 1231 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8); 1232 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); 1233 1234 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) | 1235 VSYNC_WINDOW_ENABLE; 1236 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW); 1237 1238 if (dc->pipe) 1239 value = HDMI_SRC_DISPLAYB; 1240 else 1241 value = HDMI_SRC_DISPLAYA; 1242 1243 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) || 1244 (mode->vdisplay == 576))) 1245 tegra_hdmi_writel(hdmi, 1246 value | ARM_VIDEO_RANGE_FULL, 1247 HDMI_NV_PDISP_INPUT_CONTROL); 1248 else 1249 tegra_hdmi_writel(hdmi, 1250 value | ARM_VIDEO_RANGE_LIMITED, 1251 HDMI_NV_PDISP_INPUT_CONTROL); 1252 1253 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4; 1254 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82); 1255 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK); 1256 1257 hdmi->dvi = !tegra_output_is_hdmi(output); 1258 if (!hdmi->dvi) { 1259 /* 1260 * Make sure that the audio format has been configured before 1261 * enabling audio, otherwise we may try to divide by zero. 1262 */ 1263 if (hdmi->format.sample_rate > 0) { 1264 err = tegra_hdmi_setup_audio(hdmi); 1265 if (err < 0) 1266 hdmi->dvi = true; 1267 } 1268 } 1269 1270 if (hdmi->config->has_hda) 1271 tegra_hdmi_write_eld(hdmi); 1272 1273 rekey = HDMI_REKEY_DEFAULT; 1274 value = HDMI_CTRL_REKEY(rekey); 1275 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch + 1276 h_front_porch - rekey - 18) / 32); 1277 1278 if (!hdmi->dvi) 1279 value |= HDMI_CTRL_ENABLE; 1280 1281 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL); 1282 1283 if (!hdmi->dvi) { 1284 tegra_hdmi_setup_avi_infoframe(hdmi, mode); 1285 tegra_hdmi_setup_audio_infoframe(hdmi); 1286 1287 if (hdmi->stereo) 1288 tegra_hdmi_setup_stereo_infoframe(hdmi); 1289 } 1290 1291 /* TMDS CONFIG */ 1292 for (i = 0; i < hdmi->config->num_tmds; i++) { 1293 if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) { 1294 tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]); 1295 break; 1296 } 1297 } 1298 1299 tegra_hdmi_writel(hdmi, 1300 SOR_SEQ_PU_PC(0) | 1301 SOR_SEQ_PU_PC_ALT(0) | 1302 SOR_SEQ_PD_PC(8) | 1303 SOR_SEQ_PD_PC_ALT(8), 1304 HDMI_NV_PDISP_SOR_SEQ_CTL); 1305 1306 value = SOR_SEQ_INST_WAIT_TIME(1) | 1307 SOR_SEQ_INST_WAIT_UNITS_VSYNC | 1308 SOR_SEQ_INST_HALT | 1309 SOR_SEQ_INST_PIN_A_LOW | 1310 SOR_SEQ_INST_PIN_B_LOW | 1311 SOR_SEQ_INST_DRIVE_PWM_OUT_LO; 1312 1313 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0)); 1314 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8)); 1315 1316 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM); 1317 value &= ~SOR_CSTM_ROTCLK(~0); 1318 value |= SOR_CSTM_ROTCLK(2); 1319 value |= SOR_CSTM_PLLDIV; 1320 value &= ~SOR_CSTM_LVDS_ENABLE; 1321 value &= ~SOR_CSTM_MODE_MASK; 1322 value |= SOR_CSTM_MODE_TMDS; 1323 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM); 1324 1325 /* start SOR */ 1326 tegra_hdmi_writel(hdmi, 1327 SOR_PWR_NORMAL_STATE_PU | 1328 SOR_PWR_NORMAL_START_NORMAL | 1329 SOR_PWR_SAFE_STATE_PD | 1330 SOR_PWR_SETTING_NEW_TRIGGER, 1331 HDMI_NV_PDISP_SOR_PWR); 1332 tegra_hdmi_writel(hdmi, 1333 SOR_PWR_NORMAL_STATE_PU | 1334 SOR_PWR_NORMAL_START_NORMAL | 1335 SOR_PWR_SAFE_STATE_PD | 1336 SOR_PWR_SETTING_NEW_DONE, 1337 HDMI_NV_PDISP_SOR_PWR); 1338 1339 do { 1340 BUG_ON(--retries < 0); 1341 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR); 1342 } while (value & SOR_PWR_SETTING_NEW_PENDING); 1343 1344 value = SOR_STATE_ASY_CRCMODE_COMPLETE | 1345 SOR_STATE_ASY_OWNER_HEAD0 | 1346 SOR_STATE_ASY_SUBOWNER_BOTH | 1347 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A | 1348 SOR_STATE_ASY_DEPOL_POS; 1349 1350 /* setup sync polarities */ 1351 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1352 value |= SOR_STATE_ASY_HSYNCPOL_POS; 1353 1354 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1355 value |= SOR_STATE_ASY_HSYNCPOL_NEG; 1356 1357 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1358 value |= SOR_STATE_ASY_VSYNCPOL_POS; 1359 1360 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1361 value |= SOR_STATE_ASY_VSYNCPOL_NEG; 1362 1363 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2); 1364 1365 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL; 1366 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1); 1367 1368 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0); 1369 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0); 1370 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED, 1371 HDMI_NV_PDISP_SOR_STATE1); 1372 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0); 1373 1374 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1375 value |= HDMI_ENABLE; 1376 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1377 1378 tegra_dc_commit(dc); 1379 1380 if (!hdmi->dvi) { 1381 tegra_hdmi_enable_avi_infoframe(hdmi); 1382 tegra_hdmi_enable_audio_infoframe(hdmi); 1383 tegra_hdmi_enable_audio(hdmi); 1384 1385 if (hdmi->stereo) 1386 tegra_hdmi_enable_stereo_infoframe(hdmi); 1387 } 1388 1389 /* TODO: add HDCP support */ 1390 } 1391 1392 static int 1393 tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1394 struct drm_crtc_state *crtc_state, 1395 struct drm_connector_state *conn_state) 1396 { 1397 struct tegra_output *output = encoder_to_output(encoder); 1398 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 1399 unsigned long pclk = crtc_state->mode.clock * 1000; 1400 struct tegra_hdmi *hdmi = to_hdmi(output); 1401 int err; 1402 1403 err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent, 1404 pclk, 0); 1405 if (err < 0) { 1406 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 1407 return err; 1408 } 1409 1410 return err; 1411 } 1412 1413 static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = { 1414 .disable = tegra_hdmi_encoder_disable, 1415 .enable = tegra_hdmi_encoder_enable, 1416 .atomic_check = tegra_hdmi_encoder_atomic_check, 1417 }; 1418 1419 static int tegra_hdmi_init(struct host1x_client *client) 1420 { 1421 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); 1422 struct drm_device *drm = dev_get_drvdata(client->host); 1423 int err; 1424 1425 hdmi->output.dev = client->dev; 1426 1427 drm_connector_init_with_ddc(drm, &hdmi->output.connector, 1428 &tegra_hdmi_connector_funcs, 1429 DRM_MODE_CONNECTOR_HDMIA, 1430 hdmi->output.ddc); 1431 drm_connector_helper_add(&hdmi->output.connector, 1432 &tegra_hdmi_connector_helper_funcs); 1433 hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF; 1434 1435 drm_simple_encoder_init(drm, &hdmi->output.encoder, 1436 DRM_MODE_ENCODER_TMDS); 1437 drm_encoder_helper_add(&hdmi->output.encoder, 1438 &tegra_hdmi_encoder_helper_funcs); 1439 1440 drm_connector_attach_encoder(&hdmi->output.connector, 1441 &hdmi->output.encoder); 1442 drm_connector_register(&hdmi->output.connector); 1443 1444 err = tegra_output_init(drm, &hdmi->output); 1445 if (err < 0) { 1446 dev_err(client->dev, "failed to initialize output: %d\n", err); 1447 return err; 1448 } 1449 1450 hdmi->output.encoder.possible_crtcs = 0x3; 1451 1452 err = regulator_enable(hdmi->hdmi); 1453 if (err < 0) { 1454 dev_err(client->dev, "failed to enable HDMI regulator: %d\n", 1455 err); 1456 return err; 1457 } 1458 1459 err = regulator_enable(hdmi->pll); 1460 if (err < 0) { 1461 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err); 1462 return err; 1463 } 1464 1465 err = regulator_enable(hdmi->vdd); 1466 if (err < 0) { 1467 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err); 1468 return err; 1469 } 1470 1471 return 0; 1472 } 1473 1474 static int tegra_hdmi_exit(struct host1x_client *client) 1475 { 1476 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); 1477 1478 tegra_output_exit(&hdmi->output); 1479 1480 regulator_disable(hdmi->vdd); 1481 regulator_disable(hdmi->pll); 1482 regulator_disable(hdmi->hdmi); 1483 1484 return 0; 1485 } 1486 1487 static int tegra_hdmi_runtime_suspend(struct host1x_client *client) 1488 { 1489 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); 1490 struct device *dev = client->dev; 1491 int err; 1492 1493 err = reset_control_assert(hdmi->rst); 1494 if (err < 0) { 1495 dev_err(dev, "failed to assert reset: %d\n", err); 1496 return err; 1497 } 1498 1499 usleep_range(1000, 2000); 1500 1501 clk_disable_unprepare(hdmi->clk); 1502 pm_runtime_put_sync(dev); 1503 1504 return 0; 1505 } 1506 1507 static int tegra_hdmi_runtime_resume(struct host1x_client *client) 1508 { 1509 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); 1510 struct device *dev = client->dev; 1511 int err; 1512 1513 err = pm_runtime_resume_and_get(dev); 1514 if (err < 0) { 1515 dev_err(dev, "failed to get runtime PM: %d\n", err); 1516 return err; 1517 } 1518 1519 err = clk_prepare_enable(hdmi->clk); 1520 if (err < 0) { 1521 dev_err(dev, "failed to enable clock: %d\n", err); 1522 goto put_rpm; 1523 } 1524 1525 usleep_range(1000, 2000); 1526 1527 err = reset_control_deassert(hdmi->rst); 1528 if (err < 0) { 1529 dev_err(dev, "failed to deassert reset: %d\n", err); 1530 goto disable_clk; 1531 } 1532 1533 return 0; 1534 1535 disable_clk: 1536 clk_disable_unprepare(hdmi->clk); 1537 put_rpm: 1538 pm_runtime_put_sync(dev); 1539 return err; 1540 } 1541 1542 static const struct host1x_client_ops hdmi_client_ops = { 1543 .init = tegra_hdmi_init, 1544 .exit = tegra_hdmi_exit, 1545 .suspend = tegra_hdmi_runtime_suspend, 1546 .resume = tegra_hdmi_runtime_resume, 1547 }; 1548 1549 static const struct tegra_hdmi_config tegra20_hdmi_config = { 1550 .tmds = tegra20_tmds_config, 1551 .num_tmds = ARRAY_SIZE(tegra20_tmds_config), 1552 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT, 1553 .fuse_override_value = 1 << 31, 1554 .has_sor_io_peak_current = false, 1555 .has_hda = false, 1556 .has_hbr = false, 1557 }; 1558 1559 static const struct tegra_hdmi_config tegra30_hdmi_config = { 1560 .tmds = tegra30_tmds_config, 1561 .num_tmds = ARRAY_SIZE(tegra30_tmds_config), 1562 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT, 1563 .fuse_override_value = 1 << 31, 1564 .has_sor_io_peak_current = false, 1565 .has_hda = true, 1566 .has_hbr = false, 1567 }; 1568 1569 static const struct tegra_hdmi_config tegra114_hdmi_config = { 1570 .tmds = tegra114_tmds_config, 1571 .num_tmds = ARRAY_SIZE(tegra114_tmds_config), 1572 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0, 1573 .fuse_override_value = 1 << 31, 1574 .has_sor_io_peak_current = true, 1575 .has_hda = true, 1576 .has_hbr = true, 1577 }; 1578 1579 static const struct tegra_hdmi_config tegra124_hdmi_config = { 1580 .tmds = tegra124_tmds_config, 1581 .num_tmds = ARRAY_SIZE(tegra124_tmds_config), 1582 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0, 1583 .fuse_override_value = 1 << 31, 1584 .has_sor_io_peak_current = true, 1585 .has_hda = true, 1586 .has_hbr = true, 1587 }; 1588 1589 static const struct of_device_id tegra_hdmi_of_match[] = { 1590 { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config }, 1591 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config }, 1592 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config }, 1593 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config }, 1594 { }, 1595 }; 1596 MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match); 1597 1598 static irqreturn_t tegra_hdmi_irq(int irq, void *data) 1599 { 1600 struct tegra_hdmi *hdmi = data; 1601 u32 value; 1602 int err; 1603 1604 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS); 1605 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS); 1606 1607 if (value & INT_CODEC_SCRATCH0) { 1608 unsigned int format; 1609 u32 value; 1610 1611 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0); 1612 1613 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) { 1614 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK; 1615 1616 tegra_hda_parse_format(format, &hdmi->format); 1617 1618 err = tegra_hdmi_setup_audio(hdmi); 1619 if (err < 0) { 1620 tegra_hdmi_disable_audio_infoframe(hdmi); 1621 tegra_hdmi_disable_audio(hdmi); 1622 } else { 1623 tegra_hdmi_setup_audio_infoframe(hdmi); 1624 tegra_hdmi_enable_audio_infoframe(hdmi); 1625 tegra_hdmi_enable_audio(hdmi); 1626 } 1627 } else { 1628 tegra_hdmi_disable_audio_infoframe(hdmi); 1629 tegra_hdmi_disable_audio(hdmi); 1630 } 1631 } 1632 1633 return IRQ_HANDLED; 1634 } 1635 1636 static int tegra_hdmi_probe(struct platform_device *pdev) 1637 { 1638 const char *level = KERN_ERR; 1639 struct tegra_hdmi *hdmi; 1640 struct resource *regs; 1641 int err; 1642 1643 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); 1644 if (!hdmi) 1645 return -ENOMEM; 1646 1647 hdmi->config = of_device_get_match_data(&pdev->dev); 1648 hdmi->dev = &pdev->dev; 1649 1650 hdmi->audio_source = AUTO; 1651 hdmi->stereo = false; 1652 hdmi->dvi = false; 1653 1654 hdmi->clk = devm_clk_get(&pdev->dev, NULL); 1655 if (IS_ERR(hdmi->clk)) { 1656 dev_err(&pdev->dev, "failed to get clock\n"); 1657 return PTR_ERR(hdmi->clk); 1658 } 1659 1660 hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi"); 1661 if (IS_ERR(hdmi->rst)) { 1662 dev_err(&pdev->dev, "failed to get reset\n"); 1663 return PTR_ERR(hdmi->rst); 1664 } 1665 1666 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent"); 1667 if (IS_ERR(hdmi->clk_parent)) 1668 return PTR_ERR(hdmi->clk_parent); 1669 1670 err = clk_set_parent(hdmi->clk, hdmi->clk_parent); 1671 if (err < 0) { 1672 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err); 1673 return err; 1674 } 1675 1676 hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi"); 1677 err = PTR_ERR_OR_ZERO(hdmi->hdmi); 1678 if (err) { 1679 if (err == -EPROBE_DEFER) 1680 level = KERN_DEBUG; 1681 1682 dev_printk(level, &pdev->dev, 1683 "failed to get HDMI regulator: %d\n", err); 1684 return err; 1685 } 1686 1687 hdmi->pll = devm_regulator_get(&pdev->dev, "pll"); 1688 err = PTR_ERR_OR_ZERO(hdmi->pll); 1689 if (err) { 1690 if (err == -EPROBE_DEFER) 1691 level = KERN_DEBUG; 1692 1693 dev_printk(level, &pdev->dev, 1694 "failed to get PLL regulator: %d\n", err); 1695 return err; 1696 } 1697 1698 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd"); 1699 err = PTR_ERR_OR_ZERO(hdmi->vdd); 1700 if (err) { 1701 if (err == -EPROBE_DEFER) 1702 level = KERN_DEBUG; 1703 1704 dev_printk(level, &pdev->dev, 1705 "failed to get VDD regulator: %d\n", err); 1706 return err; 1707 } 1708 1709 hdmi->output.dev = &pdev->dev; 1710 1711 err = tegra_output_probe(&hdmi->output); 1712 if (err < 0) 1713 return err; 1714 1715 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1716 hdmi->regs = devm_ioremap_resource(&pdev->dev, regs); 1717 if (IS_ERR(hdmi->regs)) 1718 return PTR_ERR(hdmi->regs); 1719 1720 err = platform_get_irq(pdev, 0); 1721 if (err < 0) 1722 return err; 1723 1724 hdmi->irq = err; 1725 1726 err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0, 1727 dev_name(hdmi->dev), hdmi); 1728 if (err < 0) { 1729 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", 1730 hdmi->irq, err); 1731 return err; 1732 } 1733 1734 platform_set_drvdata(pdev, hdmi); 1735 pm_runtime_enable(&pdev->dev); 1736 1737 INIT_LIST_HEAD(&hdmi->client.list); 1738 hdmi->client.ops = &hdmi_client_ops; 1739 hdmi->client.dev = &pdev->dev; 1740 1741 err = host1x_client_register(&hdmi->client); 1742 if (err < 0) { 1743 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 1744 err); 1745 return err; 1746 } 1747 1748 return 0; 1749 } 1750 1751 static int tegra_hdmi_remove(struct platform_device *pdev) 1752 { 1753 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev); 1754 int err; 1755 1756 pm_runtime_disable(&pdev->dev); 1757 1758 err = host1x_client_unregister(&hdmi->client); 1759 if (err < 0) { 1760 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 1761 err); 1762 return err; 1763 } 1764 1765 tegra_output_remove(&hdmi->output); 1766 1767 return 0; 1768 } 1769 1770 struct platform_driver tegra_hdmi_driver = { 1771 .driver = { 1772 .name = "tegra-hdmi", 1773 .of_match_table = tegra_hdmi_of_match, 1774 }, 1775 .probe = tegra_hdmi_probe, 1776 .remove = tegra_hdmi_remove, 1777 }; 1778