1 /* 2 * Copyright (C) 2013 Avionic Design GmbH 3 * Copyright (C) 2013 NVIDIA Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/host1x.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/reset.h> 15 #include <linux/tegra-powergate.h> 16 17 #include "drm.h" 18 #include "gem.h" 19 #include "gr3d.h" 20 21 struct gr3d { 22 struct tegra_drm_client client; 23 struct host1x_channel *channel; 24 struct clk *clk_secondary; 25 struct clk *clk; 26 struct reset_control *rst_secondary; 27 struct reset_control *rst; 28 29 DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS); 30 }; 31 32 static inline struct gr3d *to_gr3d(struct tegra_drm_client *client) 33 { 34 return container_of(client, struct gr3d, client); 35 } 36 37 static int gr3d_init(struct host1x_client *client) 38 { 39 struct tegra_drm_client *drm = host1x_to_drm_client(client); 40 struct drm_device *dev = dev_get_drvdata(client->parent); 41 unsigned long flags = HOST1X_SYNCPT_HAS_BASE; 42 struct gr3d *gr3d = to_gr3d(drm); 43 44 gr3d->channel = host1x_channel_request(client->dev); 45 if (!gr3d->channel) 46 return -ENOMEM; 47 48 client->syncpts[0] = host1x_syncpt_request(client->dev, flags); 49 if (!client->syncpts[0]) { 50 host1x_channel_free(gr3d->channel); 51 return -ENOMEM; 52 } 53 54 return tegra_drm_register_client(dev->dev_private, drm); 55 } 56 57 static int gr3d_exit(struct host1x_client *client) 58 { 59 struct tegra_drm_client *drm = host1x_to_drm_client(client); 60 struct drm_device *dev = dev_get_drvdata(client->parent); 61 struct gr3d *gr3d = to_gr3d(drm); 62 int err; 63 64 err = tegra_drm_unregister_client(dev->dev_private, drm); 65 if (err < 0) 66 return err; 67 68 host1x_syncpt_free(client->syncpts[0]); 69 host1x_channel_free(gr3d->channel); 70 71 return 0; 72 } 73 74 static const struct host1x_client_ops gr3d_client_ops = { 75 .init = gr3d_init, 76 .exit = gr3d_exit, 77 }; 78 79 static int gr3d_open_channel(struct tegra_drm_client *client, 80 struct tegra_drm_context *context) 81 { 82 struct gr3d *gr3d = to_gr3d(client); 83 84 context->channel = host1x_channel_get(gr3d->channel); 85 if (!context->channel) 86 return -ENOMEM; 87 88 return 0; 89 } 90 91 static void gr3d_close_channel(struct tegra_drm_context *context) 92 { 93 host1x_channel_put(context->channel); 94 } 95 96 static int gr3d_is_addr_reg(struct device *dev, u32 class, u32 offset) 97 { 98 struct gr3d *gr3d = dev_get_drvdata(dev); 99 100 switch (class) { 101 case HOST1X_CLASS_HOST1X: 102 if (offset == 0x2b) 103 return 1; 104 105 break; 106 107 case HOST1X_CLASS_GR3D: 108 if (offset >= GR3D_NUM_REGS) 109 break; 110 111 if (test_bit(offset, gr3d->addr_regs)) 112 return 1; 113 114 break; 115 } 116 117 return 0; 118 } 119 120 static const struct tegra_drm_client_ops gr3d_ops = { 121 .open_channel = gr3d_open_channel, 122 .close_channel = gr3d_close_channel, 123 .is_addr_reg = gr3d_is_addr_reg, 124 .submit = tegra_drm_submit, 125 }; 126 127 static const struct of_device_id tegra_gr3d_match[] = { 128 { .compatible = "nvidia,tegra114-gr3d" }, 129 { .compatible = "nvidia,tegra30-gr3d" }, 130 { .compatible = "nvidia,tegra20-gr3d" }, 131 { } 132 }; 133 MODULE_DEVICE_TABLE(of, tegra_gr3d_match); 134 135 static const u32 gr3d_addr_regs[] = { 136 GR3D_IDX_ATTRIBUTE( 0), 137 GR3D_IDX_ATTRIBUTE( 1), 138 GR3D_IDX_ATTRIBUTE( 2), 139 GR3D_IDX_ATTRIBUTE( 3), 140 GR3D_IDX_ATTRIBUTE( 4), 141 GR3D_IDX_ATTRIBUTE( 5), 142 GR3D_IDX_ATTRIBUTE( 6), 143 GR3D_IDX_ATTRIBUTE( 7), 144 GR3D_IDX_ATTRIBUTE( 8), 145 GR3D_IDX_ATTRIBUTE( 9), 146 GR3D_IDX_ATTRIBUTE(10), 147 GR3D_IDX_ATTRIBUTE(11), 148 GR3D_IDX_ATTRIBUTE(12), 149 GR3D_IDX_ATTRIBUTE(13), 150 GR3D_IDX_ATTRIBUTE(14), 151 GR3D_IDX_ATTRIBUTE(15), 152 GR3D_IDX_INDEX_BASE, 153 GR3D_QR_ZTAG_ADDR, 154 GR3D_QR_CTAG_ADDR, 155 GR3D_QR_CZ_ADDR, 156 GR3D_TEX_TEX_ADDR( 0), 157 GR3D_TEX_TEX_ADDR( 1), 158 GR3D_TEX_TEX_ADDR( 2), 159 GR3D_TEX_TEX_ADDR( 3), 160 GR3D_TEX_TEX_ADDR( 4), 161 GR3D_TEX_TEX_ADDR( 5), 162 GR3D_TEX_TEX_ADDR( 6), 163 GR3D_TEX_TEX_ADDR( 7), 164 GR3D_TEX_TEX_ADDR( 8), 165 GR3D_TEX_TEX_ADDR( 9), 166 GR3D_TEX_TEX_ADDR(10), 167 GR3D_TEX_TEX_ADDR(11), 168 GR3D_TEX_TEX_ADDR(12), 169 GR3D_TEX_TEX_ADDR(13), 170 GR3D_TEX_TEX_ADDR(14), 171 GR3D_TEX_TEX_ADDR(15), 172 GR3D_DW_MEMORY_OUTPUT_ADDRESS, 173 GR3D_GLOBAL_SURFADDR( 0), 174 GR3D_GLOBAL_SURFADDR( 1), 175 GR3D_GLOBAL_SURFADDR( 2), 176 GR3D_GLOBAL_SURFADDR( 3), 177 GR3D_GLOBAL_SURFADDR( 4), 178 GR3D_GLOBAL_SURFADDR( 5), 179 GR3D_GLOBAL_SURFADDR( 6), 180 GR3D_GLOBAL_SURFADDR( 7), 181 GR3D_GLOBAL_SURFADDR( 8), 182 GR3D_GLOBAL_SURFADDR( 9), 183 GR3D_GLOBAL_SURFADDR(10), 184 GR3D_GLOBAL_SURFADDR(11), 185 GR3D_GLOBAL_SURFADDR(12), 186 GR3D_GLOBAL_SURFADDR(13), 187 GR3D_GLOBAL_SURFADDR(14), 188 GR3D_GLOBAL_SURFADDR(15), 189 GR3D_GLOBAL_SPILLSURFADDR, 190 GR3D_GLOBAL_SURFOVERADDR( 0), 191 GR3D_GLOBAL_SURFOVERADDR( 1), 192 GR3D_GLOBAL_SURFOVERADDR( 2), 193 GR3D_GLOBAL_SURFOVERADDR( 3), 194 GR3D_GLOBAL_SURFOVERADDR( 4), 195 GR3D_GLOBAL_SURFOVERADDR( 5), 196 GR3D_GLOBAL_SURFOVERADDR( 6), 197 GR3D_GLOBAL_SURFOVERADDR( 7), 198 GR3D_GLOBAL_SURFOVERADDR( 8), 199 GR3D_GLOBAL_SURFOVERADDR( 9), 200 GR3D_GLOBAL_SURFOVERADDR(10), 201 GR3D_GLOBAL_SURFOVERADDR(11), 202 GR3D_GLOBAL_SURFOVERADDR(12), 203 GR3D_GLOBAL_SURFOVERADDR(13), 204 GR3D_GLOBAL_SURFOVERADDR(14), 205 GR3D_GLOBAL_SURFOVERADDR(15), 206 GR3D_GLOBAL_SAMP01SURFADDR( 0), 207 GR3D_GLOBAL_SAMP01SURFADDR( 1), 208 GR3D_GLOBAL_SAMP01SURFADDR( 2), 209 GR3D_GLOBAL_SAMP01SURFADDR( 3), 210 GR3D_GLOBAL_SAMP01SURFADDR( 4), 211 GR3D_GLOBAL_SAMP01SURFADDR( 5), 212 GR3D_GLOBAL_SAMP01SURFADDR( 6), 213 GR3D_GLOBAL_SAMP01SURFADDR( 7), 214 GR3D_GLOBAL_SAMP01SURFADDR( 8), 215 GR3D_GLOBAL_SAMP01SURFADDR( 9), 216 GR3D_GLOBAL_SAMP01SURFADDR(10), 217 GR3D_GLOBAL_SAMP01SURFADDR(11), 218 GR3D_GLOBAL_SAMP01SURFADDR(12), 219 GR3D_GLOBAL_SAMP01SURFADDR(13), 220 GR3D_GLOBAL_SAMP01SURFADDR(14), 221 GR3D_GLOBAL_SAMP01SURFADDR(15), 222 GR3D_GLOBAL_SAMP23SURFADDR( 0), 223 GR3D_GLOBAL_SAMP23SURFADDR( 1), 224 GR3D_GLOBAL_SAMP23SURFADDR( 2), 225 GR3D_GLOBAL_SAMP23SURFADDR( 3), 226 GR3D_GLOBAL_SAMP23SURFADDR( 4), 227 GR3D_GLOBAL_SAMP23SURFADDR( 5), 228 GR3D_GLOBAL_SAMP23SURFADDR( 6), 229 GR3D_GLOBAL_SAMP23SURFADDR( 7), 230 GR3D_GLOBAL_SAMP23SURFADDR( 8), 231 GR3D_GLOBAL_SAMP23SURFADDR( 9), 232 GR3D_GLOBAL_SAMP23SURFADDR(10), 233 GR3D_GLOBAL_SAMP23SURFADDR(11), 234 GR3D_GLOBAL_SAMP23SURFADDR(12), 235 GR3D_GLOBAL_SAMP23SURFADDR(13), 236 GR3D_GLOBAL_SAMP23SURFADDR(14), 237 GR3D_GLOBAL_SAMP23SURFADDR(15), 238 }; 239 240 static int gr3d_probe(struct platform_device *pdev) 241 { 242 struct device_node *np = pdev->dev.of_node; 243 struct host1x_syncpt **syncpts; 244 struct gr3d *gr3d; 245 unsigned int i; 246 int err; 247 248 gr3d = devm_kzalloc(&pdev->dev, sizeof(*gr3d), GFP_KERNEL); 249 if (!gr3d) 250 return -ENOMEM; 251 252 syncpts = devm_kzalloc(&pdev->dev, sizeof(*syncpts), GFP_KERNEL); 253 if (!syncpts) 254 return -ENOMEM; 255 256 gr3d->clk = devm_clk_get(&pdev->dev, NULL); 257 if (IS_ERR(gr3d->clk)) { 258 dev_err(&pdev->dev, "cannot get clock\n"); 259 return PTR_ERR(gr3d->clk); 260 } 261 262 gr3d->rst = devm_reset_control_get(&pdev->dev, "3d"); 263 if (IS_ERR(gr3d->rst)) { 264 dev_err(&pdev->dev, "cannot get reset\n"); 265 return PTR_ERR(gr3d->rst); 266 } 267 268 if (of_device_is_compatible(np, "nvidia,tegra30-gr3d")) { 269 gr3d->clk_secondary = devm_clk_get(&pdev->dev, "3d2"); 270 if (IS_ERR(gr3d->clk)) { 271 dev_err(&pdev->dev, "cannot get secondary clock\n"); 272 return PTR_ERR(gr3d->clk); 273 } 274 275 gr3d->rst_secondary = devm_reset_control_get(&pdev->dev, 276 "3d2"); 277 if (IS_ERR(gr3d->rst_secondary)) { 278 dev_err(&pdev->dev, "cannot get secondary reset\n"); 279 return PTR_ERR(gr3d->rst_secondary); 280 } 281 } 282 283 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk, 284 gr3d->rst); 285 if (err < 0) { 286 dev_err(&pdev->dev, "failed to power up 3D unit\n"); 287 return err; 288 } 289 290 if (gr3d->clk_secondary) { 291 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D1, 292 gr3d->clk_secondary, 293 gr3d->rst_secondary); 294 if (err < 0) { 295 dev_err(&pdev->dev, 296 "failed to power up secondary 3D unit\n"); 297 return err; 298 } 299 } 300 301 INIT_LIST_HEAD(&gr3d->client.base.list); 302 gr3d->client.base.ops = &gr3d_client_ops; 303 gr3d->client.base.dev = &pdev->dev; 304 gr3d->client.base.class = HOST1X_CLASS_GR3D; 305 gr3d->client.base.syncpts = syncpts; 306 gr3d->client.base.num_syncpts = 1; 307 308 INIT_LIST_HEAD(&gr3d->client.list); 309 gr3d->client.ops = &gr3d_ops; 310 311 err = host1x_client_register(&gr3d->client.base); 312 if (err < 0) { 313 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 314 err); 315 return err; 316 } 317 318 /* initialize address register map */ 319 for (i = 0; i < ARRAY_SIZE(gr3d_addr_regs); i++) 320 set_bit(gr3d_addr_regs[i], gr3d->addr_regs); 321 322 platform_set_drvdata(pdev, gr3d); 323 324 return 0; 325 } 326 327 static int gr3d_remove(struct platform_device *pdev) 328 { 329 struct gr3d *gr3d = platform_get_drvdata(pdev); 330 int err; 331 332 err = host1x_client_unregister(&gr3d->client.base); 333 if (err < 0) { 334 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 335 err); 336 return err; 337 } 338 339 if (gr3d->clk_secondary) { 340 tegra_powergate_power_off(TEGRA_POWERGATE_3D1); 341 clk_disable_unprepare(gr3d->clk_secondary); 342 } 343 344 tegra_powergate_power_off(TEGRA_POWERGATE_3D); 345 clk_disable_unprepare(gr3d->clk); 346 347 return 0; 348 } 349 350 struct platform_driver tegra_gr3d_driver = { 351 .driver = { 352 .name = "tegra-gr3d", 353 .of_match_table = tegra_gr3d_match, 354 }, 355 .probe = gr3d_probe, 356 .remove = gr3d_remove, 357 }; 358