1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 25f60ed0dSThierry Reding /* 35f60ed0dSThierry Reding * Copyright (C) 2013 Avionic Design GmbH 45f60ed0dSThierry Reding * Copyright (C) 2013 NVIDIA Corporation 55f60ed0dSThierry Reding */ 65f60ed0dSThierry Reding 75f60ed0dSThierry Reding #include <linux/clk.h> 82421b20dSDmitry Osipenko #include <linux/delay.h> 95f60ed0dSThierry Reding #include <linux/host1x.h> 10c9ac5217SDmitry Osipenko #include <linux/iommu.h> 115f60ed0dSThierry Reding #include <linux/module.h> 12*722d4f06SRob Herring #include <linux/of.h> 135f60ed0dSThierry Reding #include <linux/platform_device.h> 142421b20dSDmitry Osipenko #include <linux/pm_domain.h> 152421b20dSDmitry Osipenko #include <linux/pm_opp.h> 162421b20dSDmitry Osipenko #include <linux/pm_runtime.h> 17ca48080aSStephen Warren #include <linux/reset.h> 18306a7f91SThierry Reding 192421b20dSDmitry Osipenko #include <soc/tegra/common.h> 207232398aSThierry Reding #include <soc/tegra/pmc.h> 215f60ed0dSThierry Reding 225f60ed0dSThierry Reding #include "drm.h" 235f60ed0dSThierry Reding #include "gem.h" 245f60ed0dSThierry Reding #include "gr3d.h" 255f60ed0dSThierry Reding 262421b20dSDmitry Osipenko enum { 272421b20dSDmitry Osipenko RST_MC, 282421b20dSDmitry Osipenko RST_GR3D, 292421b20dSDmitry Osipenko RST_MC2, 302421b20dSDmitry Osipenko RST_GR3D2, 312421b20dSDmitry Osipenko RST_GR3D_MAX, 322421b20dSDmitry Osipenko }; 332421b20dSDmitry Osipenko 3433f150eaSThierry Reding struct gr3d_soc { 3533f150eaSThierry Reding unsigned int version; 362421b20dSDmitry Osipenko unsigned int num_clocks; 372421b20dSDmitry Osipenko unsigned int num_resets; 3833f150eaSThierry Reding }; 3933f150eaSThierry Reding 405f60ed0dSThierry Reding struct gr3d { 415f60ed0dSThierry Reding struct tegra_drm_client client; 425f60ed0dSThierry Reding struct host1x_channel *channel; 435f60ed0dSThierry Reding 4433f150eaSThierry Reding const struct gr3d_soc *soc; 452421b20dSDmitry Osipenko struct clk_bulk_data *clocks; 462421b20dSDmitry Osipenko unsigned int nclocks; 472421b20dSDmitry Osipenko struct reset_control_bulk_data resets[RST_GR3D_MAX]; 482421b20dSDmitry Osipenko unsigned int nresets; 4933f150eaSThierry Reding 505f60ed0dSThierry Reding DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS); 515f60ed0dSThierry Reding }; 525f60ed0dSThierry Reding 535f60ed0dSThierry Reding static inline struct gr3d *to_gr3d(struct tegra_drm_client *client) 545f60ed0dSThierry Reding { 555f60ed0dSThierry Reding return container_of(client, struct gr3d, client); 565f60ed0dSThierry Reding } 575f60ed0dSThierry Reding 585f60ed0dSThierry Reding static int gr3d_init(struct host1x_client *client) 595f60ed0dSThierry Reding { 605f60ed0dSThierry Reding struct tegra_drm_client *drm = host1x_to_drm_client(client); 61608f43adSThierry Reding struct drm_device *dev = dev_get_drvdata(client->host); 62977386a0SThierry Reding unsigned long flags = HOST1X_SYNCPT_HAS_BASE; 635f60ed0dSThierry Reding struct gr3d *gr3d = to_gr3d(drm); 64c9ac5217SDmitry Osipenko int err; 655f60ed0dSThierry Reding 66caccddcfSThierry Reding gr3d->channel = host1x_channel_request(client); 675f60ed0dSThierry Reding if (!gr3d->channel) 685f60ed0dSThierry Reding return -ENOMEM; 695f60ed0dSThierry Reding 70617dd7ccSThierry Reding client->syncpts[0] = host1x_syncpt_request(client, flags); 715f60ed0dSThierry Reding if (!client->syncpts[0]) { 72230630bdSThierry Reding err = -ENOMEM; 73230630bdSThierry Reding dev_err(client->dev, "failed to request syncpoint: %d\n", err); 74230630bdSThierry Reding goto put; 755f60ed0dSThierry Reding } 765f60ed0dSThierry Reding 777edd7961SThierry Reding err = host1x_client_iommu_attach(client); 78aacdf198SThierry Reding if (err < 0) { 790c407de5SThierry Reding dev_err(client->dev, "failed to attach to domain: %d\n", err); 80230630bdSThierry Reding goto free; 81c9ac5217SDmitry Osipenko } 82c9ac5217SDmitry Osipenko 832421b20dSDmitry Osipenko pm_runtime_enable(client->dev); 842421b20dSDmitry Osipenko pm_runtime_use_autosuspend(client->dev); 852421b20dSDmitry Osipenko pm_runtime_set_autosuspend_delay(client->dev, 200); 862421b20dSDmitry Osipenko 87230630bdSThierry Reding err = tegra_drm_register_client(dev->dev_private, drm); 88230630bdSThierry Reding if (err < 0) { 89230630bdSThierry Reding dev_err(client->dev, "failed to register client: %d\n", err); 902421b20dSDmitry Osipenko goto disable_rpm; 91230630bdSThierry Reding } 92230630bdSThierry Reding 93230630bdSThierry Reding return 0; 94230630bdSThierry Reding 952421b20dSDmitry Osipenko disable_rpm: 962421b20dSDmitry Osipenko pm_runtime_dont_use_autosuspend(client->dev); 972421b20dSDmitry Osipenko pm_runtime_force_suspend(client->dev); 982421b20dSDmitry Osipenko 99aacdf198SThierry Reding host1x_client_iommu_detach(client); 100230630bdSThierry Reding free: 1012aed4f5aSMikko Perttunen host1x_syncpt_put(client->syncpts[0]); 102230630bdSThierry Reding put: 103230630bdSThierry Reding host1x_channel_put(gr3d->channel); 104230630bdSThierry Reding return err; 1055f60ed0dSThierry Reding } 1065f60ed0dSThierry Reding 1075f60ed0dSThierry Reding static int gr3d_exit(struct host1x_client *client) 1085f60ed0dSThierry Reding { 1095f60ed0dSThierry Reding struct tegra_drm_client *drm = host1x_to_drm_client(client); 110608f43adSThierry Reding struct drm_device *dev = dev_get_drvdata(client->host); 1115f60ed0dSThierry Reding struct gr3d *gr3d = to_gr3d(drm); 1125f60ed0dSThierry Reding int err; 1135f60ed0dSThierry Reding 1149910f5c4SThierry Reding err = tegra_drm_unregister_client(dev->dev_private, drm); 1155f60ed0dSThierry Reding if (err < 0) 1165f60ed0dSThierry Reding return err; 1175f60ed0dSThierry Reding 1182421b20dSDmitry Osipenko pm_runtime_dont_use_autosuspend(client->dev); 1192421b20dSDmitry Osipenko pm_runtime_force_suspend(client->dev); 1202421b20dSDmitry Osipenko 121aacdf198SThierry Reding host1x_client_iommu_detach(client); 1222aed4f5aSMikko Perttunen host1x_syncpt_put(client->syncpts[0]); 1238474b025SMikko Perttunen host1x_channel_put(gr3d->channel); 1245f60ed0dSThierry Reding 1252421b20dSDmitry Osipenko gr3d->channel = NULL; 1262421b20dSDmitry Osipenko 1275f60ed0dSThierry Reding return 0; 1285f60ed0dSThierry Reding } 1295f60ed0dSThierry Reding 1305f60ed0dSThierry Reding static const struct host1x_client_ops gr3d_client_ops = { 1315f60ed0dSThierry Reding .init = gr3d_init, 1325f60ed0dSThierry Reding .exit = gr3d_exit, 1335f60ed0dSThierry Reding }; 1345f60ed0dSThierry Reding 1355f60ed0dSThierry Reding static int gr3d_open_channel(struct tegra_drm_client *client, 1365f60ed0dSThierry Reding struct tegra_drm_context *context) 1375f60ed0dSThierry Reding { 1385f60ed0dSThierry Reding struct gr3d *gr3d = to_gr3d(client); 1395f60ed0dSThierry Reding 1405f60ed0dSThierry Reding context->channel = host1x_channel_get(gr3d->channel); 14158ed47adSDmitry Osipenko if (!context->channel) 1425f60ed0dSThierry Reding return -ENOMEM; 1435f60ed0dSThierry Reding 1445f60ed0dSThierry Reding return 0; 1455f60ed0dSThierry Reding } 1465f60ed0dSThierry Reding 1475f60ed0dSThierry Reding static void gr3d_close_channel(struct tegra_drm_context *context) 1485f60ed0dSThierry Reding { 1495f60ed0dSThierry Reding host1x_channel_put(context->channel); 1505f60ed0dSThierry Reding } 1515f60ed0dSThierry Reding 1525f60ed0dSThierry Reding static int gr3d_is_addr_reg(struct device *dev, u32 class, u32 offset) 1535f60ed0dSThierry Reding { 1545f60ed0dSThierry Reding struct gr3d *gr3d = dev_get_drvdata(dev); 1555f60ed0dSThierry Reding 1565f60ed0dSThierry Reding switch (class) { 1575f60ed0dSThierry Reding case HOST1X_CLASS_HOST1X: 1585f60ed0dSThierry Reding if (offset == 0x2b) 1595f60ed0dSThierry Reding return 1; 1605f60ed0dSThierry Reding 1615f60ed0dSThierry Reding break; 1625f60ed0dSThierry Reding 1635f60ed0dSThierry Reding case HOST1X_CLASS_GR3D: 1645f60ed0dSThierry Reding if (offset >= GR3D_NUM_REGS) 1655f60ed0dSThierry Reding break; 1665f60ed0dSThierry Reding 1675f60ed0dSThierry Reding if (test_bit(offset, gr3d->addr_regs)) 1685f60ed0dSThierry Reding return 1; 1695f60ed0dSThierry Reding 1705f60ed0dSThierry Reding break; 1715f60ed0dSThierry Reding } 1725f60ed0dSThierry Reding 1735f60ed0dSThierry Reding return 0; 1745f60ed0dSThierry Reding } 1755f60ed0dSThierry Reding 1765f60ed0dSThierry Reding static const struct tegra_drm_client_ops gr3d_ops = { 1775f60ed0dSThierry Reding .open_channel = gr3d_open_channel, 1785f60ed0dSThierry Reding .close_channel = gr3d_close_channel, 1795f60ed0dSThierry Reding .is_addr_reg = gr3d_is_addr_reg, 1805f60ed0dSThierry Reding .submit = tegra_drm_submit, 1815f60ed0dSThierry Reding }; 1825f60ed0dSThierry Reding 18333f150eaSThierry Reding static const struct gr3d_soc tegra20_gr3d_soc = { 18433f150eaSThierry Reding .version = 0x20, 1852421b20dSDmitry Osipenko .num_clocks = 1, 1862421b20dSDmitry Osipenko .num_resets = 2, 18733f150eaSThierry Reding }; 18833f150eaSThierry Reding 18933f150eaSThierry Reding static const struct gr3d_soc tegra30_gr3d_soc = { 19033f150eaSThierry Reding .version = 0x30, 1912421b20dSDmitry Osipenko .num_clocks = 2, 1922421b20dSDmitry Osipenko .num_resets = 4, 19333f150eaSThierry Reding }; 19433f150eaSThierry Reding 19533f150eaSThierry Reding static const struct gr3d_soc tegra114_gr3d_soc = { 19633f150eaSThierry Reding .version = 0x35, 1972421b20dSDmitry Osipenko .num_clocks = 1, 1982421b20dSDmitry Osipenko .num_resets = 2, 19933f150eaSThierry Reding }; 20033f150eaSThierry Reding 2015f60ed0dSThierry Reding static const struct of_device_id tegra_gr3d_match[] = { 20233f150eaSThierry Reding { .compatible = "nvidia,tegra114-gr3d", .data = &tegra114_gr3d_soc }, 20333f150eaSThierry Reding { .compatible = "nvidia,tegra30-gr3d", .data = &tegra30_gr3d_soc }, 20433f150eaSThierry Reding { .compatible = "nvidia,tegra20-gr3d", .data = &tegra20_gr3d_soc }, 2055f60ed0dSThierry Reding { } 2065f60ed0dSThierry Reding }; 207ef70728cSStephen Warren MODULE_DEVICE_TABLE(of, tegra_gr3d_match); 2085f60ed0dSThierry Reding 2095f60ed0dSThierry Reding static const u32 gr3d_addr_regs[] = { 2105f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 0), 2115f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 1), 2125f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 2), 2135f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 3), 2145f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 4), 2155f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 5), 2165f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 6), 2175f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 7), 2185f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 8), 2195f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 9), 2205f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE(10), 2215f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE(11), 2225f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE(12), 2235f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE(13), 2245f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE(14), 2255f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE(15), 2265f60ed0dSThierry Reding GR3D_IDX_INDEX_BASE, 2275f60ed0dSThierry Reding GR3D_QR_ZTAG_ADDR, 2285f60ed0dSThierry Reding GR3D_QR_CTAG_ADDR, 2295f60ed0dSThierry Reding GR3D_QR_CZ_ADDR, 2305f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 0), 2315f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 1), 2325f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 2), 2335f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 3), 2345f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 4), 2355f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 5), 2365f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 6), 2375f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 7), 2385f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 8), 2395f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 9), 2405f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR(10), 2415f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR(11), 2425f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR(12), 2435f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR(13), 2445f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR(14), 2455f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR(15), 2465f60ed0dSThierry Reding GR3D_DW_MEMORY_OUTPUT_ADDRESS, 2475f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 0), 2485f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 1), 2495f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 2), 2505f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 3), 2515f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 4), 2525f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 5), 2535f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 6), 2545f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 7), 2555f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 8), 2565f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 9), 2575f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR(10), 2585f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR(11), 2595f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR(12), 2605f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR(13), 2615f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR(14), 2625f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR(15), 2635f60ed0dSThierry Reding GR3D_GLOBAL_SPILLSURFADDR, 2645f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 0), 2655f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 1), 2665f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 2), 2675f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 3), 2685f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 4), 2695f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 5), 2705f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 6), 2715f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 7), 2725f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 8), 2735f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 9), 2745f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR(10), 2755f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR(11), 2765f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR(12), 2775f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR(13), 2785f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR(14), 2795f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR(15), 2805f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 0), 2815f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 1), 2825f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 2), 2835f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 3), 2845f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 4), 2855f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 5), 2865f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 6), 2875f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 7), 2885f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 8), 2895f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 9), 2905f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR(10), 2915f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR(11), 2925f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR(12), 2935f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR(13), 2945f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR(14), 2955f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR(15), 2965f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 0), 2975f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 1), 2985f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 2), 2995f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 3), 3005f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 4), 3015f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 5), 3025f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 6), 3035f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 7), 3045f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 8), 3055f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 9), 3065f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR(10), 3075f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR(11), 3085f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR(12), 3095f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR(13), 3105f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR(14), 3115f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR(15), 3125f60ed0dSThierry Reding }; 3135f60ed0dSThierry Reding 3142421b20dSDmitry Osipenko static int gr3d_power_up_legacy_domain(struct device *dev, const char *name, 3152421b20dSDmitry Osipenko unsigned int id) 3162421b20dSDmitry Osipenko { 3172421b20dSDmitry Osipenko struct gr3d *gr3d = dev_get_drvdata(dev); 3182421b20dSDmitry Osipenko struct reset_control *reset; 3192421b20dSDmitry Osipenko struct clk *clk; 3202421b20dSDmitry Osipenko unsigned int i; 3212421b20dSDmitry Osipenko int err; 3222421b20dSDmitry Osipenko 3232421b20dSDmitry Osipenko /* 3242421b20dSDmitry Osipenko * Tegra20 device-tree doesn't specify 3d clock name and there is only 3252421b20dSDmitry Osipenko * one clock for Tegra20. Tegra30+ device-trees always specified names 3262421b20dSDmitry Osipenko * for the clocks. 3272421b20dSDmitry Osipenko */ 3282421b20dSDmitry Osipenko if (gr3d->nclocks == 1) { 3292421b20dSDmitry Osipenko if (id == TEGRA_POWERGATE_3D1) 3302421b20dSDmitry Osipenko return 0; 3312421b20dSDmitry Osipenko 3322421b20dSDmitry Osipenko clk = gr3d->clocks[0].clk; 3332421b20dSDmitry Osipenko } else { 3342421b20dSDmitry Osipenko for (i = 0; i < gr3d->nclocks; i++) { 3352421b20dSDmitry Osipenko if (WARN_ON(!gr3d->clocks[i].id)) 3362421b20dSDmitry Osipenko continue; 3372421b20dSDmitry Osipenko 3382421b20dSDmitry Osipenko if (!strcmp(gr3d->clocks[i].id, name)) { 3392421b20dSDmitry Osipenko clk = gr3d->clocks[i].clk; 3402421b20dSDmitry Osipenko break; 3412421b20dSDmitry Osipenko } 3422421b20dSDmitry Osipenko } 3432421b20dSDmitry Osipenko 3442421b20dSDmitry Osipenko if (WARN_ON(i == gr3d->nclocks)) 3452421b20dSDmitry Osipenko return -EINVAL; 3462421b20dSDmitry Osipenko } 3472421b20dSDmitry Osipenko 3482421b20dSDmitry Osipenko /* 3492421b20dSDmitry Osipenko * We use array of resets, which includes MC resets, and MC 3502421b20dSDmitry Osipenko * reset shouldn't be asserted while hardware is gated because 3512421b20dSDmitry Osipenko * MC flushing will fail for gated hardware. Hence for legacy 3522421b20dSDmitry Osipenko * PD we request the individual reset separately. 3532421b20dSDmitry Osipenko */ 3542421b20dSDmitry Osipenko reset = reset_control_get_exclusive_released(dev, name); 3552421b20dSDmitry Osipenko if (IS_ERR(reset)) 3562421b20dSDmitry Osipenko return PTR_ERR(reset); 3572421b20dSDmitry Osipenko 3582421b20dSDmitry Osipenko err = reset_control_acquire(reset); 3592421b20dSDmitry Osipenko if (err) { 3602421b20dSDmitry Osipenko dev_err(dev, "failed to acquire %s reset: %d\n", name, err); 3612421b20dSDmitry Osipenko } else { 3622421b20dSDmitry Osipenko err = tegra_powergate_sequence_power_up(id, clk, reset); 3632421b20dSDmitry Osipenko reset_control_release(reset); 3642421b20dSDmitry Osipenko } 3652421b20dSDmitry Osipenko 3662421b20dSDmitry Osipenko reset_control_put(reset); 3672421b20dSDmitry Osipenko if (err) 3682421b20dSDmitry Osipenko return err; 3692421b20dSDmitry Osipenko 3702421b20dSDmitry Osipenko /* 3712421b20dSDmitry Osipenko * tegra_powergate_sequence_power_up() leaves clocks enabled, 3722421b20dSDmitry Osipenko * while GENPD not. Hence keep clock-enable balanced. 3732421b20dSDmitry Osipenko */ 3742421b20dSDmitry Osipenko clk_disable_unprepare(clk); 3752421b20dSDmitry Osipenko 3762421b20dSDmitry Osipenko return 0; 3772421b20dSDmitry Osipenko } 3782421b20dSDmitry Osipenko 3792421b20dSDmitry Osipenko static void gr3d_del_link(void *link) 3802421b20dSDmitry Osipenko { 3812421b20dSDmitry Osipenko device_link_del(link); 3822421b20dSDmitry Osipenko } 3832421b20dSDmitry Osipenko 3842421b20dSDmitry Osipenko static int gr3d_init_power(struct device *dev, struct gr3d *gr3d) 3852421b20dSDmitry Osipenko { 3862421b20dSDmitry Osipenko static const char * const opp_genpd_names[] = { "3d0", "3d1", NULL }; 3872421b20dSDmitry Osipenko const u32 link_flags = DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME; 3882421b20dSDmitry Osipenko struct device **opp_virt_devs, *pd_dev; 3892421b20dSDmitry Osipenko struct device_link *link; 3902421b20dSDmitry Osipenko unsigned int i; 3912421b20dSDmitry Osipenko int err; 3922421b20dSDmitry Osipenko 3932421b20dSDmitry Osipenko err = of_count_phandle_with_args(dev->of_node, "power-domains", 3942421b20dSDmitry Osipenko "#power-domain-cells"); 3952421b20dSDmitry Osipenko if (err < 0) { 3962421b20dSDmitry Osipenko if (err != -ENOENT) 3972421b20dSDmitry Osipenko return err; 3982421b20dSDmitry Osipenko 3992421b20dSDmitry Osipenko /* 4002421b20dSDmitry Osipenko * Older device-trees don't use GENPD. In this case we should 4012421b20dSDmitry Osipenko * toggle power domain manually. 4022421b20dSDmitry Osipenko */ 4032421b20dSDmitry Osipenko err = gr3d_power_up_legacy_domain(dev, "3d", 4042421b20dSDmitry Osipenko TEGRA_POWERGATE_3D); 4052421b20dSDmitry Osipenko if (err) 4062421b20dSDmitry Osipenko return err; 4072421b20dSDmitry Osipenko 4082421b20dSDmitry Osipenko err = gr3d_power_up_legacy_domain(dev, "3d2", 4092421b20dSDmitry Osipenko TEGRA_POWERGATE_3D1); 4102421b20dSDmitry Osipenko if (err) 4112421b20dSDmitry Osipenko return err; 4122421b20dSDmitry Osipenko 4132421b20dSDmitry Osipenko return 0; 4142421b20dSDmitry Osipenko } 4152421b20dSDmitry Osipenko 4162421b20dSDmitry Osipenko /* 4172421b20dSDmitry Osipenko * The PM domain core automatically attaches a single power domain, 4182421b20dSDmitry Osipenko * otherwise it skips attaching completely. We have a single domain 4192421b20dSDmitry Osipenko * on Tegra20 and two domains on Tegra30+. 4202421b20dSDmitry Osipenko */ 4212421b20dSDmitry Osipenko if (dev->pm_domain) 4222421b20dSDmitry Osipenko return 0; 4232421b20dSDmitry Osipenko 4242421b20dSDmitry Osipenko err = devm_pm_opp_attach_genpd(dev, opp_genpd_names, &opp_virt_devs); 4252421b20dSDmitry Osipenko if (err) 4262421b20dSDmitry Osipenko return err; 4272421b20dSDmitry Osipenko 4282421b20dSDmitry Osipenko for (i = 0; opp_genpd_names[i]; i++) { 4292421b20dSDmitry Osipenko pd_dev = opp_virt_devs[i]; 4302421b20dSDmitry Osipenko if (!pd_dev) { 4312421b20dSDmitry Osipenko dev_err(dev, "failed to get %s power domain\n", 4322421b20dSDmitry Osipenko opp_genpd_names[i]); 4332421b20dSDmitry Osipenko return -EINVAL; 4342421b20dSDmitry Osipenko } 4352421b20dSDmitry Osipenko 4362421b20dSDmitry Osipenko link = device_link_add(dev, pd_dev, link_flags); 4372421b20dSDmitry Osipenko if (!link) { 4382421b20dSDmitry Osipenko dev_err(dev, "failed to link to %s\n", dev_name(pd_dev)); 4392421b20dSDmitry Osipenko return -EINVAL; 4402421b20dSDmitry Osipenko } 4412421b20dSDmitry Osipenko 4422421b20dSDmitry Osipenko err = devm_add_action_or_reset(dev, gr3d_del_link, link); 4432421b20dSDmitry Osipenko if (err) 4442421b20dSDmitry Osipenko return err; 4452421b20dSDmitry Osipenko } 4462421b20dSDmitry Osipenko 4472421b20dSDmitry Osipenko return 0; 4482421b20dSDmitry Osipenko } 4492421b20dSDmitry Osipenko 4502421b20dSDmitry Osipenko static int gr3d_get_clocks(struct device *dev, struct gr3d *gr3d) 4512421b20dSDmitry Osipenko { 4522421b20dSDmitry Osipenko int err; 4532421b20dSDmitry Osipenko 4542421b20dSDmitry Osipenko err = devm_clk_bulk_get_all(dev, &gr3d->clocks); 4552421b20dSDmitry Osipenko if (err < 0) { 4562421b20dSDmitry Osipenko dev_err(dev, "failed to get clock: %d\n", err); 4572421b20dSDmitry Osipenko return err; 4582421b20dSDmitry Osipenko } 4592421b20dSDmitry Osipenko gr3d->nclocks = err; 4602421b20dSDmitry Osipenko 4612421b20dSDmitry Osipenko if (gr3d->nclocks != gr3d->soc->num_clocks) { 4622421b20dSDmitry Osipenko dev_err(dev, "invalid number of clocks: %u\n", gr3d->nclocks); 4632421b20dSDmitry Osipenko return -ENOENT; 4642421b20dSDmitry Osipenko } 4652421b20dSDmitry Osipenko 4662421b20dSDmitry Osipenko return 0; 4672421b20dSDmitry Osipenko } 4682421b20dSDmitry Osipenko 4692421b20dSDmitry Osipenko static int gr3d_get_resets(struct device *dev, struct gr3d *gr3d) 4702421b20dSDmitry Osipenko { 4712421b20dSDmitry Osipenko int err; 4722421b20dSDmitry Osipenko 4732421b20dSDmitry Osipenko gr3d->resets[RST_MC].id = "mc"; 4742421b20dSDmitry Osipenko gr3d->resets[RST_MC2].id = "mc2"; 4752421b20dSDmitry Osipenko gr3d->resets[RST_GR3D].id = "3d"; 4762421b20dSDmitry Osipenko gr3d->resets[RST_GR3D2].id = "3d2"; 4772421b20dSDmitry Osipenko gr3d->nresets = gr3d->soc->num_resets; 4782421b20dSDmitry Osipenko 4792421b20dSDmitry Osipenko err = devm_reset_control_bulk_get_optional_exclusive_released( 4802421b20dSDmitry Osipenko dev, gr3d->nresets, gr3d->resets); 4812421b20dSDmitry Osipenko if (err) { 4822421b20dSDmitry Osipenko dev_err(dev, "failed to get reset: %d\n", err); 4832421b20dSDmitry Osipenko return err; 4842421b20dSDmitry Osipenko } 4852421b20dSDmitry Osipenko 4862421b20dSDmitry Osipenko if (WARN_ON(!gr3d->resets[RST_GR3D].rstc) || 4872421b20dSDmitry Osipenko WARN_ON(!gr3d->resets[RST_GR3D2].rstc && gr3d->nresets == 4)) 4882421b20dSDmitry Osipenko return -ENOENT; 4892421b20dSDmitry Osipenko 4902421b20dSDmitry Osipenko return 0; 4912421b20dSDmitry Osipenko } 4922421b20dSDmitry Osipenko 4935f60ed0dSThierry Reding static int gr3d_probe(struct platform_device *pdev) 4945f60ed0dSThierry Reding { 4955f60ed0dSThierry Reding struct host1x_syncpt **syncpts; 4965f60ed0dSThierry Reding struct gr3d *gr3d; 4975f60ed0dSThierry Reding unsigned int i; 4985f60ed0dSThierry Reding int err; 4995f60ed0dSThierry Reding 5005f60ed0dSThierry Reding gr3d = devm_kzalloc(&pdev->dev, sizeof(*gr3d), GFP_KERNEL); 5015f60ed0dSThierry Reding if (!gr3d) 5025f60ed0dSThierry Reding return -ENOMEM; 5035f60ed0dSThierry Reding 5042421b20dSDmitry Osipenko platform_set_drvdata(pdev, gr3d); 5052421b20dSDmitry Osipenko 50633f150eaSThierry Reding gr3d->soc = of_device_get_match_data(&pdev->dev); 50733f150eaSThierry Reding 5085f60ed0dSThierry Reding syncpts = devm_kzalloc(&pdev->dev, sizeof(*syncpts), GFP_KERNEL); 5095f60ed0dSThierry Reding if (!syncpts) 5105f60ed0dSThierry Reding return -ENOMEM; 5115f60ed0dSThierry Reding 5122421b20dSDmitry Osipenko err = gr3d_get_clocks(&pdev->dev, gr3d); 5132421b20dSDmitry Osipenko if (err) 5145f60ed0dSThierry Reding return err; 5155f60ed0dSThierry Reding 5162421b20dSDmitry Osipenko err = gr3d_get_resets(&pdev->dev, gr3d); 5172421b20dSDmitry Osipenko if (err) 5185f60ed0dSThierry Reding return err; 5192421b20dSDmitry Osipenko 5202421b20dSDmitry Osipenko err = gr3d_init_power(&pdev->dev, gr3d); 5212421b20dSDmitry Osipenko if (err) 5222421b20dSDmitry Osipenko return err; 5235f60ed0dSThierry Reding 5245f60ed0dSThierry Reding INIT_LIST_HEAD(&gr3d->client.base.list); 5255f60ed0dSThierry Reding gr3d->client.base.ops = &gr3d_client_ops; 5265f60ed0dSThierry Reding gr3d->client.base.dev = &pdev->dev; 5275f60ed0dSThierry Reding gr3d->client.base.class = HOST1X_CLASS_GR3D; 5285f60ed0dSThierry Reding gr3d->client.base.syncpts = syncpts; 5295f60ed0dSThierry Reding gr3d->client.base.num_syncpts = 1; 5305f60ed0dSThierry Reding 5315f60ed0dSThierry Reding INIT_LIST_HEAD(&gr3d->client.list); 53233f150eaSThierry Reding gr3d->client.version = gr3d->soc->version; 5335f60ed0dSThierry Reding gr3d->client.ops = &gr3d_ops; 5345f60ed0dSThierry Reding 5352421b20dSDmitry Osipenko err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 5362421b20dSDmitry Osipenko if (err) 5372421b20dSDmitry Osipenko return err; 5382421b20dSDmitry Osipenko 5395f60ed0dSThierry Reding err = host1x_client_register(&gr3d->client.base); 5405f60ed0dSThierry Reding if (err < 0) { 5415f60ed0dSThierry Reding dev_err(&pdev->dev, "failed to register host1x client: %d\n", 5425f60ed0dSThierry Reding err); 5435f60ed0dSThierry Reding return err; 5445f60ed0dSThierry Reding } 5455f60ed0dSThierry Reding 5465f60ed0dSThierry Reding /* initialize address register map */ 5475f60ed0dSThierry Reding for (i = 0; i < ARRAY_SIZE(gr3d_addr_regs); i++) 5485f60ed0dSThierry Reding set_bit(gr3d_addr_regs[i], gr3d->addr_regs); 5495f60ed0dSThierry Reding 5505f60ed0dSThierry Reding return 0; 5515f60ed0dSThierry Reding } 5525f60ed0dSThierry Reding 553de9fce20SUwe Kleine-König static void gr3d_remove(struct platform_device *pdev) 5545f60ed0dSThierry Reding { 5555f60ed0dSThierry Reding struct gr3d *gr3d = platform_get_drvdata(pdev); 5565f60ed0dSThierry Reding 5571d83d1a2SUwe Kleine-König host1x_client_unregister(&gr3d->client.base); 5585f60ed0dSThierry Reding } 5595f60ed0dSThierry Reding 5602421b20dSDmitry Osipenko static int __maybe_unused gr3d_runtime_suspend(struct device *dev) 5612421b20dSDmitry Osipenko { 5622421b20dSDmitry Osipenko struct gr3d *gr3d = dev_get_drvdata(dev); 5632421b20dSDmitry Osipenko int err; 5642421b20dSDmitry Osipenko 5652421b20dSDmitry Osipenko host1x_channel_stop(gr3d->channel); 5662421b20dSDmitry Osipenko 5672421b20dSDmitry Osipenko err = reset_control_bulk_assert(gr3d->nresets, gr3d->resets); 5682421b20dSDmitry Osipenko if (err) { 5692421b20dSDmitry Osipenko dev_err(dev, "failed to assert reset: %d\n", err); 5702421b20dSDmitry Osipenko return err; 5712421b20dSDmitry Osipenko } 5722421b20dSDmitry Osipenko 5732421b20dSDmitry Osipenko usleep_range(10, 20); 5742421b20dSDmitry Osipenko 5752421b20dSDmitry Osipenko /* 5762421b20dSDmitry Osipenko * Older device-trees don't specify MC resets and power-gating can't 5772421b20dSDmitry Osipenko * be done safely in that case. Hence we will keep the power ungated 5782421b20dSDmitry Osipenko * for older DTBs. For newer DTBs, GENPD will perform the power-gating. 5792421b20dSDmitry Osipenko */ 5802421b20dSDmitry Osipenko 5812421b20dSDmitry Osipenko clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks); 5822421b20dSDmitry Osipenko reset_control_bulk_release(gr3d->nresets, gr3d->resets); 5835f60ed0dSThierry Reding 5845f60ed0dSThierry Reding return 0; 5855f60ed0dSThierry Reding } 5865f60ed0dSThierry Reding 5872421b20dSDmitry Osipenko static int __maybe_unused gr3d_runtime_resume(struct device *dev) 5882421b20dSDmitry Osipenko { 5892421b20dSDmitry Osipenko struct gr3d *gr3d = dev_get_drvdata(dev); 5902421b20dSDmitry Osipenko int err; 5912421b20dSDmitry Osipenko 5922421b20dSDmitry Osipenko err = reset_control_bulk_acquire(gr3d->nresets, gr3d->resets); 5932421b20dSDmitry Osipenko if (err) { 5942421b20dSDmitry Osipenko dev_err(dev, "failed to acquire reset: %d\n", err); 5952421b20dSDmitry Osipenko return err; 5962421b20dSDmitry Osipenko } 5972421b20dSDmitry Osipenko 5982421b20dSDmitry Osipenko err = clk_bulk_prepare_enable(gr3d->nclocks, gr3d->clocks); 5992421b20dSDmitry Osipenko if (err) { 6002421b20dSDmitry Osipenko dev_err(dev, "failed to enable clock: %d\n", err); 6012421b20dSDmitry Osipenko goto release_reset; 6022421b20dSDmitry Osipenko } 6032421b20dSDmitry Osipenko 6042421b20dSDmitry Osipenko err = reset_control_bulk_deassert(gr3d->nresets, gr3d->resets); 6052421b20dSDmitry Osipenko if (err) { 6062421b20dSDmitry Osipenko dev_err(dev, "failed to deassert reset: %d\n", err); 6072421b20dSDmitry Osipenko goto disable_clk; 6082421b20dSDmitry Osipenko } 6092421b20dSDmitry Osipenko 6102421b20dSDmitry Osipenko return 0; 6112421b20dSDmitry Osipenko 6122421b20dSDmitry Osipenko disable_clk: 6132421b20dSDmitry Osipenko clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks); 6142421b20dSDmitry Osipenko release_reset: 6152421b20dSDmitry Osipenko reset_control_bulk_release(gr3d->nresets, gr3d->resets); 6162421b20dSDmitry Osipenko 6172421b20dSDmitry Osipenko return err; 6182421b20dSDmitry Osipenko } 6192421b20dSDmitry Osipenko 6202421b20dSDmitry Osipenko static const struct dev_pm_ops tegra_gr3d_pm = { 6212421b20dSDmitry Osipenko SET_RUNTIME_PM_OPS(gr3d_runtime_suspend, gr3d_runtime_resume, NULL) 6222421b20dSDmitry Osipenko SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 6232421b20dSDmitry Osipenko pm_runtime_force_resume) 6242421b20dSDmitry Osipenko }; 6252421b20dSDmitry Osipenko 6265f60ed0dSThierry Reding struct platform_driver tegra_gr3d_driver = { 6275f60ed0dSThierry Reding .driver = { 6285f60ed0dSThierry Reding .name = "tegra-gr3d", 6295f60ed0dSThierry Reding .of_match_table = tegra_gr3d_match, 6302421b20dSDmitry Osipenko .pm = &tegra_gr3d_pm, 6315f60ed0dSThierry Reding }, 6325f60ed0dSThierry Reding .probe = gr3d_probe, 633de9fce20SUwe Kleine-König .remove_new = gr3d_remove, 6345f60ed0dSThierry Reding }; 635